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This drives every native > active-low chip select low until tegra_spi_setup() runs for that device. > > SPI children are registered and probed one at a time. A synchronous > probe of an earlier child can therefore transfer while a later child's > chip select is still asserted. On a Tegra234 system with active-low devices > on CS0 and CS1, this caused both devices to be selected when the CS1 > device probed first. Its initialization then intermittently failed. A > logic analyzer showed CS0 remained low throughout the CS1 transfer and > went high only after the CS1 probe failed. What about the case where the SPI devices CS is active high or a mixture of the two? > The Tegra234 TRM also documents all CS_POL_INACTIVE bits as one after > reset, so the existing probe code replaces the hardware's safe reset > polarity with zeros on that SoC. > > Set CS_POL_INACTIVE for all native chip selects during controller probe. > This matches SPI's default active-low polarity and the documented > Tegra234 reset polarity. tegra_spi_setup() continues to configure the > inactive polarity of SPI_CS_HIGH devices before their drivers probe. > > Fixes: f333a331adfa ("spi/tegra114: add spi driver") > Assisted-by: Codex:GPT-5 > Signed-off-by: Abraham Zukor > --- > drivers/spi/spi-tegra114.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c > index aa44ffd09e61..c28aae093d57 100644 > --- a/drivers/spi/spi-tegra114.c > +++ b/drivers/spi/spi-tegra114.c > @@ -1394,7 +1394,7 @@ static int tegra_spi_probe(struct platform_device *pdev) > reset_control_assert(tspi->rst); > udelay(2); > reset_control_deassert(tspi->rst); > - tspi->def_command1_reg = SPI_M_S; > + tspi->def_command1_reg = SPI_M_S | SPI_CS_POL_INACTIVE_MASK; > tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); > tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); > tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); -- nvpublic