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X-CSE-ConnectionGUID: xkXKbOmlQV2aXwZj+808kA== X-CSE-MsgGUID: hvBw41w6TYW6cAkDjtY7Fw== X-IronPort-AV: E=Sophos;i="6.20,231,1758610800"; d="scan'208";a="217099809" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2025 08:50:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.29; Thu, 27 Nov 2025 08:49:45 -0700 Received: from [10.205.167.104] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 27 Nov 2025 08:49:43 -0700 Message-ID: Date: Thu, 27 Nov 2025 16:00:47 +0000 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] spi: microchip-core: Use SPI_MODE_X_MASK To: Andy Shevchenko , , CC: Mark Brown , Conor Dooley - M52691 , Prajna Rajendra Kumar - M74368 References: <20251126075558.2035012-1-andriy.shevchenko@linux.intel.com> <20251126075558.2035012-6-andriy.shevchenko@linux.intel.com> Content-Language: en-US From: Prajna Rajendra Kumar In-Reply-To: <20251126075558.2035012-6-andriy.shevchenko@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 26/11/2025 07:54, Andy Shevchenko wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Use SPI_MODE_X_MASK instead of open coded variant. > > Signed-off-by: Andy Shevchenko Reviewed-by: Prajna Rajendra Kumar > --- > drivers/spi/spi-microchip-core-spi.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/spi/spi-microchip-core-spi.c b/drivers/spi/spi-microchip-core-spi.c > index 0dca46dcdc2f..941b7e23eac3 100644 > --- a/drivers/spi/spi-microchip-core-spi.c > +++ b/drivers/spi/spi-microchip-core-spi.c > @@ -148,8 +148,6 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable) > > static int mchp_corespi_setup(struct spi_device *spi) > { > - u32 dev_mode = spi->mode & (SPI_CPOL | SPI_CPHA); > - > if (spi_get_csgpiod(spi, 0)) > return 0; > > @@ -158,7 +156,7 @@ static int mchp_corespi_setup(struct spi_device *spi) > return -EOPNOTSUPP; > } > > - if (dev_mode & ~spi->controller->mode_bits) { > + if (spi->mode & SPI_MODE_X_MASK & ~spi->controller->mode_bits) { > dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Motorola mode\n"); > return -EINVAL; > } > -- > 2.50.1 >