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Thu, 30 Jan 2025 10:58:48 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A74564002D; Thu, 30 Jan 2025 10:57:32 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7F9F72EC5C3; Thu, 30 Jan 2025 10:48:08 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 30 Jan 2025 10:48:07 +0100 Message-ID: Date: Thu, 30 Jan 2025 10:48:07 +0100 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/9] dt-bindings: spi: Add STM32 OSPI controller To: Krzysztof Kozlowski , Conor Dooley CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon , , , , , , References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> <20250128081731.2284457-2-patrice.chotard@foss.st.com> <20250128-panama-manly-a753d91c297c@spud> <20250129-annoying-flawless-porpoise-47daed@krzk-bin> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <20250129-annoying-flawless-porpoise-47daed@krzk-bin> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-30_06,2025-01-30_01,2024-11-22_01 On 1/29/25 08:40, Krzysztof Kozlowski wrote: > On Tue, Jan 28, 2025 at 06:02:27PM +0000, Conor Dooley wrote: >>> + st,syscfg-dlyb: >>> + description: phandle to syscon block >>> + Use to set the OSPI delay block within syscon to >>> + tune the phase of the RX sampling clock (or DQS) in order >>> + to sample the data in their valid window and to >>> + tune the phase of the TX launch clock in order to meet setup >>> + and hold constraints of TX signals versus the memory clock. >>> + $ref: /schemas/types.yaml#/definitions/phandle-array >> >> Why do you need a phandle here? I assume looking up by compatible ain't >> possible because you have multiple controllers on the SoC? Also, I don't >> think your copy-paste "phandle to" stuff here is accurate: >> st,syscfg-dlyb = <&syscfg 0x1000>; >> There's an offset here that you don't mention in your description. > > This needs double items: and listing them with description, instead of > free form text. ok, i will remove most of ths text description and update as following : st,syscfg-dlyb: description: configure OCTOSPI delay block. $ref: /schemas/types.yaml#/definitions/phandle-array items: - description: phandle to syscfg - description: register offset within syscfg Thanks Patrice > > Best regards, > Krzysztof >