Regression on max controller CS lines

[Luis de Arquer <ldearquer@gmail.com>]

Hi,

After commit 4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b "spi: Add multi-cs memories support in SPI core":

The code parsing device tree for a spi device seems to impose a limit on the number of cs lines for the *controller*.
From the commit:

@@ -2295,14 +2385,53 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
        return 0;
    }
 
+   if (ctlr->num_chipselect > SPI_CS_CNT_MAX) {
+       dev_err(&ctlr->dev, "No. of CS is more than max. no. of supported CS\n");
+       return -EINVAL;
+   }
+

(Note that, if I am not wrong, of_spi_parse_dt() is parsing the device tree for the device, not the controller)

Why limiting ctlr->num_chipselect to SPI_CS_CNT_MAX (4)? And why do the check here (if any, do it in spi_register_controller()) ? If I understand correctly, SPI_CS_CNT_MAX is the maximum number of cs
lines on the spi peripheral using parallel mode, but that should not imply a restriction on the controller itself.

I have seen this has been discussed already[1], but rather than increasing SPI_CS_CNT_MAX, isn't it better to remove this check altogether?

(I ended up here because I am using a board with 12 CS gpio lines, and this change broke it)

[1] https://lore.kernel.org/all/d3c93c4c-3754-480c-84c2-9455ec8af702@roeck-us.net/

Luis