[PATCH 0/6] SPI ThunderX driver

[PATCH 0/6] SPI ThunderX driver

[Jan Glauber]

Hi Mark,

This series adds support for SPI on Cavium's ThunderX (arm64). The SPI
hardware is the same as on MIPS Octeon, the only difference is that the
device appears as a PCI device. To avoid copy and paste of the Octeon
driver I've moved the common parts into a shared file.

Patches #1-5 prepare the Octeon driver for re-use.

Patch #6 adds the ThunderX driver.

The series was tested on MIPS (Edge Router PRO and cn71xx) and ThunderX.

Feedback welcome!

thanks,
Jan

Jan Glauber (5):
  spi: octeon: Store system clock freqency in struct octeon_spi
  spi: octeon: Put register offsets into a struct
  spi: octeon: Move include file from arch/mips to drivers/spi
  spi: octeon: Split driver into Octeon specific and common parts
  spi: octeon: Add thunderx driver

Steven J. Hill (1):
  spi: octeon: Convert driver to use readq()/writeq() functions

 drivers/spi/Kconfig                                |   7 +
 drivers/spi/Makefile                               |   3 +
 drivers/spi/spi-cavium-octeon.c                    | 104 +++++++++
 drivers/spi/spi-cavium-thunderx.c                  | 158 +++++++++++++
 drivers/spi/spi-cavium.c                           | 151 ++++++++++++
 .../cvmx-mpi-defs.h => drivers/spi/spi-cavium.h    |  62 ++---
 drivers/spi/spi-octeon.c                           | 255 ---------------------
 7 files changed, 456 insertions(+), 284 deletions(-)
 create mode 100644 drivers/spi/spi-cavium-octeon.c
 create mode 100644 drivers/spi/spi-cavium-thunderx.c
 create mode 100644 drivers/spi/spi-cavium.c
 rename arch/mips/include/asm/octeon/cvmx-mpi-defs.h => drivers/spi/spi-cavium.h (84%)
 delete mode 100644 drivers/spi/spi-octeon.c

-- 
2.9.0.rc0.21.g7777322

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[PATCH 1/6] spi: octeon: Convert driver to use readq()/writeq() functions

[Jan Glauber]

From: "Steven J. Hill" <steven.hill@cavium.com>

Remove all calls to cvmx_read_csr()/cvmx_write_csr() and use
the portable readq()/writeq() functions.

Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
 drivers/spi/spi-octeon.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 3b17009..b53ba53 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -27,7 +27,7 @@
 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
 
 struct octeon_spi {
-	u64 register_base;
+	void __iomem *register_base;
 	u64 last_cfg;
 	u64 cs_enax;
 };
@@ -40,7 +40,7 @@ static void octeon_spi_wait_ready(struct octeon_spi *p)
 	do {
 		if (loops++)
 			__delay(500);
-		mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS);
+		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS);
 	} while (mpi_sts.s.busy);
 }
 
@@ -85,7 +85,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 
 	if (mpi_cfg.u64 != p->last_cfg) {
 		p->last_cfg = mpi_cfg.u64;
-		cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64);
+		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG);
 	}
 	tx_buf = xfer->tx_buf;
 	rx_buf = xfer->rx_buf;
@@ -97,19 +97,19 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 				d = *tx_buf++;
 			else
 				d = 0;
-			cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
+			writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 		}
 		mpi_tx.u64 = 0;
 		mpi_tx.s.csid = spi->chip_select;
 		mpi_tx.s.leavecs = 1;
 		mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
 		mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
-		cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
+		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
 
 		octeon_spi_wait_ready(p);
 		if (rx_buf)
 			for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
-				u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+				u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 				*rx_buf++ = (u8)v;
 			}
 		len -= OCTEON_SPI_MAX_BYTES;
@@ -121,7 +121,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 			d = *tx_buf++;
 		else
 			d = 0;
-		cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
+		writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 	}
 
 	mpi_tx.u64 = 0;
@@ -132,12 +132,12 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 		mpi_tx.s.leavecs = !xfer->cs_change;
 	mpi_tx.s.txnum = tx_buf ? len : 0;
 	mpi_tx.s.totnum = len;
-	cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
+	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
 
 	octeon_spi_wait_ready(p);
 	if (rx_buf)
 		for (i = 0; i < len; i++) {
-			u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+			u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
 			*rx_buf++ = (u8)v;
 		}
 
@@ -193,7 +193,7 @@ static int octeon_spi_probe(struct platform_device *pdev)
 		goto fail;
 	}
 
-	p->register_base = (u64)reg_base;
+	p->register_base = reg_base;
 
 	master->num_chipselect = 4;
 	master->mode_bits = SPI_CPHA |
@@ -225,10 +225,9 @@ static int octeon_spi_remove(struct platform_device *pdev)
 {
 	struct spi_master *master = platform_get_drvdata(pdev);
 	struct octeon_spi *p = spi_master_get_devdata(master);
-	u64 register_base = p->register_base;
 
 	/* Clear the CSENA* and put everything in a known state. */
-	cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0);
+	writeq(0, p->register_base + OCTEON_SPI_CFG);
 
 	return 0;
 }
-- 
2.9.0.rc0.21.g7777322

[PATCH 2/6] spi: octeon: Store system clock freqency in struct octeon_spi

[Jan Glauber]

Storing the system clock frequency in struct octeon_spi avoids
calling the MIPS specific octeon_get_io_clock_rate() for every transfer.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
---
 drivers/spi/spi-octeon.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index b53ba53..e722040 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -30,6 +30,7 @@ struct octeon_spi {
 	void __iomem *register_base;
 	u64 last_cfg;
 	u64 cs_enax;
+	int sys_freq;
 };
 
 static void octeon_spi_wait_ready(struct octeon_spi *p)
@@ -53,7 +54,6 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 	union cvmx_mpi_cfg mpi_cfg;
 	union cvmx_mpi_tx mpi_tx;
 	unsigned int clkdiv;
-	unsigned int speed_hz;
 	int mode;
 	bool cpha, cpol;
 	const u8 *tx_buf;
@@ -65,9 +65,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 	cpha = mode & SPI_CPHA;
 	cpol = mode & SPI_CPOL;
 
-	speed_hz = xfer->speed_hz;
-
-	clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
+	clkdiv = p->sys_freq / (2 * xfer->speed_hz);
 
 	mpi_cfg.u64 = 0;
 
@@ -194,6 +192,7 @@ static int octeon_spi_probe(struct platform_device *pdev)
 	}
 
 	p->register_base = reg_base;
+	p->sys_freq = octeon_get_io_clock_rate();
 
 	master->num_chipselect = 4;
 	master->mode_bits = SPI_CPHA |
-- 
2.9.0.rc0.21.g7777322

[PATCH 3/6] spi: octeon: Put register offsets into a struct

[Jan Glauber]

Instead of hard-coding the register offsets put them into a struct
and set them in the probe function.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
---
 drivers/spi/spi-octeon.c | 41 +++++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index e722040..209eddc 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -17,22 +17,30 @@
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-mpi-defs.h>
 
-#define OCTEON_SPI_CFG 0
-#define OCTEON_SPI_STS 0x08
-#define OCTEON_SPI_TX 0x10
-#define OCTEON_SPI_DAT0 0x80
-
 #define OCTEON_SPI_MAX_BYTES 9
 
 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
 
+struct octeon_spi_regs {
+	int config;
+	int status;
+	int tx;
+	int data;
+};
+
 struct octeon_spi {
 	void __iomem *register_base;
 	u64 last_cfg;
 	u64 cs_enax;
 	int sys_freq;
+	struct octeon_spi_regs regs;
 };
 
+#define OCTEON_SPI_CFG(x)	(x->regs.config)
+#define OCTEON_SPI_STS(x)	(x->regs.status)
+#define OCTEON_SPI_TX(x)	(x->regs.tx)
+#define OCTEON_SPI_DAT0(x)	(x->regs.data)
+
 static void octeon_spi_wait_ready(struct octeon_spi *p)
 {
 	union cvmx_mpi_sts mpi_sts;
@@ -41,7 +49,7 @@ static void octeon_spi_wait_ready(struct octeon_spi *p)
 	do {
 		if (loops++)
 			__delay(500);
-		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS);
+		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
 	} while (mpi_sts.s.busy);
 }
 
@@ -83,7 +91,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 
 	if (mpi_cfg.u64 != p->last_cfg) {
 		p->last_cfg = mpi_cfg.u64;
-		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG);
+		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
 	}
 	tx_buf = xfer->tx_buf;
 	rx_buf = xfer->rx_buf;
@@ -95,19 +103,19 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 				d = *tx_buf++;
 			else
 				d = 0;
-			writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+			writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
 		}
 		mpi_tx.u64 = 0;
 		mpi_tx.s.csid = spi->chip_select;
 		mpi_tx.s.leavecs = 1;
 		mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
 		mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
-		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
+		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
 
 		octeon_spi_wait_ready(p);
 		if (rx_buf)
 			for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
-				u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+				u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
 				*rx_buf++ = (u8)v;
 			}
 		len -= OCTEON_SPI_MAX_BYTES;
@@ -119,7 +127,7 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 			d = *tx_buf++;
 		else
 			d = 0;
-		writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+		writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
 	}
 
 	mpi_tx.u64 = 0;
@@ -130,12 +138,12 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 		mpi_tx.s.leavecs = !xfer->cs_change;
 	mpi_tx.s.txnum = tx_buf ? len : 0;
 	mpi_tx.s.totnum = len;
-	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
+	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
 
 	octeon_spi_wait_ready(p);
 	if (rx_buf)
 		for (i = 0; i < len; i++) {
-			u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
+			u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
 			*rx_buf++ = (u8)v;
 		}
 
@@ -194,6 +202,11 @@ static int octeon_spi_probe(struct platform_device *pdev)
 	p->register_base = reg_base;
 	p->sys_freq = octeon_get_io_clock_rate();
 
+	p->regs.config = 0;
+	p->regs.status = 0x08;
+	p->regs.tx = 0x10;
+	p->regs.data = 0x80;
+
 	master->num_chipselect = 4;
 	master->mode_bits = SPI_CPHA |
 			    SPI_CPOL |
@@ -226,7 +239,7 @@ static int octeon_spi_remove(struct platform_device *pdev)
 	struct octeon_spi *p = spi_master_get_devdata(master);
 
 	/* Clear the CSENA* and put everything in a known state. */
-	writeq(0, p->register_base + OCTEON_SPI_CFG);
+	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
 
 	return 0;
 }
-- 
2.9.0.rc0.21.g7777322

[PATCH 4/6] spi: octeon: Move include file from arch/mips to drivers/spi

[Jan Glauber]

Move the register definitions to the drivers directory because they
are only used there.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
---
 .../cvmx-mpi-defs.h => drivers/spi/spi-cavium.h    | 32 +---------------------
 drivers/spi/spi-octeon.c                           |  3 +-
 2 files changed, 3 insertions(+), 32 deletions(-)
 rename arch/mips/include/asm/octeon/cvmx-mpi-defs.h => drivers/spi/spi-cavium.h (84%)

diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/drivers/spi/spi-cavium.h
similarity index 84%
rename from arch/mips/include/asm/octeon/cvmx-mpi-defs.h
rename to drivers/spi/spi-cavium.h
index 4615b10..d41dba5 100644
--- a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
+++ b/drivers/spi/spi-cavium.h
@@ -1,32 +1,4 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_MPI_DEFS_H__
-#define __CVMX_MPI_DEFS_H__
+/* MPI register descriptions */
 
 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
@@ -324,5 +296,3 @@ union cvmx_mpi_tx {
 	struct cvmx_mpi_tx_s cn66xx;
 	struct cvmx_mpi_tx_cn61xx cnf71xx;
 };
-
-#endif
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
index 209eddc..2180176 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-octeon.c
@@ -15,7 +15,8 @@
 #include <linux/of.h>
 
 #include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-mpi-defs.h>
+
+#include "spi-cavium.h"
 
 #define OCTEON_SPI_MAX_BYTES 9
 
-- 
2.9.0.rc0.21.g7777322

[PATCH 5/6] spi: octeon: Split driver into Octeon specific and common parts

[Jan Glauber]

Separate driver probing from SPI transfer functions.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
---
 drivers/spi/Makefile                       |   1 +
 drivers/spi/spi-cavium-octeon.c            | 104 +++++++++++++++++++++++++
 drivers/spi/{spi-octeon.c => spi-cavium.c} | 120 +----------------------------
 drivers/spi/spi-cavium.h                   |  31 ++++++++
 4 files changed, 138 insertions(+), 118 deletions(-)
 create mode 100644 drivers/spi/spi-cavium-octeon.c
 rename drivers/spi/{spi-octeon.c => spi-cavium.c} (55%)

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3c74d00..185367e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
+spi-octeon-objs				:= spi-cavium.o spi-cavium-octeon.o
 obj-$(CONFIG_SPI_OCTEON)		+= spi-octeon.o
 obj-$(CONFIG_SPI_OMAP_UWIRE)		+= spi-omap-uwire.o
 obj-$(CONFIG_SPI_OMAP_100K)		+= spi-omap-100k.o
diff --git a/drivers/spi/spi-cavium-octeon.c b/drivers/spi/spi-cavium-octeon.c
new file mode 100644
index 0000000..ee4703e
--- /dev/null
+++ b/drivers/spi/spi-cavium-octeon.c
@@ -0,0 +1,104 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011, 2012 Cavium, Inc.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "spi-cavium.h"
+
+static int octeon_spi_probe(struct platform_device *pdev)
+{
+	struct resource *res_mem;
+	void __iomem *reg_base;
+	struct spi_master *master;
+	struct octeon_spi *p;
+	int err = -ENOENT;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
+	if (!master)
+		return -ENOMEM;
+	p = spi_master_get_devdata(master);
+	platform_set_drvdata(pdev, master);
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(reg_base)) {
+		err = PTR_ERR(reg_base);
+		goto fail;
+	}
+
+	p->register_base = reg_base;
+	p->sys_freq = octeon_get_io_clock_rate();
+
+	p->regs.config = 0;
+	p->regs.status = 0x08;
+	p->regs.tx = 0x10;
+	p->regs.data = 0x80;
+
+	master->num_chipselect = 4;
+	master->mode_bits = SPI_CPHA |
+			    SPI_CPOL |
+			    SPI_CS_HIGH |
+			    SPI_LSB_FIRST |
+			    SPI_3WIRE;
+
+	master->transfer_one_message = octeon_spi_transfer_one_message;
+	master->bits_per_word_mask = SPI_BPW_MASK(8);
+	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
+
+	master->dev.of_node = pdev->dev.of_node;
+	err = devm_spi_register_master(&pdev->dev, master);
+	if (err) {
+		dev_err(&pdev->dev, "register master failed: %d\n", err);
+		goto fail;
+	}
+
+	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
+
+	return 0;
+fail:
+	spi_master_put(master);
+	return err;
+}
+
+static int octeon_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct octeon_spi *p = spi_master_get_devdata(master);
+
+	/* Clear the CSENA* and put everything in a known state. */
+	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
+
+	return 0;
+}
+
+static const struct of_device_id octeon_spi_match[] = {
+	{ .compatible = "cavium,octeon-3010-spi", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, octeon_spi_match);
+
+static struct platform_driver octeon_spi_driver = {
+	.driver = {
+		.name		= "spi-octeon",
+		.of_match_table = octeon_spi_match,
+	},
+	.probe		= octeon_spi_probe,
+	.remove		= octeon_spi_remove,
+};
+
+module_platform_driver(octeon_spi_driver);
+
+MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
+MODULE_AUTHOR("David Daney");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-cavium.c
similarity index 55%
rename from drivers/spi/spi-octeon.c
rename to drivers/spi/spi-cavium.c
index 2180176..5aaf215 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-cavium.c
@@ -6,42 +6,13 @@
  * Copyright (C) 2011, 2012 Cavium, Inc.
  */
 
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/of.h>
-
-#include <asm/octeon/octeon.h>
 
 #include "spi-cavium.h"
 
-#define OCTEON_SPI_MAX_BYTES 9
-
-#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
-
-struct octeon_spi_regs {
-	int config;
-	int status;
-	int tx;
-	int data;
-};
-
-struct octeon_spi {
-	void __iomem *register_base;
-	u64 last_cfg;
-	u64 cs_enax;
-	int sys_freq;
-	struct octeon_spi_regs regs;
-};
-
-#define OCTEON_SPI_CFG(x)	(x->regs.config)
-#define OCTEON_SPI_STS(x)	(x->regs.status)
-#define OCTEON_SPI_TX(x)	(x->regs.tx)
-#define OCTEON_SPI_DAT0(x)	(x->regs.data)
-
 static void octeon_spi_wait_ready(struct octeon_spi *p)
 {
 	union cvmx_mpi_sts mpi_sts;
@@ -154,8 +125,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 	return xfer->len;
 }
 
-static int octeon_spi_transfer_one_message(struct spi_master *master,
-					   struct spi_message *msg)
+int octeon_spi_transfer_one_message(struct spi_master *master,
+				    struct spi_message *msg)
 {
 	struct octeon_spi *p = spi_master_get_devdata(master);
 	unsigned int total_len = 0;
@@ -178,90 +149,3 @@ err:
 	spi_finalize_current_message(master);
 	return status;
 }
-
-static int octeon_spi_probe(struct platform_device *pdev)
-{
-	struct resource *res_mem;
-	void __iomem *reg_base;
-	struct spi_master *master;
-	struct octeon_spi *p;
-	int err = -ENOENT;
-
-	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
-	if (!master)
-		return -ENOMEM;
-	p = spi_master_get_devdata(master);
-	platform_set_drvdata(pdev, master);
-
-	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
-	if (IS_ERR(reg_base)) {
-		err = PTR_ERR(reg_base);
-		goto fail;
-	}
-
-	p->register_base = reg_base;
-	p->sys_freq = octeon_get_io_clock_rate();
-
-	p->regs.config = 0;
-	p->regs.status = 0x08;
-	p->regs.tx = 0x10;
-	p->regs.data = 0x80;
-
-	master->num_chipselect = 4;
-	master->mode_bits = SPI_CPHA |
-			    SPI_CPOL |
-			    SPI_CS_HIGH |
-			    SPI_LSB_FIRST |
-			    SPI_3WIRE;
-
-	master->transfer_one_message = octeon_spi_transfer_one_message;
-	master->bits_per_word_mask = SPI_BPW_MASK(8);
-	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
-
-	master->dev.of_node = pdev->dev.of_node;
-	err = devm_spi_register_master(&pdev->dev, master);
-	if (err) {
-		dev_err(&pdev->dev, "register master failed: %d\n", err);
-		goto fail;
-	}
-
-	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
-
-	return 0;
-fail:
-	spi_master_put(master);
-	return err;
-}
-
-static int octeon_spi_remove(struct platform_device *pdev)
-{
-	struct spi_master *master = platform_get_drvdata(pdev);
-	struct octeon_spi *p = spi_master_get_devdata(master);
-
-	/* Clear the CSENA* and put everything in a known state. */
-	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
-
-	return 0;
-}
-
-static const struct of_device_id octeon_spi_match[] = {
-	{ .compatible = "cavium,octeon-3010-spi", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, octeon_spi_match);
-
-static struct platform_driver octeon_spi_driver = {
-	.driver = {
-		.name		= "spi-octeon",
-		.of_match_table = octeon_spi_match,
-	},
-	.probe		= octeon_spi_probe,
-	.remove		= octeon_spi_remove,
-};
-
-module_platform_driver(octeon_spi_driver);
-
-MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
-MODULE_AUTHOR("David Daney");
-MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-cavium.h b/drivers/spi/spi-cavium.h
index d41dba5..88c5f36 100644
--- a/drivers/spi/spi-cavium.h
+++ b/drivers/spi/spi-cavium.h
@@ -1,3 +1,32 @@
+#ifndef __SPI_CAVIUM_H
+#define __SPI_CAVIUM_H
+
+#define OCTEON_SPI_MAX_BYTES 9
+#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
+
+struct octeon_spi_regs {
+	int config;
+	int status;
+	int tx;
+	int data;
+};
+
+struct octeon_spi {
+	void __iomem *register_base;
+	u64 last_cfg;
+	u64 cs_enax;
+	int sys_freq;
+	struct octeon_spi_regs regs;
+};
+
+#define OCTEON_SPI_CFG(x)	(x->regs.config)
+#define OCTEON_SPI_STS(x)	(x->regs.status)
+#define OCTEON_SPI_TX(x)	(x->regs.tx)
+#define OCTEON_SPI_DAT0(x)	(x->regs.data)
+
+int octeon_spi_transfer_one_message(struct spi_master *master,
+				    struct spi_message *msg);
+
 /* MPI register descriptions */
 
 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
@@ -296,3 +325,5 @@ union cvmx_mpi_tx {
 	struct cvmx_mpi_tx_s cn66xx;
 	struct cvmx_mpi_tx_cn61xx cnf71xx;
 };
+
+#endif /* __SPI_CAVIUM_H */
-- 
2.9.0.rc0.21.g7777322

Re: [PATCH 5/6] spi: octeon: Split driver into Octeon specific and common parts

[Paul Gortmaker]

On Sat, Jul 23, 2016 at 6:42 AM, Jan Glauber <jglauber@cavium.com> wrote:
> Separate driver probing from SPI transfer functions.
>
> Signed-off-by: Jan Glauber <jglauber@cavium.com>
> Tested-by: Steven J. Hill <steven.hill@cavium.com>
> ---
>  drivers/spi/Makefile                       |   1 +
>  drivers/spi/spi-cavium-octeon.c            | 104 +++++++++++++++++++++++++
>  drivers/spi/{spi-octeon.c => spi-cavium.c} | 120 +----------------------------
>  drivers/spi/spi-cavium.h                   |  31 ++++++++
>  4 files changed, 138 insertions(+), 118 deletions(-)
>  create mode 100644 drivers/spi/spi-cavium-octeon.c
>  rename drivers/spi/{spi-octeon.c => spi-cavium.c} (55%)
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 3c74d00..185367e 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
>  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
>  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
>  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
> +spi-octeon-objs                                := spi-cavium.o spi-cavium-octeon.o
>  obj-$(CONFIG_SPI_OCTEON)               += spi-octeon.o
>  obj-$(CONFIG_SPI_OMAP_UWIRE)           += spi-omap-uwire.o
>  obj-$(CONFIG_SPI_OMAP_100K)            += spi-omap-100k.o
> diff --git a/drivers/spi/spi-cavium-octeon.c b/drivers/spi/spi-cavium-octeon.c
> new file mode 100644
> index 0000000..ee4703e
> --- /dev/null
> +++ b/drivers/spi/spi-cavium-octeon.c
> @@ -0,0 +1,104 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 2011, 2012 Cavium, Inc.
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/spi/spi.h>
> +#include <linux/module.h>
> +#include <linux/io.h>
> +#include <linux/of.h>

[...]

> +MODULE_DEVICE_TABLE(of, octeon_spi_match);
> +
> +static struct platform_driver octeon_spi_driver = {
> +       .driver = {
> +               .name           = "spi-octeon",
> +               .of_match_table = octeon_spi_match,
> +       },
> +       .probe          = octeon
_spi_probe,
> +       .remove         = octeon_spi_remove,
> +};
> +
> +module_platform_driver(octeon_spi_driver);
> +
> +MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
> +MODULE_AUTHOR("David Daney");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-cavium.c
> similarity index 55%
> rename from drivers/spi/spi-octeon.c
> rename to drivers/spi/spi-cavium.c
> index 2180176..5aaf215 100644
> --- a/drivers/spi/spi-octeon.c
> +++ b/drivers/spi/spi-cavium.c
> @@ -6,42 +6,13 @@
>   * Copyright (C) 2011, 2012 Cavium, Inc.
>   */
>
> -#include <linux/platform_device.h>
> -#include <linux/interrupt.h>
>  #include <linux/spi/spi.h>
>  #include <linux/module.h>

It almost looks like all the modular stuff got moved to the new file and
maybe the above module.h isn't needed in the original file anymore?

Paul.
--

>  #include <linux/delay.h>
>  #include <linux/io.h>
> -#include <linux/of.h>
> -
> -#include <asm/octeon/octeon.h>
>
>  #include "spi-cavium.h"

[...]

Re: [PATCH 5/6] spi: octeon: Split driver into Octeon specific and common parts

[Jan Glauber]

On Sun, Jul 24, 2016 at 02:38:11PM -0400, Paul Gortmaker wrote:
> On Sat, Jul 23, 2016 at 6:42 AM, Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> wrote:
> > Separate driver probing from SPI transfer functions.
> >
> > Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> > Tested-by: Steven J. Hill <steven.hill-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> > ---
> >  drivers/spi/Makefile                       |   1 +
> >  drivers/spi/spi-cavium-octeon.c            | 104 +++++++++++++++++++++++++
> >  drivers/spi/{spi-octeon.c => spi-cavium.c} | 120 +----------------------------
> >  drivers/spi/spi-cavium.h                   |  31 ++++++++
> >  4 files changed, 138 insertions(+), 118 deletions(-)
> >  create mode 100644 drivers/spi/spi-cavium-octeon.c
> >  rename drivers/spi/{spi-octeon.c => spi-cavium.c} (55%)
> >
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index 3c74d00..185367e 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
> >  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
> >  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
> >  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
> > +spi-octeon-objs                                := spi-cavium.o spi-cavium-octeon.o
> >  obj-$(CONFIG_SPI_OCTEON)               += spi-octeon.o
> >  obj-$(CONFIG_SPI_OMAP_UWIRE)           += spi-omap-uwire.o
> >  obj-$(CONFIG_SPI_OMAP_100K)            += spi-omap-100k.o
> > diff --git a/drivers/spi/spi-cavium-octeon.c b/drivers/spi/spi-cavium-octeon.c
> > new file mode 100644
> > index 0000000..ee4703e
> > --- /dev/null
> > +++ b/drivers/spi/spi-cavium-octeon.c
> > @@ -0,0 +1,104 @@
> > +/*
> > + * This file is subject to the terms and conditions of the GNU General Public
> > + * License.  See the file "COPYING" in the main directory of this archive
> > + * for more details.
> > + *
> > + * Copyright (C) 2011, 2012 Cavium, Inc.
> > + */
> > +
> > +#include <linux/platform_device.h>
> > +#include <linux/spi/spi.h>
> > +#include <linux/module.h>
> > +#include <linux/io.h>
> > +#include <linux/of.h>
> 
> [...]
> 
> > +MODULE_DEVICE_TABLE(of, octeon_spi_match);
> > +
> > +static struct platform_driver octeon_spi_driver = {
> > +       .driver = {
> > +               .name           = "spi-octeon",
> > +               .of_match_table = octeon_spi_match,
> > +       },
> > +       .probe          = octeon
> _spi_probe,
> > +       .remove         = octeon_spi_remove,
> > +};
> > +
> > +module_platform_driver(octeon_spi_driver);
> > +
> > +MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
> > +MODULE_AUTHOR("David Daney");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-cavium.c
> > similarity index 55%
> > rename from drivers/spi/spi-octeon.c
> > rename to drivers/spi/spi-cavium.c
> > index 2180176..5aaf215 100644
> > --- a/drivers/spi/spi-octeon.c
> > +++ b/drivers/spi/spi-cavium.c
> > @@ -6,42 +6,13 @@
> >   * Copyright (C) 2011, 2012 Cavium, Inc.
> >   */
> >
> > -#include <linux/platform_device.h>
> > -#include <linux/interrupt.h>
> >  #include <linux/spi/spi.h>
> >  #include <linux/module.h>
> 
> It almost looks like all the modular stuff got moved to the new file and
> maybe the above module.h isn't needed in the original file anymore?
> 
> Paul.
> --

Yes, that can be removed. Also io.h isn't needed there.

thanks,
Jan

> >  #include <linux/delay.h>
> >  #include <linux/io.h>
> > -#include <linux/of.h>
> > -
> > -#include <asm/octeon/octeon.h>
> >
> >  #include "spi-cavium.h"
> 
> [...]
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Re: [PATCH 5/6] spi: octeon: Split driver into Octeon specific and common parts

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 147 bytes --]

On Sat, Jul 23, 2016 at 12:42:54PM +0200, Jan Glauber wrote:

> +	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");

This is just noise, remove it.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

Re: [PATCH 5/6] spi: octeon: Split driver into Octeon specific and common parts

[Jan Glauber]

On Sun, Jul 24, 2016 at 09:54:16PM +0100, Mark Brown wrote:
> On Sat, Jul 23, 2016 at 12:42:54PM +0200, Jan Glauber wrote:
> 
> > +	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
> 
> This is just noise, remove it.

I'll remove these in both drivers.

Thanks,
Jan
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[PATCH v2] spi: octeon: Split driver into Octeon specific and common parts

[Jan Glauber]

Separate driver probing from SPI transfer functions.

Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
---
 drivers/spi/Makefile                       |   1 +
 drivers/spi/spi-cavium-octeon.c            | 102 ++++++++++++++++++++++++
 drivers/spi/{spi-octeon.c => spi-cavium.c} | 122 +----------------------------
 drivers/spi/spi-cavium.h                   |  31 ++++++++
 4 files changed, 136 insertions(+), 120 deletions(-)
 create mode 100644 drivers/spi/spi-cavium-octeon.c
 rename drivers/spi/{spi-octeon.c => spi-cavium.c} (54%)

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3c74d00..185367e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
+spi-octeon-objs				:= spi-cavium.o spi-cavium-octeon.o
 obj-$(CONFIG_SPI_OCTEON)		+= spi-octeon.o
 obj-$(CONFIG_SPI_OMAP_UWIRE)		+= spi-omap-uwire.o
 obj-$(CONFIG_SPI_OMAP_100K)		+= spi-omap-100k.o
diff --git a/drivers/spi/spi-cavium-octeon.c b/drivers/spi/spi-cavium-octeon.c
new file mode 100644
index 0000000..97310c1
--- /dev/null
+++ b/drivers/spi/spi-cavium-octeon.c
@@ -0,0 +1,102 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011, 2012 Cavium, Inc.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "spi-cavium.h"
+
+static int octeon_spi_probe(struct platform_device *pdev)
+{
+	struct resource *res_mem;
+	void __iomem *reg_base;
+	struct spi_master *master;
+	struct octeon_spi *p;
+	int err = -ENOENT;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
+	if (!master)
+		return -ENOMEM;
+	p = spi_master_get_devdata(master);
+	platform_set_drvdata(pdev, master);
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
+	if (IS_ERR(reg_base)) {
+		err = PTR_ERR(reg_base);
+		goto fail;
+	}
+
+	p->register_base = reg_base;
+	p->sys_freq = octeon_get_io_clock_rate();
+
+	p->regs.config = 0;
+	p->regs.status = 0x08;
+	p->regs.tx = 0x10;
+	p->regs.data = 0x80;
+
+	master->num_chipselect = 4;
+	master->mode_bits = SPI_CPHA |
+			    SPI_CPOL |
+			    SPI_CS_HIGH |
+			    SPI_LSB_FIRST |
+			    SPI_3WIRE;
+
+	master->transfer_one_message = octeon_spi_transfer_one_message;
+	master->bits_per_word_mask = SPI_BPW_MASK(8);
+	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
+
+	master->dev.of_node = pdev->dev.of_node;
+	err = devm_spi_register_master(&pdev->dev, master);
+	if (err) {
+		dev_err(&pdev->dev, "register master failed: %d\n", err);
+		goto fail;
+	}
+
+	return 0;
+fail:
+	spi_master_put(master);
+	return err;
+}
+
+static int octeon_spi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct octeon_spi *p = spi_master_get_devdata(master);
+
+	/* Clear the CSENA* and put everything in a known state. */
+	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
+
+	return 0;
+}
+
+static const struct of_device_id octeon_spi_match[] = {
+	{ .compatible = "cavium,octeon-3010-spi", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, octeon_spi_match);
+
+static struct platform_driver octeon_spi_driver = {
+	.driver = {
+		.name		= "spi-octeon",
+		.of_match_table = octeon_spi_match,
+	},
+	.probe		= octeon_spi_probe,
+	.remove		= octeon_spi_remove,
+};
+
+module_platform_driver(octeon_spi_driver);
+
+MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
+MODULE_AUTHOR("David Daney");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-cavium.c
similarity index 54%
rename from drivers/spi/spi-octeon.c
rename to drivers/spi/spi-cavium.c
index 2180176..8857e7d 100644
--- a/drivers/spi/spi-octeon.c
+++ b/drivers/spi/spi-cavium.c
@@ -6,42 +6,11 @@
  * Copyright (C) 2011, 2012 Cavium, Inc.
  */
 
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
 #include <linux/spi/spi.h>
-#include <linux/module.h>
 #include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/of.h>
-
-#include <asm/octeon/octeon.h>
 
 #include "spi-cavium.h"
 
-#define OCTEON_SPI_MAX_BYTES 9
-
-#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
-
-struct octeon_spi_regs {
-	int config;
-	int status;
-	int tx;
-	int data;
-};
-
-struct octeon_spi {
-	void __iomem *register_base;
-	u64 last_cfg;
-	u64 cs_enax;
-	int sys_freq;
-	struct octeon_spi_regs regs;
-};
-
-#define OCTEON_SPI_CFG(x)	(x->regs.config)
-#define OCTEON_SPI_STS(x)	(x->regs.status)
-#define OCTEON_SPI_TX(x)	(x->regs.tx)
-#define OCTEON_SPI_DAT0(x)	(x->regs.data)
-
 static void octeon_spi_wait_ready(struct octeon_spi *p)
 {
 	union cvmx_mpi_sts mpi_sts;
@@ -154,8 +123,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
 	return xfer->len;
 }
 
-static int octeon_spi_transfer_one_message(struct spi_master *master,
-					   struct spi_message *msg)
+int octeon_spi_transfer_one_message(struct spi_master *master,
+				    struct spi_message *msg)
 {
 	struct octeon_spi *p = spi_master_get_devdata(master);
 	unsigned int total_len = 0;
@@ -178,90 +147,3 @@ err:
 	spi_finalize_current_message(master);
 	return status;
 }
-
-static int octeon_spi_probe(struct platform_device *pdev)
-{
-	struct resource *res_mem;
-	void __iomem *reg_base;
-	struct spi_master *master;
-	struct octeon_spi *p;
-	int err = -ENOENT;
-
-	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
-	if (!master)
-		return -ENOMEM;
-	p = spi_master_get_devdata(master);
-	platform_set_drvdata(pdev, master);
-
-	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
-	if (IS_ERR(reg_base)) {
-		err = PTR_ERR(reg_base);
-		goto fail;
-	}
-
-	p->register_base = reg_base;
-	p->sys_freq = octeon_get_io_clock_rate();
-
-	p->regs.config = 0;
-	p->regs.status = 0x08;
-	p->regs.tx = 0x10;
-	p->regs.data = 0x80;
-
-	master->num_chipselect = 4;
-	master->mode_bits = SPI_CPHA |
-			    SPI_CPOL |
-			    SPI_CS_HIGH |
-			    SPI_LSB_FIRST |
-			    SPI_3WIRE;
-
-	master->transfer_one_message = octeon_spi_transfer_one_message;
-	master->bits_per_word_mask = SPI_BPW_MASK(8);
-	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
-
-	master->dev.of_node = pdev->dev.of_node;
-	err = devm_spi_register_master(&pdev->dev, master);
-	if (err) {
-		dev_err(&pdev->dev, "register master failed: %d\n", err);
-		goto fail;
-	}
-
-	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
-
-	return 0;
-fail:
-	spi_master_put(master);
-	return err;
-}
-
-static int octeon_spi_remove(struct platform_device *pdev)
-{
-	struct spi_master *master = platform_get_drvdata(pdev);
-	struct octeon_spi *p = spi_master_get_devdata(master);
-
-	/* Clear the CSENA* and put everything in a known state. */
-	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
-
-	return 0;
-}
-
-static const struct of_device_id octeon_spi_match[] = {
-	{ .compatible = "cavium,octeon-3010-spi", },
-	{},
-};
-MODULE_DEVICE_TABLE(of, octeon_spi_match);
-
-static struct platform_driver octeon_spi_driver = {
-	.driver = {
-		.name		= "spi-octeon",
-		.of_match_table = octeon_spi_match,
-	},
-	.probe		= octeon_spi_probe,
-	.remove		= octeon_spi_remove,
-};
-
-module_platform_driver(octeon_spi_driver);
-
-MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
-MODULE_AUTHOR("David Daney");
-MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-cavium.h b/drivers/spi/spi-cavium.h
index d41dba5..88c5f36 100644
--- a/drivers/spi/spi-cavium.h
+++ b/drivers/spi/spi-cavium.h
@@ -1,3 +1,32 @@
+#ifndef __SPI_CAVIUM_H
+#define __SPI_CAVIUM_H
+
+#define OCTEON_SPI_MAX_BYTES 9
+#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
+
+struct octeon_spi_regs {
+	int config;
+	int status;
+	int tx;
+	int data;
+};
+
+struct octeon_spi {
+	void __iomem *register_base;
+	u64 last_cfg;
+	u64 cs_enax;
+	int sys_freq;
+	struct octeon_spi_regs regs;
+};
+
+#define OCTEON_SPI_CFG(x)	(x->regs.config)
+#define OCTEON_SPI_STS(x)	(x->regs.status)
+#define OCTEON_SPI_TX(x)	(x->regs.tx)
+#define OCTEON_SPI_DAT0(x)	(x->regs.data)
+
+int octeon_spi_transfer_one_message(struct spi_master *master,
+				    struct spi_message *msg);
+
 /* MPI register descriptions */
 
 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
@@ -296,3 +325,5 @@ union cvmx_mpi_tx {
 	struct cvmx_mpi_tx_s cn66xx;
 	struct cvmx_mpi_tx_cn61xx cnf71xx;
 };
+
+#endif /* __SPI_CAVIUM_H */
-- 
2.9.0.rc0.21.g7777322

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[PATCH 6/6] spi: octeon: Add thunderx driver

[Jan Glauber]

Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
 drivers/spi/Kconfig               |   7 ++
 drivers/spi/Makefile              |   2 +
 drivers/spi/spi-cavium-thunderx.c | 158 ++++++++++++++++++++++++++++++++++++++
 drivers/spi/spi-cavium.h          |   3 +
 4 files changed, 170 insertions(+)
 create mode 100644 drivers/spi/spi-cavium-thunderx.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4b931ec..db02ba7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -630,6 +630,13 @@ config SPI_TEGRA20_SLINK
 	help
 	  SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
 
+config SPI_THUNDERX
+	tristate "Cavium ThunderX SPI controller"
+	depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC
+	help
+	  SPI host driver for the hardware found on Cavium ThunderX
+	  SOCs.
+
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
 	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 185367e..133364b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -91,6 +91,8 @@ obj-$(CONFIG_SPI_TEGRA114)		+= spi-tegra114.o
 obj-$(CONFIG_SPI_TEGRA20_SFLASH)	+= spi-tegra20-sflash.o
 obj-$(CONFIG_SPI_TEGRA20_SLINK)		+= spi-tegra20-slink.o
 obj-$(CONFIG_SPI_TLE62X0)		+= spi-tle62x0.o
+spi-thunderx-objs			:= spi-cavium.o spi-cavium-thunderx.o
+obj-$(CONFIG_SPI_THUNDERX)		+= spi-thunderx.o
 obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
 obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
 obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
diff --git a/drivers/spi/spi-cavium-thunderx.c b/drivers/spi/spi-cavium-thunderx.c
new file mode 100644
index 0000000..7eb9141
--- /dev/null
+++ b/drivers/spi/spi-cavium-thunderx.c
@@ -0,0 +1,158 @@
+/*
+ * Cavium ThunderX SPI driver.
+ *
+ * Copyright (C) 2016 Cavium Inc.
+ * Authors: Jan Glauber <jglauber@cavium.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+
+#include "spi-cavium.h"
+
+#define DRV_NAME "spi-thunderx"
+
+#define SYS_FREQ_DEFAULT		700000000
+
+static void thunderx_spi_clock_enable(struct device *dev, struct octeon_spi *p)
+{
+	int ret;
+
+	p->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(p->clk)) {
+		p->clk = NULL;
+		goto skip;
+	}
+
+	ret = clk_prepare_enable(p->clk);
+	if (ret)
+		goto skip;
+	p->sys_freq = clk_get_rate(p->clk);
+
+skip:
+	if (!p->sys_freq)
+		p->sys_freq = SYS_FREQ_DEFAULT;
+
+	dev_info(dev, "Set system clock to %u\n", p->sys_freq);
+}
+
+static void thunderx_spi_clock_disable(struct device *dev, struct clk *clk)
+{
+	if (!clk)
+		return;
+	clk_disable_unprepare(clk);
+	devm_clk_put(dev, clk);
+}
+
+static int thunderx_spi_probe(struct pci_dev *pdev,
+			      const struct pci_device_id *ent)
+{
+	struct device *dev = &pdev->dev;
+	struct spi_master *master;
+	struct octeon_spi *p;
+	int ret = -ENOENT;
+
+	master = spi_alloc_master(dev, sizeof(struct octeon_spi));
+	if (!master)
+		return -ENOMEM;
+	p = spi_master_get_devdata(master);
+
+	ret = pci_enable_device(pdev);
+	if (ret) {
+		dev_err(dev, "Failed to enable PCI device\n");
+		goto out_free;
+	}
+
+	ret = pci_request_regions(pdev, DRV_NAME);
+	if (ret) {
+		dev_err(dev, "PCI request regions failed 0x%x\n", ret);
+		goto out_disable;
+	}
+
+	p->register_base = pci_ioremap_bar(pdev, 0);
+	if (!p->register_base) {
+		dev_err(dev, "Cannot map reg base\n");
+		ret = -EINVAL;
+		goto out_region;
+	}
+
+	p->regs.config = 0x1000;
+	p->regs.status = 0x1008;
+	p->regs.tx = 0x1010;
+	p->regs.data = 0x1080;
+
+	thunderx_spi_clock_enable(dev, p);
+
+	master->num_chipselect = 4;
+	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
+			    SPI_LSB_FIRST | SPI_3WIRE;
+	master->transfer_one_message = octeon_spi_transfer_one_message;
+	master->bits_per_word_mask = SPI_BPW_MASK(8);
+	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
+	master->dev.of_node = pdev->dev.of_node;
+
+	pci_set_drvdata(pdev, master);
+	ret = devm_spi_register_master(dev, master);
+	if (ret) {
+		dev_err(&pdev->dev, "Register master failed: %d\n", ret);
+		goto out_unmap;
+	}
+
+	dev_info(&pdev->dev, "Cavium SPI bus driver probed\n");
+	return 0;
+
+out_unmap:
+	thunderx_spi_clock_disable(dev, p->clk);
+	iounmap(p->register_base);
+out_region:
+	pci_release_regions(pdev);
+out_disable:
+	pci_disable_device(pdev);
+out_free:
+	spi_master_put(master);
+	return ret;
+}
+
+static void thunderx_spi_remove(struct pci_dev *pdev)
+{
+	struct spi_master *master = pci_get_drvdata(pdev);
+	struct octeon_spi *p;
+
+	p = spi_master_get_devdata(master);
+	if (!p)
+		return;
+
+	/* Put everything in a known state. */
+	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
+
+	thunderx_spi_clock_disable(&pdev->dev, p->clk);
+	iounmap(p->register_base);
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+	pci_set_drvdata(pdev, NULL);
+}
+
+#define PCI_DEVICE_ID_THUNDERX_SPI      0xa00b
+
+static const struct pci_device_id thunderx_spi_pci_id_table[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDERX_SPI) },
+	{ 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
+
+static struct pci_driver thunderx_spi_driver = {
+	.name		= DRV_NAME,
+	.id_table	= thunderx_spi_pci_id_table,
+	.probe		= thunderx_spi_probe,
+	.remove		= thunderx_spi_remove,
+};
+
+module_pci_driver(thunderx_spi_driver);
+
+MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
+MODULE_AUTHOR("Jan Glauber");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-cavium.h b/drivers/spi/spi-cavium.h
index 88c5f36..1f91d61 100644
--- a/drivers/spi/spi-cavium.h
+++ b/drivers/spi/spi-cavium.h
@@ -1,6 +1,8 @@
 #ifndef __SPI_CAVIUM_H
 #define __SPI_CAVIUM_H
 
+#include <linux/clk.h>
+
 #define OCTEON_SPI_MAX_BYTES 9
 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
 
@@ -17,6 +19,7 @@ struct octeon_spi {
 	u64 cs_enax;
 	int sys_freq;
 	struct octeon_spi_regs regs;
+	struct clk *clk;
 };
 
 #define OCTEON_SPI_CFG(x)	(x->regs.config)
-- 
2.9.0.rc0.21.g7777322

Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1524 bytes --]

On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:

> +config SPI_THUNDERX
> +	tristate "Cavium ThunderX SPI controller"
> +	depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC

This is a *weird* and most likely broken set of dependencies - why
exclude this if we're on Octeon (or Octeon happens to have been enabled
in a config)?

> +static void thunderx_spi_clock_enable(struct device *dev, struct octeon_spi *p)
> +{
> +	int ret;
> +
> +	p->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(p->clk)) {
> +		p->clk = NULL;
> +		goto skip;
> +	}

This is really not clever - we should be requesting clocks on probe, not
only when we're trying to enable them, and using devm_ outside of probe
paths is usually a warning sign too.  Now, this is actually called from
probe so it works out fine but obviously it'd be better to improve the
power management to only enable the clock when needed and at that point
this function will be used and we'll fall into a bad pattern.

Given how tiny this function is and that we've not bothered splitting
out any of the other resource acquisition it's probably better to just
inline it into probe.

> +	dev_info(&pdev->dev, "Cavium SPI bus driver probed\n");

Again, this is just adding noise to the boot log.

> +#define PCI_DEVICE_ID_THUNDERX_SPI      0xa00b
> +
> +static const struct pci_device_id thunderx_spi_pci_id_table[] = {
> +	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDERX_SPI) },
> +	{ 0, }
> +};

The define for the device ID doesn't seem to be adding much here.

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Jan Glauber]

On Sun, Jul 24, 2016 at 10:04:52PM +0100, Mark Brown wrote:
> On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:
> 
> > +config SPI_THUNDERX
> > +	tristate "Cavium ThunderX SPI controller"
> > +	depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC
> 
> This is a *weird* and most likely broken set of dependencies - why
> exclude this if we're on Octeon (or Octeon happens to have been enabled
> in a config)?

I agree that it looks weird, the reasoning is that we would like
to avoid making the driver depend on something like ARCH_THUNDER.

So I made the driver depend on the things it actually uses
(PCI for probing and 64BIT because of readq/writeq) and don't care if it
compiles on other platforms too (like x86).

That said, I can remove the !CAVIUM_OCTEON_SOC, it compiles without
errors on MIPS too. Would that be ok?

> > +static void thunderx_spi_clock_enable(struct device *dev, struct octeon_spi *p)
> > +{
> > +	int ret;
> > +
> > +	p->clk = devm_clk_get(dev, NULL);
> > +	if (IS_ERR(p->clk)) {
> > +		p->clk = NULL;
> > +		goto skip;
> > +	}
> 
> This is really not clever - we should be requesting clocks on probe, not
> only when we're trying to enable them, and using devm_ outside of probe
> paths is usually a warning sign too.  Now, this is actually called from
> probe so it works out fine but obviously it'd be better to improve the
> power management to only enable the clock when needed and at that point
> this function will be used and we'll fall into a bad pattern.
> 
> Given how tiny this function is and that we've not bothered splitting
> out any of the other resource acquisition it's probably better to just
> inline it into probe.

OK, I'll merge it into the probe function.

> > +	dev_info(&pdev->dev, "Cavium SPI bus driver probed\n");
> 
> Again, this is just adding noise to the boot log.
> 
> > +#define PCI_DEVICE_ID_THUNDERX_SPI      0xa00b
> > +
> > +static const struct pci_device_id thunderx_spi_pci_id_table[] = {
> > +	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDERX_SPI) },
> > +	{ 0, }
> > +};
> 
> The define for the device ID doesn't seem to be adding much here.

I find it more readable instead of PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b),
or did I miss your point?

thanks,
Jan
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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1056 bytes --]

On Mon, Jul 25, 2016 at 05:51:22PM +0200, Jan Glauber wrote:
> On Sun, Jul 24, 2016 at 10:04:52PM +0100, Mark Brown wrote:
> > On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:

> > > +	depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC

> > This is a *weird* and most likely broken set of dependencies - why
> > exclude this if we're on Octeon (or Octeon happens to have been enabled
> > in a config)?

> I agree that it looks weird, the reasoning is that we would like
> to avoid making the driver depend on something like ARCH_THUNDER.

Why?

> So I made the driver depend on the things it actually uses
> (PCI for probing and 64BIT because of readq/writeq) and don't care if it
> compiles on other platforms too (like x86).

The usual pattern would be something like (ARCH_THUNDER || COMPILE_TEST)
&& PCI && 64BIT (so that people on other platforms where the device will
never actually appear don't get bothered by the prompt).

> That said, I can remove the !CAVIUM_OCTEON_SOC, it compiles without
> errors on MIPS too. Would that be ok?

Sure.

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[David Daney]

On 07/25/2016 09:16 AM, Mark Brown wrote:
> On Mon, Jul 25, 2016 at 05:51:22PM +0200, Jan Glauber wrote:
>> On Sun, Jul 24, 2016 at 10:04:52PM +0100, Mark Brown wrote:
>>> On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:
>
>>>> +	depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC
>
>>> This is a *weird* and most likely broken set of dependencies - why
>>> exclude this if we're on Octeon (or Octeon happens to have been enabled
>>> in a config)?
>
>> I agree that it looks weird, the reasoning is that we would like
>> to avoid making the driver depend on something like ARCH_THUNDER.
>
> Why?
>
>> So I made the driver depend on the things it actually uses
>> (PCI for probing and 64BIT because of readq/writeq) and don't care if it
>> compiles on other platforms too (like x86).
>
> The usual pattern would be something like (ARCH_THUNDER || COMPILE_TEST)
> && PCI && 64BIT (so that people on other platforms where the device will
> never actually appear don't get bothered by the prompt).

ARCH_THUNDER needs to die, so perhaps it should be (ARM64 || 
COMPILE_TEST) && PCI && 64BIT if you really want to hide it from 
non-arm64 kernel configs.


>
>> That said, I can remove the !CAVIUM_OCTEON_SOC, it compiles without
>> errors on MIPS too. Would that be ok?
>
> Sure.
>

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[PATCH v2] spi: octeon: Add thunderx driver

[Jan Glauber]

Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
 drivers/spi/Kconfig               |   7 ++
 drivers/spi/Makefile              |   2 +
 drivers/spi/spi-cavium-thunderx.c | 140 ++++++++++++++++++++++++++++++++++++++
 drivers/spi/spi-cavium.h          |   3 +
 4 files changed, 152 insertions(+)
 create mode 100644 drivers/spi/spi-cavium-thunderx.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4b931ec..e0ee112 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -630,6 +630,13 @@ config SPI_TEGRA20_SLINK
 	help
 	  SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
 
+config SPI_THUNDERX
+	tristate "Cavium ThunderX SPI controller"
+	depends on (ARM64 || CONFIG_TEST) && 64BIT && PCI
+	help
+	  SPI host driver for the hardware found on Cavium ThunderX
+	  SOCs.
+
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
 	depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 185367e..133364b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -91,6 +91,8 @@ obj-$(CONFIG_SPI_TEGRA114)		+= spi-tegra114.o
 obj-$(CONFIG_SPI_TEGRA20_SFLASH)	+= spi-tegra20-sflash.o
 obj-$(CONFIG_SPI_TEGRA20_SLINK)		+= spi-tegra20-slink.o
 obj-$(CONFIG_SPI_TLE62X0)		+= spi-tle62x0.o
+spi-thunderx-objs			:= spi-cavium.o spi-cavium-thunderx.o
+obj-$(CONFIG_SPI_THUNDERX)		+= spi-thunderx.o
 obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
 obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
 obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
diff --git a/drivers/spi/spi-cavium-thunderx.c b/drivers/spi/spi-cavium-thunderx.c
new file mode 100644
index 0000000..28c3dcc
--- /dev/null
+++ b/drivers/spi/spi-cavium-thunderx.c
@@ -0,0 +1,140 @@
+/*
+ * Cavium ThunderX SPI driver.
+ *
+ * Copyright (C) 2016 Cavium Inc.
+ * Authors: Jan Glauber <jglauber@cavium.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+
+#include "spi-cavium.h"
+
+#define DRV_NAME "spi-thunderx"
+
+#define SYS_FREQ_DEFAULT 700000000 /* 700 Mhz */
+
+static int thunderx_spi_probe(struct pci_dev *pdev,
+			      const struct pci_device_id *ent)
+{
+	struct device *dev = &pdev->dev;
+	struct spi_master *master;
+	struct octeon_spi *p;
+	int ret = -ENOENT;
+
+	master = spi_alloc_master(dev, sizeof(struct octeon_spi));
+	if (!master)
+		return -ENOMEM;
+	p = spi_master_get_devdata(master);
+
+	ret = pci_enable_device(pdev);
+	if (ret) {
+		dev_err(dev, "Failed to enable PCI device\n");
+		goto out_free;
+	}
+
+	ret = pci_request_regions(pdev, DRV_NAME);
+	if (ret) {
+		dev_err(dev, "PCI request regions failed 0x%x\n", ret);
+		goto out_disable;
+	}
+
+	p->register_base = pci_ioremap_bar(pdev, 0);
+	if (!p->register_base) {
+		dev_err(dev, "Cannot map reg base\n");
+		ret = -EINVAL;
+		goto out_region;
+	}
+
+	p->regs.config = 0x1000;
+	p->regs.status = 0x1008;
+	p->regs.tx = 0x1010;
+	p->regs.data = 0x1080;
+
+	p->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(p->clk))
+		goto out_unmap;
+
+	ret = clk_prepare_enable(p->clk);
+	if (ret)
+		goto out_clock_devm;
+
+	p->sys_freq = clk_get_rate(p->clk);
+	if (!p->sys_freq)
+		p->sys_freq = SYS_FREQ_DEFAULT;
+	dev_info(dev, "Set system clock to %u\n", p->sys_freq);
+
+	master->num_chipselect = 4;
+	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
+			    SPI_LSB_FIRST | SPI_3WIRE;
+	master->transfer_one_message = octeon_spi_transfer_one_message;
+	master->bits_per_word_mask = SPI_BPW_MASK(8);
+	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
+	master->dev.of_node = pdev->dev.of_node;
+
+	pci_set_drvdata(pdev, master);
+	ret = devm_spi_register_master(dev, master);
+	if (ret) {
+		dev_err(&pdev->dev, "Register master failed: %d\n", ret);
+		goto out_clock;
+	}
+
+	return 0;
+
+out_clock:
+	clk_disable_unprepare(p->clk);
+out_clock_devm:
+	devm_clk_put(dev, p->clk);
+out_unmap:
+	iounmap(p->register_base);
+out_region:
+	pci_release_regions(pdev);
+out_disable:
+	pci_disable_device(pdev);
+out_free:
+	spi_master_put(master);
+	return ret;
+}
+
+static void thunderx_spi_remove(struct pci_dev *pdev)
+{
+	struct spi_master *master = pci_get_drvdata(pdev);
+	struct octeon_spi *p;
+
+	p = spi_master_get_devdata(master);
+	if (!p)
+		return;
+
+	/* Put everything in a known state. */
+	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
+
+	clk_disable_unprepare(p->clk);
+	devm_clk_put(&pdev->dev, p->clk);
+	iounmap(p->register_base);
+	pci_release_regions(pdev);
+	pci_disable_device(pdev);
+	pci_set_drvdata(pdev, NULL);
+}
+
+static const struct pci_device_id thunderx_spi_pci_id_table[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b) },
+	{ 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
+
+static struct pci_driver thunderx_spi_driver = {
+	.name		= DRV_NAME,
+	.id_table	= thunderx_spi_pci_id_table,
+	.probe		= thunderx_spi_probe,
+	.remove		= thunderx_spi_remove,
+};
+
+module_pci_driver(thunderx_spi_driver);
+
+MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
+MODULE_AUTHOR("Jan Glauber");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-cavium.h b/drivers/spi/spi-cavium.h
index 88c5f36..1f91d61 100644
--- a/drivers/spi/spi-cavium.h
+++ b/drivers/spi/spi-cavium.h
@@ -1,6 +1,8 @@
 #ifndef __SPI_CAVIUM_H
 #define __SPI_CAVIUM_H
 
+#include <linux/clk.h>
+
 #define OCTEON_SPI_MAX_BYTES 9
 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
 
@@ -17,6 +19,7 @@ struct octeon_spi {
 	u64 cs_enax;
 	int sys_freq;
 	struct octeon_spi_regs regs;
+	struct clk *clk;
 };
 
 #define OCTEON_SPI_CFG(x)	(x->regs.config)
-- 
2.9.0.rc0.21.g7777322

Re: [PATCH v2] spi: octeon: Add thunderx driver

[Mark Brown]

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On Mon, Jul 25, 2016 at 07:56:22PM +0200, Jan Glauber wrote:
> Add ThunderX SPI driver using the shared part from the Octeon
> driver. The main difference of the ThunderX driver is that it
> is a PCI device so probing is different. The system clock settings
> can be specified in device tree.

Don't send individual patches in reply to the middle of threads, it
makes it really confusing what's going on.  I now have multiple patches
from you for this driver completely unthreaded in my inbox with no
indication of ordering or anything.  Please resend anything that's
pending as a proper patch series.

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Re: [PATCH v2] spi: octeon: Add thunderx driver

[Jan Glauber]

On Wed, Jul 27, 2016 at 07:08:24PM +0100, Mark Brown wrote:
> On Mon, Jul 25, 2016 at 07:56:22PM +0200, Jan Glauber wrote:
> > Add ThunderX SPI driver using the shared part from the Octeon
> > driver. The main difference of the ThunderX driver is that it
> > is a PCI device so probing is different. The system clock settings
> > can be specified in device tree.
> 
> Don't send individual patches in reply to the middle of threads, it
> makes it really confusing what's going on.  I now have multiple patches
> from you for this driver completely unthreaded in my inbox with no
> indication of ordering or anything.  Please resend anything that's
> pending as a proper patch series.

With multiple being exactly two. I thought it to be easier this way
around and the ordering to be obvious (if you use threading),
but of course I can resend the two patches as a new series.
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Re: [PATCH v2] spi: octeon: Add thunderx driver

[Mark Brown]

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On Thu, Jul 28, 2016 at 10:12:55AM +0200, Jan Glauber wrote:
> On Wed, Jul 27, 2016 at 07:08:24PM +0100, Mark Brown wrote:

> > Don't send individual patches in reply to the middle of threads, it
> > makes it really confusing what's going on.  I now have multiple patches

> With multiple being exactly two. I thought it to be easier this way
> around and the ordering to be obvious (if you use threading),
> but of course I can resend the two patches as a new series.

The threading wasn't even visible in my inbox since I delete mails after
I'm done with them, the only reason I knew you were replying in the
middle of a series was that I still had David's mail to reply to.  Even
if the threading is visible it gets very confusing if you've got a
series consisting of different versions of patches at different levels
of the thread, it's not always going to be direct replacements of
individual patches.

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Mark Brown]

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On Mon, Jul 25, 2016 at 09:31:15AM -0700, David Daney wrote:
> On 07/25/2016 09:16 AM, Mark Brown wrote:

> > The usual pattern would be something like (ARCH_THUNDER || COMPILE_TEST)
> > && PCI && 64BIT (so that people on other platforms where the device will
> > never actually appear don't get bothered by the prompt).

> ARCH_THUNDER needs to die, so perhaps it should be (ARM64 || COMPILE_TEST)
> && PCI && 64BIT if you really want to hide it from non-arm64 kernel configs.

It does?  Why?  One of the functions of the vendor specific Kconfig
options is to improve UX when configuring the kernel, if you're building
for a particular SoC or set of SoCs then we can avoid showing you
drivers that can never possibly appear in your system which makes life
a bit easier.  We shouldn't be using them in the code itself but they do
help people in Kconfig.

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[David Daney]

On 07/27/2016 11:12 AM, Mark Brown wrote:
> On Mon, Jul 25, 2016 at 09:31:15AM -0700, David Daney wrote:
>> On 07/25/2016 09:16 AM, Mark Brown wrote:
>
>>> The usual pattern would be something like (ARCH_THUNDER || COMPILE_TEST)
>>> && PCI && 64BIT (so that people on other platforms where the device will
>>> never actually appear don't get bothered by the prompt).
>
>> ARCH_THUNDER needs to die, so perhaps it should be (ARM64 || COMPILE_TEST)
>> && PCI && 64BIT if you really want to hide it from non-arm64 kernel configs.
>
> It does?  Why?

It adds clutter.  If we build a generic kernel, we first must select all 
the ARCH_*, then go back and select the devices we want.  Not much of a 
value add.

Better to just directly select the devices and remove this middle ARCH_* 
layer.

Also who is responsible for making sure the proper ARCH_* constraints 
are maintained?  If we remove ARCH_THUNDER, no need to worry about this.


>  One of the functions of the vendor specific Kconfig
> options is to improve UX when configuring the kernel, if you're building
> for a particular SoC or set of SoCs then we can avoid showing you
> drivers that can never possibly appear in your system which makes life
> a bit easier.  We shouldn't be using them in the code itself but they do
> help people in Kconfig.
>

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Mark Brown]

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On Wed, Jul 27, 2016 at 11:25:10AM -0700, David Daney wrote:
> On 07/27/2016 11:12 AM, Mark Brown wrote:
> > On Mon, Jul 25, 2016 at 09:31:15AM -0700, David Daney wrote:

> > > ARCH_THUNDER needs to die, so perhaps it should be (ARM64 || COMPILE_TEST)
> > > && PCI && 64BIT if you really want to hide it from non-arm64 kernel configs.

> > It does?  Why?

> It adds clutter.  If we build a generic kernel, we first must select all the
> ARCH_*, then go back and select the devices we want.  Not much of a value
> add.

The value comes when moving to a new kernel version and updating your
config or doing a new board - if you're building for a specific system
then you get fewer new driver prompts (especially if you've got a
smaller number of hotpluggable buses enabled).  This is the much more
common case for people doing kernel configuration, it did bother people
a lot in the past.

> Better to just directly select the devices and remove this middle ARCH_*
> layer.

It's one option every time a new vendor appears rather than every time a
new driver appears - it's a useful quality of life improvement for
people who are doing system customization that is fairly painless for
those doing generic kernels (who can just enable everything).

> Also who is responsible for making sure the proper ARCH_* constraints are
> maintained?  If we remove ARCH_THUNDER, no need to worry about this.

People using the devices or writing drivers...  this really isn't
particularly challenging and it's not like it's hard to fix if people
notice issues.

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Re: [PATCH 6/6] spi: octeon: Add thunderx driver

[Mark Brown]

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On Mon, Jul 25, 2016 at 05:51:22PM +0200, Jan Glauber wrote:
> On Sun, Jul 24, 2016 at 10:04:52PM +0100, Mark Brown wrote:
> > On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:

> > > +#define PCI_DEVICE_ID_THUNDERX_SPI      0xa00b

> > > +static const struct pci_device_id thunderx_spi_pci_id_table[] = {
> > > +	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDERX_SPI) },
> > > +	{ 0, }
> > > +};

> > The define for the device ID doesn't seem to be adding much here.

> I find it more readable instead of PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b),
> or did I miss your point?

No, that's my point - I find myself wondering why there's a define half
way down the file and what else is looking at the define other than the
location a few lines below.

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