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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA3OCBTYWx0ZWRfXyh9RawbtSqUJ doOqg4rTkVdMArLg7Z9eHktWRG3vUwcGt0Ci8+nCEynf5MiW2PtoFdQVUXWKDHAflrjFYBVHH9n Apd+PmDT32DkTw4i3fXZdgPhdrF2N+w= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA3OCBTYWx0ZWRfX0l1JrdnMu62v 3BWySCk3bxDI4wRZGUPcsTYjOANhJKZHNnZSZTZUqKa1NlZMFZYWnKQraTMjBGIjfPVcoMNfeLf l45zn1SfeQAiLCgQV95VVkU5wPMRUbpPWr1ueWDCH8CkRIHIbXkMyRrjKLMgUMo15thb445ix64 mv8UX+HPfG2rFRcZY9zxppymS1W2P6e73JwSNMx7sgCL+G268rIQxUkvWCOFYygn/hfBXtdaxXQ Mh0/Y85v+aR4WCHBDZjafTYmMSXStTsXFvY32WTSzzTZK2oIHRc6Zio08Uqoa/6YFLpi3kW+oyc 77dsQe/JdDIgoxE8WTBVTk/meSfX7tF3eHPT0bIqR/2DFUnmAPIXnB/FVEcgNYOybzEwLPo0PEe Wm6MOXg7FKS3rLWQnQgPF30x1924aStH6XWV+OccE/VPnADLHOXx8j85hl/R/i78zWZzN4tkNQ7 Pfpvxya9QKofaWYl9VA== X-Proofpoint-GUID: mzPpCo5swdrgrLhDiMhFmn6wGvzD55mB X-Proofpoint-ORIG-GUID: mzPpCo5swdrgrLhDiMhFmn6wGvzD55mB X-Authority-Analysis: v=2.4 cv=IqCL47/g c=1 sm=1 tr=0 ts=6ac7f2e4 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=soJen2uxB0ky/kNk6TDY8g==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=ld924GHQG9e8gPgwT3gA:9 a=QEXdDO2ut3YA:10 a=ZXulRonScM0A:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_06,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1011 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080078 On 8/27/2026 11:29 PM, Praveen Talari wrote: > On the SA8255P platform there is no Linux clock handler for the SE > source clock, so the driver has no way to look up the source clock > index and divider needed to fill the GSI CONFIG0 TRE for a requested > transfer frequency. To work around this, firmware instead exposes the > SE HW supported source clock frequencies as OPPs on the perf domain > device. > > geni_se_domain_attach() now populates clk_perf_tbl from > the performance-domain OPP table, allowing firmware-managed > platforms to use geni_se_clk_freq_match(). > > Use geni_se_set_rate() instead of dev_pm_opp_set_rate() > so clock programming is handled centrally by the GENI core, > independent of the underlying clock-control mechanism. > > Acked-by: Mark Brown > Signed-off-by: Praveen Talari > --- Reviewed-by: Mukesh Kumar Savaliya