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[93.89.165.28]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d047c30sm1101122166b.6.2025.05.22.10.49.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 May 2025 10:49:24 -0700 (PDT) Message-ID: Date: Thu, 22 May 2025 19:49:24 +0200 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH next 2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength Content-Language: hu To: Miquel Raynal , Md Sadre Alam Cc: Mark Brown , Manivannan Sadhasivam , Richard Weinberger , Vignesh Raghavendra , Varadarajan Narayanan , Sricharan Ramabadhran , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com> <20250502-qpic-snand-8bit-ecc-v1-2-95f3cd08bbc5@gmail.com> <8aa3d4da-da3e-2af4-e0f9-cd56d6259d8f@quicinc.com> <878qn2nsa0.fsf@bootlin.com> <16195524-1f31-4968-a3fd-f3d24f1c4223@gmail.com> <87msbhezjf.fsf@bootlin.com> <007881c9-e03c-1473-d8eb-53fbad8c6a8e@quicinc.com> <87frh4ej87.fsf@bootlin.com> <87h61e8kow.fsf@bootlin.com> From: Gabor Juhos In-Reply-To: <87h61e8kow.fsf@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 2025. 05. 21. 9:52 keltezéssel, Miquel Raynal írta: > On 21/05/2025 at 11:08:02 +0530, Md Sadre Alam wrote: > >> Hi, >> >> On 5/16/2025 7:44 PM, Miquel Raynal wrote: >>> >>>>>> Interestingly enough, it reports the correct number of bit errors now. >>>>>> For me it seems, that the hardware reports the number of the corrected >>>>>> *bytes* instead of the corrected *bits*. >>>>> I doubt that, nobody counts bytes of errors. >>>>> You results are surprising. I initially though in favour of a software >>>>> bug, but then it looks even weirder than that. Alam? >>>> I have checked with HW team , the QPIC ECC HW engine reports the bit >>>> error byte wise not bit wise. >>>> >>>> e.g >>>> Byte0 --> 2-bitflips --> QPIC ECC counts 1 only >>>> Byte1 --> 3-bitflips --> QPIC ECC counts 1 only >>>> Byte2 --> 1-bitflips --> QPIC ECC counts 1 only >>>> Byte3 --> 4-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) >>>> Byte4 --> 6-bitflips --> QPIC ECC counts 1 only (in 8-bit ecc) >>>> >>>> Hope this can clearify the things now. >>> o_O ???? >>> How is that even useful? This basically means UBI will never refresh >>> the >>> data because we will constantly underestimate the number of bitflips! We >>> need to know the actual number, this averaging does not make any sense >>> for Linux. Is there another way to get the raw number of bitflips? >> I have re-checked with HW team, unfortunately currently there is no >> register fields available to get the raw number of bit flips. But >> for newer chipset they have fixed this issue. But currently the QPIC >> QPIC_NANDC_BUFFER_STATUS | 0x79B0018 register bit-8 will get set if >> there is uncorrectable bitflips happened. >> >> For 4-bit ECC if 5-bit raw bit flips happened then bit-8 will get set in >> QPIC_NANDC_BUFFER_STATUS. >> >> similar for 8-bit ECC if 9-bit raw bit flips happened then bit-8 will >> get set in QPIC_NANDC_BUFFER_STATUS. > > I believe the unrecoverable situation is handled correctly. What is not > is the fact that we care about the number of bitflips before having a > failure because if it reaches a certain threshold (typically 2/3 of the > strength) the upper layer is responsible of moving the data around to > avoid loosing it. > > You need to identify the hardware revision that fixed it and provide a > warning otherwise, or at least a comment in the code... In itself, neither a comment, nor a warning will help as far as the upper layer is concerned. However the driver can be changed to overestimate the number of corrected bitflips. I just sent a patch [1] which tries to addresses this. I admit that it is not ideal, but in my opinion it is a reasonable tradeoff which can be used as a temporary solution. For a long term fix, probably it would be possible to change the driver to do the ECC correction in software. Although I have no idea how that would impact the performance. [1] https://lore.kernel.org/r/20250522-qpic-snand-overestimate-bitflips-v1-1-35c65c05068e@gmail.com Regards, Gabor