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[2003:f6:ef1b:2000:944c:cbc7:1e1c:2c47]) by smtp.gmail.com with ESMTPSA id ps8-20020a170906bf4800b00a3ca744438csm1407182ejb.213.2024.02.13.08.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 08:05:00 -0800 (PST) Message-ID: Subject: Re: [PATCH 5/5] iio: adc: ad7380: use spi_optimize_message() From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner Cc: Mark Brown , Martin Sperl , David Jander , Jonathan Cameron , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Alain Volmat , Maxime Coquelin , Alexandre Torgue , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org Date: Tue, 13 Feb 2024 17:08:19 +0100 In-Reply-To: References: <20240212-mainline-spi-precook-message-v1-0-a2373cd72d36@baylibre.com> <20240212-mainline-spi-precook-message-v1-5-a2373cd72d36@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2024-02-13 at 09:27 -0600, David Lechner wrote: > On Tue, Feb 13, 2024 at 3:47=E2=80=AFAM Nuno S=C3=A1 wrote: > >=20 > > On Mon, 2024-02-12 at 17:26 -0600, David Lechner wrote: > > > This modifies the ad7380 ADC driver to use spi_optimize_message() to > > > optimize the SPI message for the buffered read operation. Since buffe= red > > > reads reuse the same SPI message for each read, this can improve > > > performance by reducing the overhead of setting up some parts the SPI > > > message in each spi_sync() call. > > >=20 > > > Signed-off-by: David Lechner > > > --- > > > =C2=A0drivers/iio/adc/ad7380.c | 52 +++++++++++++++++++++++++++++++++= ++++++++-- > > > ---- > > > - > > > =C2=A01 file changed, 45 insertions(+), 7 deletions(-) > > >=20 > > > diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c > > > index abd746aef868..5c5d2642a474 100644 > > > --- a/drivers/iio/adc/ad7380.c > > > +++ b/drivers/iio/adc/ad7380.c > > > @@ -133,6 +133,7 @@ struct ad7380_state { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct spi_device *spi; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct regulator *vref; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct regmap *regmap; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 struct spi_message *msg; > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * DMA (thus cache coherency main= tenance) requires the > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * transfer buffers to live in th= eir own cache lines. > > > @@ -231,19 +232,55 @@ static int ad7380_debugfs_reg_access(struct iio= _dev > > > *indio_dev, u32 reg, > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; > > > =C2=A0} > > >=20 > > > +static int ad7380_buffer_preenable(struct iio_dev *indio_dev) > > > +{ > > > +=C2=A0=C2=A0=C2=A0=C2=A0 struct ad7380_state *st =3D iio_priv(indio_= dev); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 struct spi_transfer *xfer; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 int ret; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 st->msg =3D spi_message_alloc(1, GFP_KERNEL= ); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 if (!st->msg) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 return -ENOMEM; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 xfer =3D list_first_entry(&st->msg->transfe= rs, struct spi_transfer, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 transfer_list); > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 xfer->bits_per_word =3D st->chip_info->chan= nels[0].scan_type.realbits; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 xfer->len =3D 4; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 xfer->rx_buf =3D st->scan_data.raw; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D spi_optimize_message(st->spi, st->m= sg); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 if (ret) { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 spi_message_free(st->msg); > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 return ret; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 } > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 return 0; > > > +} > > > + > > > +static int ad7380_buffer_postdisable(struct iio_dev *indio_dev) > > > +{ > > > +=C2=A0=C2=A0=C2=A0=C2=A0 struct ad7380_state *st =3D iio_priv(indio_= dev); > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 spi_unoptimize_message(st->msg); > > > +=C2=A0=C2=A0=C2=A0=C2=A0 spi_message_free(st->msg); > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0 return 0; > > > +} > > > + > >=20 > > Not such a big deal but unless I'm missing something we could have the > > spi_message (+ the transfer) statically allocated in struct ad7380_stat= e and > > do > > the optimize only once at probe (naturally with proper devm action for > > unoptimize). Then we would not need to this for every buffer enable + > > disable. I > > know in terms of performance it won't matter but it would be less code = I > > guess. > >=20 > > Am I missing something? >=20 > No, your understanding is correct for the current state of everything > in this series. So, we could do as you suggest, but I have a feeling > that future additions to this driver might require that it gets > changed back this way eventually. Hmm, not really sure about that as chip_info stuff is always our friend :).= And I'm anyways of the opinion of keeping things simpler and start to evolve wh= en really needed (because often we never really need to evolve). But bah, as I said... this is really not a big deal. - Nuno S=C3=A1