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From: Sricharan R <sricharan@codeaurora.org>
To: Andy Gross <andy.gross@linaro.org>
Cc: Varadarajan Narayanan <varada@codeaurora.org>,
	broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
	david.brown@linaro.org, linux-spi@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	Matthew McClintock <mmcclint@codeaurora.org>
Subject: Re: [PATCH 11/18] spi: qup: properly detect extra interrupts
Date: Thu, 15 Jun 2017 10:57:27 +0530	[thread overview]
Message-ID: <e3b6bcde-0749-1e8e-431f-a42e9207bbef@codeaurora.org> (raw)
In-Reply-To: <20170614195953.GD32733@hector.wework.com>

Hi Andy,

On 6/15/2017 1:29 AM, Andy Gross wrote:
> On Wed, Jun 14, 2017 at 12:57:25PM +0530, Sricharan R wrote:
>> Hi Varada,
>>
>> On 6/14/2017 11:22 AM, Varadarajan Narayanan wrote:
>>> It's possible for a SPI transaction to complete and get another
>>> interrupt and have it processed on the same spi_transfer before the
>>> transfer_one can set it to NULL.
>>>
>>> This masks unexpected interrupts, so let's set the spi_transfer to
>>> NULL in the interrupt once the transaction is done. So we can
>>> properly detect these bad interrupts and print warning messages.
>>>
>>> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
>>> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
>>> ---
>>>  drivers/spi/spi-qup.c | 20 +++++++++++---------
>>>  1 file changed, 11 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
>>> index bd53e82..1a2a9d9 100644
>>> --- a/drivers/spi/spi-qup.c
>>> +++ b/drivers/spi/spi-qup.c
>>> @@ -496,13 +496,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
>>>  	struct spi_qup *controller = dev_id;
>>>  	struct spi_transfer *xfer;
>>>  	u32 opflags, qup_err, spi_err;
>>> -	unsigned long flags;
>>>  	int error = 0;
>>> +	bool done = 0;
>>>  
>>> -	spin_lock_irqsave(&controller->lock, flags);
>>> +	spin_lock(&controller->lock);
>>>  	xfer = controller->xfer;
>>>  	controller->xfer = NULL;
>>> -	spin_unlock_irqrestore(&controller->lock, flags);
>>> +	spin_unlock(&controller->lock);
>>
>>  Why change the locking here ?
>>
>>>  
>>>  	qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
>>>  	spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
>>> @@ -556,16 +556,19 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
>>>  			spi_qup_write(controller, xfer);
>>>  	}
>>>  
>>> -	spin_lock_irqsave(&controller->lock, flags);
>>> -	controller->error = error;
>>> -	controller->xfer = xfer;
>>> -	spin_unlock_irqrestore(&controller->lock, flags);
>>> -
>>>  	/* re-read opflags as flags may have changed due to actions above */
>>>  	opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
>>>  
>>>  	if ((controller->rx_bytes == xfer->len &&
>>>  		(opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) ||  error)
>>> +		done = true;
>>> +
>>> +	spin_lock(&controller->lock);
>>> +	controller->error = error;
>>> +	controller->xfer = done ? NULL : xfer;
>>> +	spin_unlock(&controller->lock);
>>> +
>>> +	if (done)
>>>  		complete(&controller->done);
>>>  
>>   Its not clear, why the driver is setting the controller->xfer = NULL
>>   and restoring it inside the irq. This patch seems to fix things on
>>   top of that.
> 
> I think the original intent was to make sure that the irqhandler knew that there
> was no outstanding transaction.  This begs the question of why that would ever
> be necessary.  I think it would suffice to rework all of that to remove that
> behavior and perhaps enable/disable the irq as we need to during transactions.
> 
> I've never been a fan of the controller->xfer being set to NULL.

 Agree, that part needs fixing in the original code. Also patch #10 changing the
 behavior to acknowledge the interrupts only when its spurious does not look
 correct. Trying to fix the original should simplify or avoid the spurious case
 itself.

Regards,
 Sricharan 

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2017-06-15  5:27 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-14  5:52 [PATCH 00/18] spi: qup: Fixes and add support for >64k transfers Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 01/18] spi: qup: Enable chip select support Varadarajan Narayanan
2017-06-14  9:47   ` Stanimir Varbanov
2017-08-08 11:18   ` Applied "spi: qup: Enable chip select support" to the spi tree Mark Brown
2017-06-14  5:52 ` [PATCH 03/18] spi: qup: Add completion timeout for dma mode Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 04/18] spi: qup: Add completion timeout for fifo/block mode Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 05/18] spi: qup: Place the QUP in run mode before DMA transactions Varadarajan Narayanan
     [not found] ` <1497419551-21834-1-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14  5:52   ` [PATCH 02/18] spi: qup: Setup DMA mode correctly Varadarajan Narayanan
2017-08-08 11:18     ` Applied "spi: qup: Setup DMA mode correctly" to the spi tree Mark Brown
2017-06-14  5:52   ` [PATCH 06/18] spi: qup: Fix error handling in spi_qup_prep_sg Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 07/18] spi: qup: Fix transaction done signaling Varadarajan Narayanan
2017-06-14  7:13   ` Sricharan R
     [not found]     ` <4b81a4c7-b85c-a35d-15fb-4aaaec3c7e8c-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14 19:51       ` Andy Gross
     [not found]         ` <20170614195155.GB32733-5taXn+FmohyKb9UB7mSz9QC/G2K4zDHf@public.gmane.org>
2017-06-15  5:14           ` Sricharan R
2017-06-14  5:52 ` [PATCH 08/18] spi: qup: Handle v1 dma completion differently Varadarajan Narayanan
     [not found]   ` <1497419551-21834-9-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14  7:15     ` Sricharan R
     [not found]       ` <a0e499a7-8f89-96d6-9463-c2b3f774cd6d-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14 19:53         ` Andy Gross
2017-06-14  5:52 ` [PATCH 09/18] spi: qup: Do block sized read/write in block mode Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 10/18] spi: qup: Fix DMA mode interrupt handling Varadarajan Narayanan
2017-06-14  7:21   ` Sricharan R
     [not found]     ` <66ba7dfb-6ff3-884e-6db0-8d5191f87c93-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14 20:06       ` Andy Gross
2017-06-15  5:52         ` Sricharan R
2017-06-14  5:52 ` [PATCH 11/18] spi: qup: properly detect extra interrupts Varadarajan Narayanan
     [not found]   ` <1497419551-21834-12-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-14  7:27     ` Sricharan R
2017-06-14 19:59       ` Andy Gross
     [not found]         ` <20170614195953.GD32733-5taXn+FmohyKb9UB7mSz9QC/G2K4zDHf@public.gmane.org>
2017-06-14 21:51           ` Matthew McClintock
2017-06-15  5:27         ` Sricharan R [this message]
2017-06-14  5:52 ` [PATCH 12/18] spi: qup: refactor spi_qup_io_config into two functions Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 13/18] spi: qup: call io_config in mode specific function Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 14/18] spi: qup: allow block mode to generate multiple transactions Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 15/18] spi: qup: refactor spi_qup_prep_sg Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 16/18] spi: qup: allow multiple DMA transactions per spi xfer Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 17/18] spi: qup: Ensure done detection Varadarajan Narayanan
2017-06-14  5:52 ` [PATCH 18/18] spi: qup: support for qup v1 dma Varadarajan Narayanan

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