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Wed, 29 Jan 2025 18:48:00 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C08524002D; Wed, 29 Jan 2025 18:46:38 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BCFC43CD6F7; Wed, 29 Jan 2025 18:40:25 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 29 Jan 2025 18:40:24 +0100 Message-ID: Date: Wed, 29 Jan 2025 18:40:23 +0100 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/9] dt-bindings: spi: Add STM32 OSPI controller To: Conor Dooley CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon , , , , , , References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> <20250128081731.2284457-2-patrice.chotard@foss.st.com> <20250128-panama-manly-a753d91c297c@spud> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <20250128-panama-manly-a753d91c297c@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-29_03,2025-01-29_01,2024-11-22_01 On 1/28/25 19:02, Conor Dooley wrote: > On Tue, Jan 28, 2025 at 09:17:23AM +0100, patrice.chotard@foss.st.com wrote: >> From: Patrice Chotard >> >> Add device tree bindings for the STM32 OSPI controller. >> >> Main features of the Octo-SPI controller : >> - support sNOR / sNAND / HyperRAM™ and HyperFlash™ devices. >> - Three functional modes: indirect, automatic-status polling, >> memory-mapped. >> - Up to 4 Gbytes of external memory can be addressed in indirect >> mode (per physical port and per CS), and up to 256 Mbytes in >> memory-mapped mode (combined for both physical ports and per CS). >> - Single-, dual-, quad-, and octal-SPI communication. >> - Dual-quad communication. >> - Single data rate (SDR) and double transfer rate (DTR). >> - Maximum target frequency is 133 MHz for SDR and 133 MHz for DTR. >> - Data strobe support. >> - DMA channel for indirect mode. >> - Double CS mapping that allows two external flash devices to be >> addressed with a single OCTOSPI controller mapped on a single >> OCTOSPI port. >> >> Signed-off-by: Patrice Chotard >> --- >> .../bindings/spi/st,stm32mp25-ospi.yaml | 102 ++++++++++++++++++ >> 1 file changed, 102 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml >> new file mode 100644 >> index 000000000000..f1d539444673 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml >> @@ -0,0 +1,102 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI) >> + >> +maintainers: >> + - Patrice Chotard >> + >> +allOf: >> + - $ref: spi-controller.yaml# >> + >> +properties: >> + compatible: >> + const: st,stm32mp25-ospi >> + >> + reg: >> + maxItems: 1 >> + >> + memory-region: >> + maxItems: 1 > > Whatever about not having descriptions for clocks or reg when there's > only one, I think a memory region should be explained. ok i will add : description: | Memory region to be used for memory-map read access. > >> + >> + clocks: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + resets: >> + items: >> + - description: phandle to OSPI block reset >> + - description: phandle to delay block reset >> + >> + dmas: >> + maxItems: 2 >> + >> + dma-names: >> + items: >> + - const: tx >> + - const: rx >> + >> + st,syscfg-dlyb: >> + description: phandle to syscon block >> + Use to set the OSPI delay block within syscon to >> + tune the phase of the RX sampling clock (or DQS) in order >> + to sample the data in their valid window and to >> + tune the phase of the TX launch clock in order to meet setup >> + and hold constraints of TX signals versus the memory clock. >> + $ref: /schemas/types.yaml#/definitions/phandle-array > > Why do you need a phandle here? I assume looking up by compatible ain't > possible because you have multiple controllers on the SoC? Also, I don't Yes, we got 2 OCTOSPI controller, each of them have a dedicated delay block syscfg register. > think your copy-paste "phandle to" stuff here is accurate: > st,syscfg-dlyb = <&syscfg 0x1000>; > There's an offset here that you don't mention in your description. I will add it as following: st,syscfg-dlyb: description: Use to set the OSPI delay block within syscon to tune the phase of the RX sampling clock (or DQS) in order to sample the data in their valid window and to tune the phase of the TX launch clock in order to meet setup and hold constraints of TX signals versus the memory clock. $ref: /schemas/types.yaml#/definitions/phandle-array items: - description: phandle to syscfg - description: register offset within syscfg > >> + items: >> + maxItems: 1 >> + >> + access-controllers: >> + description: phandle to the rifsc device to check access right >> + and in some cases, an additional phandle to the rcc device for >> + secure clock control > > This should be described using items rather than a free-form list. access-controllers: description: phandle to the rifsc device to check access right and in some cases, an additional phandle to the rcc device for secure clock control items: - description: phandle to bus controller or to clock controller - description: access controller specifier minItems: 1 maxItems: 2 > >> + minItems: 1 >> + maxItems: 2 >> + >> + power-domains: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - interrupts >> + - st,syscfg-dlyb >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + spi@40430000 { > > nit: you missing a blank line here. > >> + compatible = "st,stm32mp25-ospi"; >> + reg = <0x40430000 0x400>; >> + memory-region = <&mm_ospi1>; >> + interrupts = ; >> + dmas = <&hpdma 2 0x62 0x00003121 0x0>, >> + <&hpdma 2 0x42 0x00003112 0x0>; >> + dma-names = "tx", "rx"; >> + clocks = <&scmi_clk CK_SCMI_OSPI1>; >> + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; >> + access-controllers = <&rifsc 74>; >> + power-domains = <&CLUSTER_PD>; >> + st,syscfg-dlyb = <&syscfg 0x1000>; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + flash@0 { >> + compatible = "jedec,spi-nor"; >> + reg = <0>; >> + spi-rx-bus-width = <4>; >> + spi-max-frequency = <108000000>; >> + }; >> + }; >> -- >> 2.25.1 >>