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Fri, 3 Jul 2026 16:29:09 +0000 Message-ID: Date: Fri, 3 Jul 2026 19:29:01 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCHv2 3/4] mmc: sdhci-esdhc-mcf: do not use readl()/writel() on ColdFire To: Greg Ungerer , CC: , , , , , , , , , , , , , References: <20260609142139.1563360-1-gerg@linux-m68k.org> <20260609142139.1563360-5-gerg@linux-m68k.org> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20260609142139.1563360-5-gerg@linux-m68k.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DUZPR01CA0241.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b5::24) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|SA1PR11MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: 114684c2-0597-438d-3f4d-08ded9203514 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|376014|7416014|56012099006|11063799006|4143699003|6133799003|22082099003|18002099003|18092099006; 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They check the supplied > IO address and will return either big or little endian results based on > that check. This is non-standard, they are expected to always return > little-endian byte ordered data. Unfortunately this behavior also means > that ioreadX()/iowroteX() and their big-endian counter parts > ioreadXbe()/iowriteXbe() are wrong. This is now in the process of being > cleaned up and fixed. > > Change the use of the readX() and writeX() access functions in this driver > to use the recently defined specific ColdFire internal SoC hardware IO > access functions mcf_read8()/mcf_read16()/mcf_read32() and > mcf_write8()/mcf_write16()/mcf_write32(). > > There is no functional change to the driver. Though it does have the > effect of making the IO access slightly more efficient, since there is > no longer a need to do the address check at every register access. > > Acked-by: Angelo Dureghello > Tested-by: Angelo Dureghello > Signed-off-by: Greg Ungerer Acked-by: Adrian Hunter > --- > v2: moved from RFC to PATCH > > drivers/mmc/host/sdhci-esdhc-mcf.c | 24 ++++++++++++------------ > 1 file changed, 12 insertions(+), 12 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-esdhc-mcf.c b/drivers/mmc/host/sdhci-esdhc-mcf.c > index 375fce5639d7..6853521e8b2c 100644 > --- a/drivers/mmc/host/sdhci-esdhc-mcf.c > +++ b/drivers/mmc/host/sdhci-esdhc-mcf.c > @@ -55,7 +55,7 @@ static inline void esdhc_clrset_be(struct sdhci_host *host, > if (reg == SDHCI_HOST_CONTROL) > val |= ESDHC_PROCTL_D3CD; > > - writel((readl(base) & ~mask) | val, base); > + mcf_write32((mcf_read32(base) & ~mask) | val, base); > } > > /* > @@ -71,7 +71,7 @@ static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg) > if (reg == SDHCI_HOST_CONTROL) { > u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL; > u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3; > - u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1); > + u8 tmp = mcf_read8(host->ioaddr + SDHCI_HOST_CONTROL + 1); > > tmp &= ~0x03; > tmp |= dma_bits; > @@ -82,12 +82,12 @@ static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg) > */ > host_ctrl |= val; > host_ctrl |= (dma_bits << 8); > - writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); > + mcf_write32(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); > > return; > } > > - writel((readl(base) & mask) | (val << shift), base); > + mcf_write32((mcf_read32(base) & mask) | (val << shift), base); > } > > static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg) > @@ -110,24 +110,24 @@ static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg) > * As for the fsl driver, > * we have to set the mode in a single write here. > */ > - writel(val << 16 | mcf_data->aside, > + mcf_write32(val << 16 | mcf_data->aside, > host->ioaddr + SDHCI_TRANSFER_MODE); > return; > } > > - writel((readl(base) & mask) | (val << shift), base); > + mcf_write32((mcf_read32(base) & mask) | (val << shift), base); > } > > static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg) > { > - writel(val, host->ioaddr + reg); > + mcf_write32(val, host->ioaddr + reg); > } > > static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg) > { > if (reg == SDHCI_HOST_CONTROL) { > u8 __iomem *base = host->ioaddr + (reg & ~3); > - u16 val = readw(base + 2); > + u16 val = mcf_read16(base + 2); > u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK; > u8 host_ctrl = val & 0xff; > > @@ -137,7 +137,7 @@ static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg) > return host_ctrl; > } > > - return readb(host->ioaddr + (reg ^ 0x3)); > + return mcf_read8(host->ioaddr + (reg ^ 0x3)); > } > > static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg) > @@ -149,14 +149,14 @@ static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg) > if (reg == SDHCI_HOST_VERSION) > reg -= 2; > > - return readw(host->ioaddr + (reg ^ 0x2)); > + return mcf_read16(host->ioaddr + (reg ^ 0x2)); > } > > static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg) > { > u32 val; > > - val = readl(host->ioaddr + reg); > + val = mcf_read32(host->ioaddr + reg); > > /* > * RM (25.3.9) sd pin clock must never exceed 25Mhz. > @@ -245,7 +245,7 @@ static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host, > * fvco = fsys * outdvi1 + 1 > * fshdc = fvco / outdiv3 + 1 > */ > - temp = readl(pll_dr); > + temp = mcf_read32(pll_dr); > fsys = pltfm_host->clock; > fvco = fsys * ((temp & 0x1f) + 1); > fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);