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Wed, 2 Sep 2026 04:45:25 -0500 Message-ID: Date: Wed, 2 Sep 2026 15:15:24 +0530 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support To: Mark Brown CC: , , , , , , , , , , , , , , , , , References: <20260825171737.776052-1-s-k6@ti.com> <20260825171737.776052-9-s-k6@ti.com> <8aac0c42-fad5-4146-a2a3-b60bdab71a20@sirena.org.uk> Content-Language: en-US From: Santhosh Kumar K In-Reply-To: <8aac0c42-fad5-4146-a2a3-b60bdab71a20@sirena.org.uk> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BBC:EE_|DS0PR10MB7089:EE_ X-MS-Office365-Filtering-Correlation-Id: 5052d7ab-ce72-4bdc-77e5-08df08d70890 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|23010399003|82310400026|1800799024|5023799004|4143699003|10067099003|6133799003|22082099003|18002099003|56012099006|13003099007; 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Without calibration the PHY is unused and read capture relies >> on a fixed delay, limiting throughput at frequencies above the base >> operating speed. > >> Add an execute_tuning callback that performs delay-line calibration using >> a known data pattern written to a dedicated flash region. The pattern is >> either read from a NOR partition identified by the DT property >> spi-phy-pattern-partition, or written to the NAND page cache before >> each calibration read. > >> struct cqspi_flash_pdata { > >> + bool use_dqs; >> + bool use_tuned_phy; > > The AM65x has a fun erratum i2189 which mentions that it requires > disabling DQS for writes: > > https://www.ti.com.cn/lit/er/sprz452i/sprz452i.pdf > > which suggests we might need separate controls for read and write > operation. Thanks for pointing this out. The DQS bit in CQSPI_REG_READCAPTURE is used for read data capture and it's not consulted during writes. However, the actual i2189 issue was that cqspi_tune_phy() unconditionally set both PHY_EN and PHY_PIPELINE on both read and write path - non-compliant with the erratum. So, I'll split the tune_phy() into two separate paths for read and write. Will respin the series with this fix and some sashiko-bot fixes. > >> +static int cqspi_write_pattern_to_cache(struct cqspi_flash_pdata *f_pdata, >> + struct spi_mem *mem, >> + const struct spi_mem_op *write_op) >> +{ >> + struct spi_controller *ctlr = mem->spi->controller; >> + struct device *dev = &f_pdata->cqspi->pdev->dev; >> + struct spi_mem_op op = *write_op; >> + int ret; >> + >> + op.max_freq = mem->spi->max_speed_hz; >> + op.data.nbytes = sizeof(phy_tuning_pattern); >> + op.data.buf.out = phy_tuning_pattern; >> + >> + ret = ctlr->mem_ops->exec_op(mem, &op); >> + if (ret) { >> + dev_err(dev, "Failed to write PHY pattern to cache: %d\n", ret); >> + return ret; >> + } >> + dev_dbg(dev, "PHY pattern (%zu bytes) written to cache\n", >> + sizeof(phy_tuning_pattern)); >> + >> + return 0; >> +} > > spinand_write_page() has a multi-operation sequence, I've not checked if > any fancy flashes with DQS support actually need that. _read_page() > looks more straightforward. cqspi_write_pattern_to_cache() does a PROGRAM_LOAD only (no PROGRAM_EXECUTE), and tuning reads the pattern back from cache - no cell wear. True for all SPI NANDs we've tested; a DQS capable device needing EXECUTE before readback would need separate handling, but haven't seen one. Thanks, Santhosh.