[PATCH 0/9] Add QPIC SPI NAND support for IPQ5424 and IPQ5332 platforms

[PATCH 0/9] Add QPIC SPI NAND support for IPQ5424 and IPQ5332 platforms

[Md Sadre Alam]

This patch series adds comprehensive QPIC SPI NAND flash controller support
for Qualcomm IPQ5424 and IPQ5332 SoCs.

The Qualcomm IPQ5424 and IPQ5332 are ARM64-based networking SoCs that include
QPIC (Qualcomm Parallel Interface Controller) with SPI NAND flash support.
These platforms are commonly used in wireless routers, access points.

This series enables SPI NAND functionality by:
1. Adding device tree binding support for both platforms
2. Fixing a critical BAM DMA mask field issue affecting IPQ5424
3. Enabling SoC-level device tree support
4. Configuring reference board implementations
5. Resolving GPIO conflicts with eMMC interfaces

I have tested these patches on IPQ9574, IPQ5424 and IPQ5332 SoCs.


Md Sadre Alam (9):
  spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatible
  spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatible
  dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+
  arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support
  arm64: dts: qcom: ipq5332: Add QPIC SPI NAND controller support
  arm64: dts: qcom: ipq5424: Enable QPIC SPI NAND support
  arm64: dts: qcom: ipq5332: Enable QPIC SPI NAND support
  arm64: dts: qcom: ipq5424: Remove eMMC support
  arm64: dts: qcom: ipq5332: Remove eMMC support

 .../bindings/spi/qcom,spi-qpic-snand.yaml     |  2 +
 .../boot/dts/qcom/ipq5332-rdp-common.dtsi     | 44 +++++++++++++++++++
 arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts   | 34 --------------
 arch/arm64/boot/dts/qcom/ipq5332.dtsi         | 27 ++++++++++++
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts   | 43 +++++++++++-------
 arch/arm64/boot/dts/qcom/ipq5424.dtsi         | 27 ++++++++++++
 include/linux/dma/qcom_bam_dma.h              | 21 ++++++---
 7 files changed, 144 insertions(+), 54 deletions(-)

-- 
2.34.1

[PATCH 1/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatible

[Md Sadre Alam]

IPQ5424 contains the QPIC-SPI-NAND flash controller which is the same as
the one found in IPQ9574. So let's document the IPQ5424 compatible and
use IPQ9574 as the fallback.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
index cb1f15224b45..39e086ced891 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
@@ -25,6 +25,7 @@ properties:
       - items:
           - enum:
               - qcom,ipq5018-snand
+              - qcom,ipq5424-snand
           - const: qcom,ipq9574-snand
       - const: qcom,ipq9574-snand
 
-- 
2.34.1

Re: [PATCH 1/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatible

[Rob Herring (Arm)]

On Thu, 18 Sep 2025 15:10:09 +0530, Md Sadre Alam wrote:
> IPQ5424 contains the QPIC-SPI-NAND flash controller which is the same as
> the one found in IPQ9574. So let's document the IPQ5424 compatible and
> use IPQ9574 as the fallback.
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---
>  Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 2/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatible

[Md Sadre Alam]

IPQ5332 contains the QPIC-SPI-NAND flash controller which is the same as
the one found in IPQ9574. So let's document the IPQ5332 compatible and
use IPQ9574 as the fallback.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
index 39e086ced891..7d0571feb46d 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
@@ -25,6 +25,7 @@ properties:
       - items:
           - enum:
               - qcom,ipq5018-snand
+              - qcom,ipq5332-snand
               - qcom,ipq5424-snand
           - const: qcom,ipq9574-snand
       - const: qcom,ipq9574-snand
-- 
2.34.1

Re: [PATCH 2/9] spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatible

[Rob Herring (Arm)]

On Thu, 18 Sep 2025 15:10:10 +0530, Md Sadre Alam wrote:
> IPQ5332 contains the QPIC-SPI-NAND flash controller which is the same as
> the one found in IPQ9574. So let's document the IPQ5332 compatible and
> use IPQ9574 as the fallback.
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---
>  Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+

[Md Sadre Alam]

BAM version 1.6.0 and later changed the behavior of the mask field in
command elements for read operations. In newer BAM versions, the mask
field for read commands contains the upper 4 bits of the destination
address to support 36-bit addressing, while for write commands it
continues to function as a traditional write mask.

This change causes NAND enumeration failures on platforms like IPQ5424
that use BAM v1.6.0+, because the current code sets mask=0xffffffff
for all commands. For read commands on newer BAM versions, this results
in the hardware interpreting the destination address as 0xf_xxxxxxxx
(invalid high memory) instead of the intended 0x0_xxxxxxxx address.

Fixed this issue by:
1. Updating the bam_cmd_element structure documentation to reflect the
   dual purpose of the mask field
2. Modifying bam_prep_ce_le32() to set appropriate mask values based on
   command type:
   - For read commands: mask = 0 (32-bit addressing, upper bits = 0)
   - For write commands: mask = 0xffffffff (traditional write mask)
3. Maintaining backward compatibility with older BAM versions

This fix enables proper NAND functionality on IPQ5424 and other platforms
using BAM v1.6.0+ while preserving compatibility with existing systems.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 include/linux/dma/qcom_bam_dma.h | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h
index 68fc0e643b1b..d9d07a9ab313 100644
--- a/include/linux/dma/qcom_bam_dma.h
+++ b/include/linux/dma/qcom_bam_dma.h
@@ -13,9 +13,12 @@
  * supported by BAM DMA Engine.
  *
  * @cmd_and_addr - upper 8 bits command and lower 24 bits register address.
- * @data - for write command: content to be written into peripheral register.
- *	   for read command: dest addr to write peripheral register value.
- * @mask - register mask.
+ * @data - For write command: content to be written into peripheral register.
+ *	   For read command: lower 32 bits of destination address.
+ * @mask - For write command: register write mask.
+ *	   For read command on BAM v1.6.0+: upper 4 bits of destination address.
+ *	   For read command on BAM < v1.6.0: ignored by hardware.
+ *	   Setting to 0 ensures 32-bit addressing compatibility.
  * @reserved - for future usage.
  *
  */
@@ -42,6 +45,10 @@ enum bam_command_type {
  * @addr: target address
  * @cmd: BAM command
  * @data: actual data for write and dest addr for read in le32
+ *
+ * For BAM v1.6.0+, the mask field behavior depends on command type:
+ * - Write commands: mask = write mask (typically 0xffffffff)
+ * - Read commands: mask = upper 4 bits of destination address (0 for 32-bit)
  */
 static inline void
 bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr,
@@ -50,7 +57,11 @@ bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr,
 	bam_ce->cmd_and_addr =
 		cpu_to_le32((addr & 0xffffff) | ((cmd & 0xff) << 24));
 	bam_ce->data = data;
-	bam_ce->mask = cpu_to_le32(0xffffffff);
+	if (cmd == BAM_READ_COMMAND)
+		bam_ce->mask = cpu_to_le32(0x0); /* 32-bit addressing */
+	else
+		bam_ce->mask = cpu_to_le32(0xffffffff); /* Write mask */
+	bam_ce->reserved = 0;
 }
 
 /*
@@ -60,7 +71,7 @@ bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr,
  * @bam_ce: BAM command element
  * @addr: target address
  * @cmd: BAM command
- * @data: actual data for write and dest addr for read
+ * @data: actual data for write and destination address for read
  */
 static inline void
 bam_prep_ce(struct bam_cmd_element *bam_ce, u32 addr,
-- 
2.34.1

Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+

[Konrad Dybcio]

On 9/18/25 11:40 AM, Md Sadre Alam wrote:
> BAM version 1.6.0 and later changed the behavior of the mask field in
> command elements for read operations. In newer BAM versions, the mask
> field for read commands contains the upper 4 bits of the destination
> address to support 36-bit addressing, while for write commands it
> continues to function as a traditional write mask.

So the hardware can read from higher addresses but not write to them?

Plus, you didn't explain what the mask register does on BAM <1.6.0.
If it really masks the address, all reads will now point to 0x0

Konrad

Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+

[Md Sadre Alam]

On 9/18/2025 3:57 PM, Konrad Dybcio wrote:
> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>> BAM version 1.6.0 and later changed the behavior of the mask field in
>> command elements for read operations. In newer BAM versions, the mask
>> field for read commands contains the upper 4 bits of the destination
>> address to support 36-bit addressing, while for write commands it
>> continues to function as a traditional write mask.
> 
> So the hardware can read from higher addresses but not write to them?
No,
Write Operations: Can target any 32-bit address in the peripheral 
address space (up to 4GB)

Read Operations: Can read from any 32-bit peripheral address and
place the data into 36-bit memory addresses (up to 64GB) starting
from BAM v1.6.0
> 
> Plus, you didn't explain what the mask register does on BAM <1.6.0.
> If it really masks the address, all reads will now point to 0x0
The mask field never masks addresses in any BAM version. Here's the 
complete specification:

BAM Command Element Structure

Write Command Elements (All BAM Versions):

| Field  | Bits  | Description                                         |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 0 for write)                       |
|        | 23:0  | Address - target address in peripheral              |
|-----------------------------------------------------------------------
| 2nd DW | 31:0  | Data - the data to be written                       |
------------------------------------------------------------------------
| 3rd DW | 31:0  | Mask - 32-bit mask defining which bits to modify    |
-----------------------------------------------------------------------
| 4th DW | 31:0  | Reserved                                            |
------------------------------------------------------------------------

Read Command Elements (BAM < v1.6.0):

| Field  | Bits  | Description                                         |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 1 for read)                        |
|        | 23:0  | Address - source address in peripheral              |
------------------------------------------------------------------------
| 2nd DW | 31:0  | Destination - memory address to write read-data     |
------------------------------------------------------------------------
| 3rd DW | 31:0  | Reserved (IGNORED by hardware)                      |
------------------------------------------------------------------------
| 4th DW | 31:0  | Reserved                                            |
------------------------------------------------------------------------

Read Command Elements (BAM >= v1.6.0):

| Field  | Bits  | Description                                         |
|--------|-------|-----------------------------------------------------|
| 1st DW | 31:24 | Command (must be 1 for read)                        |
|        | 23:0  | Address - source address in peripheral              |
------------------------------------------------------------------------
| 2nd DW | 31:0  | Destination - 32 LSBs of 36-bit destination addr    |
------------------------------------------------------------------------
| 3rd DW | 31:4  | Reserved                                            |
|        | 3:0   | Destination Address 4 MSBs (bits 35:32)             |
------------------------------------------------------------------------
| 4th DW | 31:0  | Reserved                                            |
------------------------------------------------------------------------

For Read Commands:
- BAM < v1.6.0: 3rd Dword completely ignored by hardware
- BAM >= v1.6.0: 3rd Dword[3:0] contains upper 4 bits of destination
address

Thanks,
Alam.

RE: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+

[Lakshmi Sowjanya D (QUIC)]

> -----Original Message-----
> From: Md Sadre Alam <quic_mdalam@quicinc.com>
> Sent: Friday, September 19, 2025 11:27 AM
> To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>;
> broonie@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; andersson@kernel.org; konradybcio@kernel.org;
> vkoul@kernel.org; linux-arm-msm@vger.kernel.org; linux-spi@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> dmaengine@vger.kernel.org
> Cc: Varadarajan Narayanan (QUIC) <quic_varada@quicinc.com>
> Subject: Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask
> field for BAM v1.6.0+
> 
> 
> 
> On 9/18/2025 3:57 PM, Konrad Dybcio wrote:
> > On 9/18/25 11:40 AM, Md Sadre Alam wrote:
> >> BAM version 1.6.0 and later changed the behavior of the mask field in
> >> command elements for read operations. In newer BAM versions, the mask
> >> field for read commands contains the upper 4 bits of the destination
> >> address to support 36-bit addressing, while for write commands it
> >> continues to function as a traditional write mask.
> >
> > So the hardware can read from higher addresses but not write to them?
> No,
> Write Operations: Can target any 32-bit address in the peripheral address
> space (up to 4GB)
> 
> Read Operations: Can read from any 32-bit peripheral address and place the
> data into 36-bit memory addresses (up to 64GB) starting from BAM v1.6.0
> >
> > Plus, you didn't explain what the mask register does on BAM <1.6.0.
> > If it really masks the address, all reads will now point to 0x0
> The mask field never masks addresses in any BAM version. Here's the
> complete specification:
> 
> BAM Command Element Structure
> 
> Write Command Elements (All BAM Versions):
> 
> | Field  | Bits  | Description                                         |
> |--------|-------|-----------------------------------------------------|
> | 1st DW | 31:24 | Command (must be 0 for write)                       |
> |        | 23:0  | Address - target address in peripheral              |
> |-----------------------------------------------------------------------
> | 2nd DW | 31:0  | Data - the data to be written                       |
> ------------------------------------------------------------------------
> | 3rd DW | 31:0  | Mask - 32-bit mask defining which bits to modify    |
> -----------------------------------------------------------------------
> | 4th DW | 31:0  | Reserved                                            |
> ------------------------------------------------------------------------
> 
> Read Command Elements (BAM < v1.6.0):
> 
> | Field  | Bits  | Description                                         |
> |--------|-------|-----------------------------------------------------|
> | 1st DW | 31:24 | Command (must be 1 for read)                        |
> |        | 23:0  | Address - source address in peripheral              |
> ------------------------------------------------------------------------
> | 2nd DW | 31:0  | Destination - memory address to write read-data     |
> ------------------------------------------------------------------------
> | 3rd DW | 31:0  | Reserved (IGNORED by hardware)                      |
> ------------------------------------------------------------------------
> | 4th DW | 31:0  | Reserved                                            |
> ------------------------------------------------------------------------
> 
> Read Command Elements (BAM >= v1.6.0):
> 
> | Field  | Bits  | Description                                         |
> |--------|-------|-----------------------------------------------------|
> | 1st DW | 31:24 | Command (must be 1 for read)                        |
> |        | 23:0  | Address - source address in peripheral              |
> ------------------------------------------------------------------------
> | 2nd DW | 31:0  | Destination - 32 LSBs of 36-bit destination addr    |
> ------------------------------------------------------------------------
> | 3rd DW | 31:4  | Reserved                                            |
> |        | 3:0   | Destination Address 4 MSBs (bits 35:32)             |
> ------------------------------------------------------------------------
> | 4th DW | 31:0  | Reserved                                            |
> ------------------------------------------------------------------------
> 
> For Read Commands:
> - BAM < v1.6.0: 3rd Dword completely ignored by hardware
> - BAM >= v1.6.0: 3rd Dword[3:0] contains upper 4 bits of destination address
> 
> Thanks,
> Alam.

Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com>  # on SDX75

Thanks,
Lakshmi Sowjanya

Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field for BAM v1.6.0+

[Konrad Dybcio]

On 9/19/25 7:56 AM, Md Sadre Alam wrote:
> 
> 
> On 9/18/2025 3:57 PM, Konrad Dybcio wrote:
>> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>>> BAM version 1.6.0 and later changed the behavior of the mask field in
>>> command elements for read operations. In newer BAM versions, the mask
>>> field for read commands contains the upper 4 bits of the destination
>>> address to support 36-bit addressing, while for write commands it
>>> continues to function as a traditional write mask.
>>
>> So the hardware can read from higher addresses but not write to them?
> No,
> Write Operations: Can target any 32-bit address in the peripheral address space (up to 4GB)
> 
> Read Operations: Can read from any 32-bit peripheral address and
> place the data into 36-bit memory addresses (up to 64GB) starting
> from BAM v1.6.0

OK I misread your commit message

[...]

> For Read Commands:
> - BAM < v1.6.0: 3rd Dword completely ignored by hardware
> - BAM >= v1.6.0: 3rd Dword[3:0] contains upper 4 bits of destination
> address

This is important to point out. With that, the change looks sane indeed

Konrad

[PATCH 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support

[Md Sadre Alam]

Add device tree nodes for QPIC SPI NAND flash controller support
on IPQ5424 SoC.

The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash
devices with hardware ECC capabilities and DMA support through BAM
(Bus Access Manager).

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index ef2b52f3597d..81f133568bb6 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -567,6 +567,33 @@ sdhc: mmc@7804000 {
 			status = "disabled";
 		};
 
+		qpic_bam: dma-controller@7984000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x0 0x07984000 0x0 0x1c000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		qpic_nand: spi@79b0000 {
+			compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand";
+			reg = <0x0 0x079b0000 0x0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_QPIC_CLK>,
+				 <&gcc GCC_QPIC_AHB_CLK>,
+				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
+			clock-names = "core", "aon", "iom";
+			dmas = <&qpic_bam 0>,
+			       <&qpic_bam 1>,
+			       <&qpic_bam 2>;
+			dma-names = "tx", "rx", "cmd";
+			status = "disabled";
+		};
+
 		intc: interrupt-controller@f200000 {
 			compatible = "arm,gic-v3";
 			reg = <0 0xf200000 0 0x10000>, /* GICD */
-- 
2.34.1

[PATCH 5/9] arm64: dts: qcom: ipq5332: Add QPIC SPI NAND controller support

[Md Sadre Alam]

Add device tree nodes for QPIC SPI NAND flash controller support
on IPQ5332 SoC.

The IPQ5332 SoC includes a QPIC controller that supports SPI NAND flash
devices with hardware ECC capabilities and DMA support through BAM
(Bus Access Manager).

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 45fc512a3bab..af3fd55a85cf 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -423,6 +423,33 @@ blsp1_spi2: spi@78b7000 {
 			status = "disabled";
 		};
 
+		qpic_bam: dma-controller@7984000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x07984000 0x1c000>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		qpic_nand: spi@79b0000 {
+			compatible = "qcom,ipq5332-snand", "qcom,ipq9574-snand";
+			reg = <0x079b0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcc GCC_QPIC_CLK>,
+				 <&gcc GCC_QPIC_AHB_CLK>,
+				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
+			clock-names = "core", "aon", "iom";
+			dmas = <&qpic_bam 0>,
+			       <&qpic_bam 1>,
+			       <&qpic_bam 2>;
+			dma-names = "tx", "rx", "cmd";
+			status = "disabled";
+		};
+
 		usb: usb@8af8800 {
 			compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
 			reg = <0x08af8800 0x400>;
-- 
2.34.1

[PATCH 6/9] arm64: dts: qcom: ipq5424: Enable QPIC SPI NAND support

[Md Sadre Alam]

Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466
reference design platform.

The RDP466 board features a SPI NAND flash device connected to the QPIC
controller for primary storage. This patch enables the QPIC BAM DMA
controller and SPI NAND interface of QPIC, and configures the necessary
pin control settings for proper operation.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index 738618551203..accb15b0d742 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -224,6 +224,29 @@ data-pins {
 		};
 	};
 
+	qpic_snand_default_state: qpic-snand-default-state {
+		clock-pins {
+			pins = "gpio5";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		cs-pins {
+			pins = "gpio4";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio0", "gpio1", "gpio2", "gpio3";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
 	uart0_pins: uart0-default-state {
 		pins = "gpio10", "gpio11", "gpio12", "gpio13";
 		function = "uart0";
@@ -246,6 +269,26 @@ pcie3_default_state: pcie3-default-state {
 	};
 };
 
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qpic_snand_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		nand-ecc-engine = <&qpic_nand>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+	};
+};
+
 &uart0 {
 	pinctrl-0 = <&uart0_pins>;
 	pinctrl-names = "default";
-- 
2.34.1

Re: [PATCH 6/9] arm64: dts: qcom: ipq5424: Enable QPIC SPI NAND support

[Konrad Dybcio]

On 9/18/25 11:40 AM, Md Sadre Alam wrote:
> Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466
> reference design platform.
> 
> The RDP466 board features a SPI NAND flash device connected to the QPIC
> controller for primary storage. This patch enables the QPIC BAM DMA
> controller and SPI NAND interface of QPIC, and configures the necessary
> pin control settings for proper operation.
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---

[...]

> +&qpic_nand {
> +	pinctrl-0 = <&qpic_snand_default_state>;
> +	pinctrl-names = "default";
> +	status = "okay";

\n before 'status' is customary

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 6/9] arm64: dts: qcom: ipq5424: Enable QPIC SPI NAND support

[Md Sadre Alam]

On 9/18/2025 6:18 PM, Konrad Dybcio wrote:
> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>> Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466
>> reference design platform.
>>
>> The RDP466 board features a SPI NAND flash device connected to the QPIC
>> controller for primary storage. This patch enables the QPIC BAM DMA
>> controller and SPI NAND interface of QPIC, and configures the necessary
>> pin control settings for proper operation.
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> ---
> 
> [...]
> 
>> +&qpic_nand {
>> +	pinctrl-0 = <&qpic_snand_default_state>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
> 
> \n before 'status' is customary
Ok
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad

[PATCH 7/9] arm64: dts: qcom: ipq5332: Enable QPIC SPI NAND support

[Md Sadre Alam]

Enable QPIC SPI NAND flash controller support on the IPQ5332 reference
design platform.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 .../boot/dts/qcom/ipq5332-rdp-common.dtsi     | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
index b37ae7749083..8967861be5fd 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
@@ -78,4 +78,48 @@ gpio_leds_default: gpio-leds-default-state {
 		drive-strength = <8>;
 		bias-pull-down;
 	};
+
+	qpic_snand_default_state: qpic-snand-default-state {
+		clock-pins {
+			pins = "gpio13";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cs-pins {
+			pins = "gpio12";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data-pins {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "qspi_data";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	pinctrl-0 = <&qpic_snand_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		nand-ecc-engine = <&qpic_nand>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+	};
 };
-- 
2.34.1

Re: [PATCH 7/9] arm64: dts: qcom: ipq5332: Enable QPIC SPI NAND support

[Konrad Dybcio]

On 9/18/25 11:40 AM, Md Sadre Alam wrote:
> Enable QPIC SPI NAND flash controller support on the IPQ5332 reference
> design platform.
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 8/9] arm64: dts: qcom: ipq5424: Remove eMMC support

[Md Sadre Alam]

Remove eMMC support from the IPQ5424 RDP466 board configuration to
resolve GPIO pin conflicts with SPI NAND interface.

The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot
mode configuration. The eMMC controller and SPI NAND controller share
the same GPIO pins, creating a hardware conflict:

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 30 ---------------------
 1 file changed, 30 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
index accb15b0d742..347659d4f551 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
@@ -124,13 +124,6 @@ &qusb_phy_1 {
 	status = "okay";
 };
 
-&sdhc {
-	pinctrl-0 = <&sdc_default_state>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
 &sleep_clk {
 	clock-frequency = <32000>;
 };
@@ -201,29 +194,6 @@ mosi-pins {
 		};
 	};
 
-	sdc_default_state: sdc-default-state {
-		clk-pins {
-			pins = "gpio5";
-			function = "sdc_clk";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		cmd-pins {
-			pins = "gpio4";
-			function = "sdc_cmd";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-
-		data-pins {
-			pins = "gpio0", "gpio1", "gpio2", "gpio3";
-			function = "sdc_data";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
-
 	qpic_snand_default_state: qpic-snand-default-state {
 		clock-pins {
 			pins = "gpio5";
-- 
2.34.1

Re: [PATCH 8/9] arm64: dts: qcom: ipq5424: Remove eMMC support

[Konrad Dybcio]

On 9/18/25 11:40 AM, Md Sadre Alam wrote:
> Remove eMMC support from the IPQ5424 RDP466 board configuration to
> resolve GPIO pin conflicts with SPI NAND interface.
> 
> The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot
> mode configuration. The eMMC controller and SPI NAND controller share
> the same GPIO pins, creating a hardware conflict:
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---

The subject should contain the board name, i.e.:

arm64: dts: qcom: ipq5424-rdp466: xxx

same for patch 9

Konrad

Re: [PATCH 8/9] arm64: dts: qcom: ipq5424: Remove eMMC support

[Konrad Dybcio]

On 9/18/25 2:46 PM, Konrad Dybcio wrote:
> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>> Remove eMMC support from the IPQ5424 RDP466 board configuration to
>> resolve GPIO pin conflicts with SPI NAND interface.
>>
>> The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot
>> mode configuration. The eMMC controller and SPI NAND controller share
>> the same GPIO pins, creating a hardware conflict:
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> ---
> 
> The subject should contain the board name, i.e.:
> 
> arm64: dts: qcom: ipq5424-rdp466: xxx
> 
> same for patch 9

(and for patches 6-7)

Konrad

Re: [PATCH 8/9] arm64: dts: qcom: ipq5424: Remove eMMC support

[Md Sadre Alam]

On 9/18/2025 6:16 PM, Konrad Dybcio wrote:
> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>> Remove eMMC support from the IPQ5424 RDP466 board configuration to
>> resolve GPIO pin conflicts with SPI NAND interface.
>>
>> The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot
>> mode configuration. The eMMC controller and SPI NAND controller share
>> the same GPIO pins, creating a hardware conflict:
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> ---
> 
> The subject should contain the board name, i.e.:
> 
> arm64: dts: qcom: ipq5424-rdp466: xxx
Ok, will add in next revision.
> 
> same for patch 9
ok

[PATCH 9/9] arm64: dts: qcom: ipq5332: Remove eMMC support

[Md Sadre Alam]

Remove eMMC support from the IPQ5332 RDP442 board configuration to
align with the board's default NOR+NAND boot mode design.

The IPQ5332 RDP442 board is designed with NOR+NAND as the default boot
mode configuration. The eMMC and SPI NAND interface share
same GPIO

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 34 ---------------------
 1 file changed, 34 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
index ed8a54eb95c0..6e2abde9ed89 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
@@ -35,17 +35,6 @@ flash@0 {
 	};
 };
 
-&sdhc {
-	bus-width = <4>;
-	max-frequency = <192000000>;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	non-removable;
-	pinctrl-0 = <&sdc_default_state>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
 &tlmm {
 	i2c_1_pins: i2c-1-state {
 		pins = "gpio29", "gpio30";
@@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state {
 		bias-pull-up;
 	};
 
-	sdc_default_state: sdc-default-state {
-		clk-pins {
-			pins = "gpio13";
-			function = "sdc_clk";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		cmd-pins {
-			pins = "gpio12";
-			function = "sdc_cmd";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-
-		data-pins {
-			pins = "gpio8", "gpio9", "gpio10", "gpio11";
-			function = "sdc_data";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
-
 	spi_0_data_clk_pins: spi-0-data-clk-state {
 		pins = "gpio14", "gpio15", "gpio16";
 		function = "blsp0_spi";
-- 
2.34.1