Re: [PATCH] Fixed data sampling on the correct edge

[Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>]

On Fri, Jan 29, 2010 at 6:37 AM, Pietrek, Markus
<Markus.Pietrek-BU0Y/NROKIiELgA04lAiVw@public.gmane.org> wrote:
> Hi,
>
> it seems to me that the spi_sh_msiof.c driver configures REDG and TEDG wrongly. TEDG==0 outputs data at the **rising edge** of the clock and REDG==0 samples data at the **falling edge** of the clock. Therefore for SPI, TEDG must be equal to REDG, otherwise the last byte received is not sampled in the SPI mode 3
>
> The SH7723 HW Reference Manual explains the setting in Figure 20.20 and Figure 20.21 ("SPI Clock and data timing")
>
>
> Signed-off-by: Markus Pietrek <markus.pietrek-BU0Y/NROKIiELgA04lAiVw@public.gmane.org>
> Acked-by: Magnus Damm <damm-yzvPICuk2ACczHhG9Qg4qA@public.gmane.org>

Patch is whitespace damaged and so doesn't cleanly apply.  It's been
picked up anyway since this one is pretty trivial, but you should look
into fixing your mailer for sending patches.

Thanks,
g.

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