From mboxrd@z Thu Jan 1 00:00:00 1970 From: jassi brar Subject: Re: [PATCH] drivers: spi-gpio: add support for controllers without MISO or MOSI pin Date: Thu, 1 Apr 2010 20:17:01 +0900 Message-ID: References: <1270118151-13286-1-git-send-email-m.szyprowski@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, David Brownell To: Marek Szyprowski Return-path: In-Reply-To: <1270118151-13286-1-git-send-email-m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org On Thu, Apr 1, 2010 at 7:35 PM, Marek Szyprowski wrote: > There are some boards that do not strictly follow SPI standard and use > only 3 wires (SCLK, MOSI or MISO, SS) for connecting some simple auxiliary > chips and controls them with GPIO based 'spi controller'. In this > configuration the MISO or MOSI line is missing (it is not required if the > chip does not transfer any data back to host or host only reads data from > chip). > > This patch adds support for such non-standard configuration in GPIO-based > SPI controller. It has been tested in configuration without MISO pin. Though not very clear atm, but wouldn't having some ineffective virtual GPIO assigned to this non-existing MISO/MOSI do the trick? ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev