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Mon, 19 Oct 2026 12:00:06 -0700 (PDT) Received: from silicon.doe.home ([148.69.129.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e1d818237sm702781f8f.27.2026.10.19.12.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 12:00:04 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-arm-kernel@lists.infradead.org, Navid Ghahremani Cc: arnd@arndb.de, krzk@kernel.org, Navid Ghahremani , Mark Brown , Philipp Zabel , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Subject: Re: [PATCH v2 20/24] spi: zx: Add ZTE ZX family SPI flash controller driver Date: Mon, 19 Oct 2026 14:15:30 +0200 Message-ID: In-Reply-To: <20261014072109.1759502-21-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-21-ghahramani.navid@gmail.com> X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPartw_T8zL-ZTluB82Us-2CIWw"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPartw_T8zL-ZTluB82Us-2CIWw Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Date: Mon, 19 Oct 2026 14:15:30 +0200 Message-ID: In-Reply-To: <20261014072109.1759502-21-ghahramani.navid@gmail.com> MIME-Version: 1.0 Hi Navid, I had some time to review the changes you made to my SPI driver. I'll grab the code style changes, they seem in line with kernel guidelines.= Of=20 course it'll only live in my gitlab repo for the time being. Am Mittwoch, 14. Oktober 2026, 09:21:00 Mitteleurop=C3=A4ische Sommerzeit s= chrieb=20 Navid Ghahremani: > +static int zx_qspi_set_speed(struct zx_qspi *qspi, unsigned int max_hz) > +{ > + unsigned long rate; > + long rounded; > + int ret; > + > + if (!max_hz) > + return -EINVAL; > + if (qspi->speed_hz =3D=3D max_hz) > + return 0; > + > + rounded =3D clk_round_rate(qspi->wclk, max_hz); > + if (rounded < 0) > + return rounded; > + if (!rounded || rounded > max_hz) > + return -EINVAL; > + > + ret =3D clk_set_rate(qspi->wclk, rounded); > + if (ret) > + return ret; > + rate =3D clk_get_rate(qspi->wclk); > + if (!rate || rate > max_hz) > + return -EINVAL; > + qspi->speed_hz =3D rate; > + > + return 0; > +} I think the idea of op->max_freq is that it is the SPI bus clock, not the=20 controller clock. Existing drivers aren't quite consistent on it though (or= =20 there's HW without a divider register). spi-ma35d1-qspi.c for example sets = the=20 controller's clock divider rather than the clock. So IOW, this function should primarily configure ZX_QSPI_TIMING_REG. If the= =20 target clock can't be achieved with the controller input clock (e.g. divide= r=20 is larger than ZX_QSPI_TIMING_REG supports or clock rate is lower than=20 requested SPI speed), then a change to the wclk is in order.=20 > + ctrl->min_speed_hz =3D clk_round_rate(qspi->wclk, 1); > + ctrl->max_speed_hz =3D 50000000; This looks wrong - the max speed is probably the highest possible wclk rate= ,=20 the lowest speed the lowest possible wclk rate divided by the highest possi= ble=20 divider. > + /* Ensure proper data sampling point */ > + reg =3D readl_relaxed(qspi->io_base + ZX_QSPI_TIMING_REG); > + if (!FIELD_GET(GENMASK(17, 16), reg)) { > + reg |=3D FIELD_PREP(GENMASK(17, 16), 1); > + writel_relaxed(reg, qspi->io_base + ZX_QSPI_TIMING_REG); > + } I don't know what this is doing. Can you elaborate? Cheers, Stefan --nextPartw_T8zL-ZTluB82Us-2CIWw Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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