* Re: [PATCH 1/2] spi: dt-bindings: qcom,spi-geni-qcom: Add property to force GSI mode
From: Mark Brown @ 2026-06-14 10:55 UTC (permalink / raw)
To: Pengyu Luo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Andy Gross,
Bjorn Andersson, linux-arm-msm, linux-spi, devicetree,
linux-kernel
In-Reply-To: <20260614083424.464132-1-mitltlatltl@gmail.com>
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On Sun, Jun 14, 2026 at 04:34:23PM +0800, Pengyu Luo wrote:
> Some devices (such as gaokun3) do not disable FIFO mode, causing the
> driver to fallback to FIFO mode by default. However, these platforms
> also support GSI mode, which is highly preferred for certain
> peripherals like SPI touchscreens to improve performance.
>
> Introduce the "qcom,force-gsi-mode" device property to hint and force
> the controller into GSI mode during initialization.
This is an optimisation not a fundamental part of how these devices
operate. The DT should describe whatever it is about these SoCs that
allows this mode, or this should be triggered based on the compatible
for the variant of the device that can do this.
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^ permalink raw reply
* Patchwork summary for: spi-devel-general
From: patchwork-bot+spi-devel-general @ 2026-06-14 10:40 UTC (permalink / raw)
To: linux-spi, broonie
Hello:
The following patches were marked "accepted", because they were applied to
broonie/spi.git (for-next):
Patch: spi: Fix mismatched DT property access types
Submitter: Rob Herring <robh@kernel.org>
Committer: Mark Brown <broonie@kernel.org>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1110888
Lore link: https://lore.kernel.org/r/20260612215017.1884893-1-robh@kernel.org
Total patches: 1
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH] spi: Fix mismatched DT property access types
From: Mark Brown @ 2026-06-14 0:18 UTC (permalink / raw)
To: Yang Shen, Rob Herring (Arm); +Cc: linux-spi, linux-kernel
In-Reply-To: <20260612215017.1884893-1-robh@kernel.org>
On Fri, 12 Jun 2026 16:50:17 -0500, Rob Herring (Arm) wrote:
> spi: Fix mismatched DT property access types
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2
Thanks!
[1/1] spi: Fix mismatched DT property access types
https://git.kernel.org/broonie/spi/c/f846d6899214
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* [PATCH 2/2] spi: qcom-geni: Add property to force GSI mode
From: Pengyu Luo @ 2026-06-14 8:34 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson
Cc: linux-arm-msm, linux-spi, devicetree, linux-kernel, Pengyu Luo
In-Reply-To: <20260614083424.464132-1-mitltlatltl@gmail.com>
Some devices (such as gaokun3) do not disable FIFO mode, causing the
driver to fallback to FIFO mode by default. However, these platforms
also support GSI mode, which is highly preferred for certain
peripherals like SPI touchscreens to improve performance.
Introduce the "qcom,force-gsi-mode" device property to hint and force
the controller into GSI mode during initialization.
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
---
drivers/spi/spi-geni-qcom.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index 26e723cfea61..eece7312f780 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -102,6 +102,7 @@ struct spi_geni_master {
int irq;
bool cs_flag;
bool abort_failed;
+ bool force_gsi_mode;
struct dma_chan *tx;
struct dma_chan *rx;
int cur_xfer_mode;
@@ -655,6 +656,9 @@ static int spi_geni_init(struct spi_geni_master *mas)
mas->oversampling = 1;
fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
+ if (mas->force_gsi_mode)
+ fifo_disable = 1;
+
switch (fifo_disable) {
case 1:
ret = spi_geni_grab_gpi_chan(mas);
@@ -1133,6 +1137,9 @@ static int spi_geni_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (device_property_read_bool(&pdev->dev, "qcom,force-gsi-mode"))
+ mas->force_gsi_mode = true;
+
ret = spi_geni_init(mas);
if (ret)
return ret;
--
2.54.0
^ permalink raw reply related
* [PATCH 1/2] spi: dt-bindings: qcom,spi-geni-qcom: Add property to force GSI mode
From: Pengyu Luo @ 2026-06-14 8:34 UTC (permalink / raw)
To: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson
Cc: linux-arm-msm, linux-spi, devicetree, linux-kernel, Pengyu Luo
Some devices (such as gaokun3) do not disable FIFO mode, causing the
driver to fallback to FIFO mode by default. However, these platforms
also support GSI mode, which is highly preferred for certain
peripherals like SPI touchscreens to improve performance.
Introduce the "qcom,force-gsi-mode" device property to hint and force
the controller into GSI mode during initialization.
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
---
.../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index edf399681d7a..80e394c1c715 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -45,6 +45,11 @@ properties:
- const: tx
- const: rx
+ qcom,force-gsi-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Use DMA (GSI) mode, even if FIFO mode is not disabled.
+
interconnects:
minItems: 2
maxItems: 3
--
2.54.0
^ permalink raw reply related
* Patchwork housekeeping for: spi-devel-general
From: patchwork-bot+spi-devel-general @ 2026-06-13 19:57 UTC (permalink / raw)
To: linux-spi, broonie
Latest series: [v2] spi: dt-bindings: octeon: Convert to DT schema (2026-06-13T19:22:33)
Superseding: [v1] spi: dt-bindings: octeon: Convert to DT schema (2026-06-07T14:23:56):
spi: dt-bindings: octeon: Convert to DT schema
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* [PATCH v2] spi: dt-bindings: octeon: Convert to DT schema
From: Ninad Naik @ 2026-06-13 19:22 UTC (permalink / raw)
To: broonie, robh, krzk+dt, conor+dt, david.daney
Cc: linux-spi, devicetree, linux-kernel, me, linux-kernel-mentees,
skhan, Ninad Naik
Convert octeon-3010 to DT schema
Signed-off-by: Ninad Naik <ninadnaik07@gmail.com>
---
Changes in v2:
- Change the maintainer from Mark Brown to David Daney.
- Use soc node wrapper instead of root node in the example to handle
address-cells and size-cells requirements.
- Remove interrupt controller provider from the example.
.../bindings/spi/cavium,octeon-3010-spi.yaml | 61 +++++++++++++++++++
.../devicetree/bindings/spi/spi-octeon.txt | 33 ----------
2 files changed, 61 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-octeon.txt
diff --git a/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml b/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml
new file mode 100644
index 000000000000..e35e661d0a58
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cavium,octeon-3010-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cavium, Inc. OCTEON SoC SPI master controller
+
+description:
+ The Cavium OCTEON SPI controller is an SPI master controller found in
+ OCTEON SoCs.
+
+maintainers:
+ - David Daney <david.daney@cavium.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ const: cavium,octeon-3010-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spi@1070000001000 {
+ compatible = "cavium,octeon-3010-spi";
+ reg = <0x10700 0x00001000 0x0 0x100>;
+ interrupts = <0 58>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "st,m95256", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <64>;
+ size = <32768>;
+ address-width = <16>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
deleted file mode 100644
index 431add192342..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-octeon.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Cavium, Inc. OCTEON SOC SPI master controller.
-
-Required properties:
-- compatible : "cavium,octeon-3010-spi"
-- reg : The register base for the controller.
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
- spi@1070000001000 {
- compatible = "cavium,octeon-3010-spi";
- reg = <0x10700 0x00001000 0x0 0x100>;
- interrupts = <0 58>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- eeprom@0 {
- compatible = "st,m95256", "atmel,at25";
- reg = <0>;
- spi-max-frequency = <5000000>;
- spi-cpha;
- spi-cpol;
-
- pagesize = <64>;
- size = <32768>;
- address-width = <16>;
- };
- };
-
--
2.54.0
^ permalink raw reply related
* Re: [PATCHv2 0/4] m68k: coldfire: fix non-standard readX()/writeX() functions
From: Paolo Abeni @ 2026-06-13 9:22 UTC (permalink / raw)
To: Greg Ungerer, linux-m68k
Cc: linux-kernel, arnd, wei.fang, frank.li, shenwei.wang, imx, netdev,
nico, adureghello, ulfh, linux-mmc, linux-can, linux-spi, olteanv
In-Reply-To: <20260609142139.1563360-1-gerg@linux-m68k.org>
On 6/9/26 4:12 PM, Greg Ungerer wrote:
> This odd collection of patches is aimed at fixing the non-standard ColdFire
> set of readX()/writeX() IO access functions. Instead switching to using the
> asm-generic definitions in include/asm-generic/io.h. The difficulty comes
> in trying not to break any drivers with this change.
>
> The implementation of the readX()/writeX() family of IO access functions
> is non-standard on ColdFire platforms. They either return big-endian (that
> is native endian) data, or on platforms with PCI bus support check the
> supplied address and return either big or little endian data based on that
> check. This is non-standard, they are expected to always return
> little-endian byte ordered data. Unfortunately this behavior also means
> that ioreadX()/iowroteX() and their big-endian counter parts
> ioreadXbe()/iowriteXbe() are currently broken because they are implemented
> using the readX()/writeX() functions.
>
> Patches 1, 2 and 3 in this series are specific driver changes that can be
> made independently of the final ColdFire readX()/writeX() change.
>
> Patch 4 is the actual switch to ColdFire building using asm-generic
> readX()/writeX(), but also contains three driver fixes that are not easily
> handled independently.
>
> Note that I don't have access to all supported hardware needed to fully
> test all these changes. I have tested what I have, a bunch of the standard
> Freescale ColdFire eval boards, and inspected generated code for differences.
>
> Note also that patch 3 relies on changes that are currently only in
> linux-next, and are scheduled to hit mainline during the next v7.2
> merge window. Those changes are also available in an immutable git tree
> at git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git
> cf-internal-io branch.
I understand that with this series you are targeting the m68K tree, am I
correct?
A possibly better option would be, after that the pre-req patches land
into Linus's tree, to share an immutable branch for this series, so that
both m68k and net-next could pull it.
/P
^ permalink raw reply
* Re: [PATCH v1 1/2] dt-bindings: spi: snps,dw-apb-ssi: Add support for snps,dwc-ssi-2.00a
From: Changhuang Liang @ 2026-06-13 3:38 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
In-Reply-To: <20260612-mute-aqueduct-029ac227314e@spud>
Hi, Conor
Thanks for the review.
> On Fri, Jun 12, 2026 at 05:58:55AM -0700, Changhuang Liang wrote:
> > Add a new compatible string "snps,dwc-ssi-2.00a" for the Synopsys
> > DesignWare SSI controller version 2.00a.
>
> Two things. Firstly, driver patch suggests a fallback to 1.01a is possible. Why
> haven't you added one?
Will support fallback.
> Secondly, I am going to expect that when your starfive user for this appears in
> my inbox that it has a device-specific compatible, so you may as well add that
> now.
Our standard SPI control is completely based on the Synopsys DesignWare SSI controller version 2.00a.
However, for the controller that accesses the flash, a set of modifications has been made based on the
Synopsys DesignWare SSI controller version 2.00a, and the driver part also requires specific adaptation.
Therefore, on the JHB100 SoC, the initial device tree source I have planned looks like this:
spi0: spi@17f20000 {
compatible = "snps,dwc-ssi-2.00a";
reg = <0x0 0x17f20000 0x0 0x10000>;
};
sfc0: spi@18000000 {
compatible = "starfive,jhb100-spi";
reg = <0x0 0x18000000 0x0 0x10000>;
};
Thus, I plan to add a new "starfive,jhb100-spi" compatible string for the controller that accesses the flash.
For now, I intend to keep these as two separate series.
Best Regards
Changhuang
^ permalink raw reply
* Re: [PATCH v2 02/14] firewire: core: Open-code topology list walk
From: Takashi Sakamoto @ 2026-06-13 2:11 UTC (permalink / raw)
To: Kaitao Cheng
Cc: Andy Shevchenko, Muchun Song, Philipp Reisner, Lars Ellenberg,
Christoph Böhmwalder, Jens Axboe, Andrzej Hajda,
Neil Armstrong, Robert Foss, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Christian Koenig,
Huang Rui, Eddie James, Mark Brown, Maxime Coquelin,
Alexandre Torgue, Laxman Dewangan, Thierry Reding,
Jonathan Hunter, Sowjanya Komatineni, Davidlohr Bueso,
Paul E . McKenney, Josh Triplett, Peter Zijlstra, Ingo Molnar,
Will Deacon, Boqun Feng, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Matthew Auld, Matthew Brost, Waiman Long, drbd-dev, linux-block,
linux1394-devel, dri-devel, intel-gfx, linux-spi, linux-stm32,
linux-arm-kernel, linux-tegra, linux-sound, linux-kernel,
Andrew Morton, Randy Dunlap, Christian Brauner, David Howells,
Luca Ceresoli, Kaitao Cheng
In-Reply-To: <20260609061347.93688-3-kaitao.cheng@linux.dev>
Hi,
On Tue, Jun 09, 2026 at 02:13:35PM +0800, Kaitao Cheng wrote:
> From: Kaitao Cheng <chengkaitao@kylinos.cn>
>
> A later change will make list_for_each_entry() cache the next element
> before entering the loop body. for_each_fw_node() intentionally appends
> newly discovered child nodes to the temporary walk list while the list is
> being traversed.
>
> Keep the loop open-coded so the next node is looked up only after
> children have been appended. This preserves the current breadth-first
> traversal semantics and prepares the code for the list iterator update.
>
> Signed-off-by: Kaitao Cheng <chengkaitao@kylinos.cn>
> ---
> drivers/firewire/core-topology.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Thanks for the patch.
Last September I've realized the issue but not solved yet[1]. A pointer
array would be another candidate to store the found nodes, since IEEE 1394
bus a restriction about the maximum number of nodes up to 256. But It is
too large if put in kernel stack, while it is slightly difficult to keep
it in heap dynamically since the function is called under holding
spinning lock.
Anyway, there is no objection to your change. Let me apply it to
for-next branch so that your further work goes well with no blocks
locating in this subsystem.
[1] https://social.kernel.org/notice/AyDqvLkpwUvI5eyokK
Thanks
Takashi Sakamoto
^ permalink raw reply
* Re: [PATCH] spi: spi-mem: Fix spi_controller_mem_ops kdoc
From: Mark Brown @ 2026-06-12 13:10 UTC (permalink / raw)
To: Miquel Raynal; +Cc: Thomas Petazzoni, Michael Walle, linux-spi, linux-kernel
In-Reply-To: <20260612-perso-fix-no-cs-assertion-kdoc-v1-1-626b2d6d0d9b@bootlin.com>
On Fri, 12 Jun 2026 10:58:07 +0200, Miquel Raynal wrote:
> spi: spi-mem: Fix spi_controller_mem_ops kdoc
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2
Thanks!
[1/1] spi: spi-mem: Fix spi_controller_mem_ops kdoc
https://git.kernel.org/broonie/spi/c/c0a5405ec38b
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH v2] spi: xilinx: use FIFO occupancy register to determine buffer size
From: Mark Brown @ 2026-06-12 13:21 UTC (permalink / raw)
To: Michal Simek, linux-spi, linux-arm-kernel, linux-kernel,
lars.poeschel.linux
Cc: Amit Kumar, Lars Pöschel
In-Reply-To: <20260612105244.9076-1-lars.poeschel.linux@edag.com>
On Fri, 12 Jun 2026 12:52:44 +0200, lars.poeschel.linux@edag.com wrote:
> spi: xilinx: use FIFO occupancy register to determine buffer size
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2
Thanks!
[1/1] spi: xilinx: use FIFO occupancy register to determine buffer size
https://git.kernel.org/broonie/spi/c/47f3b5365536
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* [PATCH] spi: Fix mismatched DT property access types
From: Rob Herring (Arm) @ 2026-06-12 21:50 UTC (permalink / raw)
To: Mark Brown, Yang Shen; +Cc: linux-spi, linux-kernel
The SPI drivers read properties whose bindings use normal uint32 cells.
Using boolean or u16 helpers makes the access look like a different DT
encoding and causes the property checker to flag the call sites.
Use presence checks for unsupported properties and read numeric cell
properties through u32 helpers before assigning to driver fields.
Assisted-by: Codex:gpt-5-5
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
drivers/spi/spi-fsl-espi.c | 2 +-
drivers/spi/spi-hisi-kunpeng.c | 6 ++++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 45b9974ae911..7e8c1a124463 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -760,7 +760,7 @@ static int of_fsl_espi_probe(struct platform_device *ofdev)
unsigned int irq, num_cs;
int ret;
- if (of_property_read_bool(np, "mode")) {
+ if (of_property_present(np, "mode")) {
dev_err(dev, "mode property is not supported on ESPI!\n");
return -EINVAL;
}
diff --git a/drivers/spi/spi-hisi-kunpeng.c b/drivers/spi/spi-hisi-kunpeng.c
index 046bd894040b..0e61bf0bf2a4 100644
--- a/drivers/spi/spi-hisi-kunpeng.c
+++ b/drivers/spi/spi-hisi-kunpeng.c
@@ -463,6 +463,7 @@ static int hisi_spi_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct spi_controller *host;
struct hisi_spi *hs;
+ u32 num_cs;
int ret, irq;
irq = platform_get_irq(pdev, 0);
@@ -495,10 +496,11 @@ static int hisi_spi_probe(struct platform_device *pdev)
if (host->max_speed_hz == 0)
return dev_err_probe(dev, -EINVAL, "spi-max-frequency can't be 0\n");
- ret = device_property_read_u16(dev, "num-cs",
- &host->num_chipselect);
+ ret = device_property_read_u32(dev, "num-cs", &num_cs);
if (ret)
host->num_chipselect = DEFAULT_NUM_CS;
+ else
+ host->num_chipselect = num_cs;
host->use_gpio_descriptors = true;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
--
2.53.0
^ permalink raw reply related
* Re: [GIT PULL] SPI fixes for v7.1-rc7
From: pr-tracker-bot @ 2026-06-12 18:25 UTC (permalink / raw)
To: Mark Brown; +Cc: Linus Torvalds, linux-spi, linux-kernel, Mark Brown
In-Reply-To: <20260612175231.46F121AC5AC5@finisterre.sirena.org.uk>
The pull request you sent on Fri, 12 Jun 2026 18:52:25 +0100:
> https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git tags/spi-fix-v7.1-rc7
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/28608283615e5e7e92ea79c8ea13507f4b5e0cbe
Thank you!
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* [GIT PULL] SPI fixes for v7.1-rc7
From: Mark Brown @ 2026-06-12 17:52 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linux-spi, linux-kernel, Mark Brown
The following changes since commit 79378db6a86c7014cce40b65252e6c18f5b8bcc2:
spi: spi-mem: avoid mutating op template in spi_mem_supports_op() (2026-05-28 13:49:00 +0100)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git tags/spi-fix-v7.1-rc7
for you to fetch changes up to 3c60184e39b57e5efe664fe8540cdbc1bc7ea899:
spi: dw: fix race between IRQ handler and error handler on SMP (2026-06-10 00:07:39 +0100)
----------------------------------------------------------------
spi: Fixes for v7.1
A couple of driver specific fixes for v7.1, a small targetted fix for
hardware error handling on DesignWare controllers and another for
handling of custom chip select managmenet on Qualcomm GENI controllers.
----------------------------------------------------------------
Peng Yang (1):
spi: dw: fix race between IRQ handler and error handler on SMP
Viken Dadhaniya (1):
spi: qcom-geni: Fix cs_change handling on the last transfer
drivers/spi/spi-dw-core.c | 2 ++
drivers/spi/spi-geni-qcom.c | 27 +++++++++++++++++++--------
2 files changed, 21 insertions(+), 8 deletions(-)
^ permalink raw reply
* Re: [PATCH v3 2/4] spi: qcom-geni: Use geni_se_resources_init() for resource initialization
From: Mark Brown @ 2026-06-12 17:28 UTC (permalink / raw)
To: Praveen Talari
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
bjorn.andersson, linux-arm-msm, linux-spi, devicetree,
linux-kernel, mukesh.savaliya, aniket.randive, chandana.chiluveru,
jyothi.seerapu, chiluka.harish
In-Reply-To: <20260604-enable-spi-on-sa8255p-v3-2-43984eac4c67@oss.qualcomm.com>
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On Thu, Jun 04, 2026 at 12:20:36PM +0530, Praveen Talari wrote:
> - ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
> + ret = geni_se_resources_init(&mas->se);
> if (ret)
> return ret;
Doesn't this still make qup-memory mandatory, breaking existing DTs that
might not supply it?
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* Patchwork summary for: spi-devel-general
From: patchwork-bot+spi-devel-general @ 2026-06-12 17:00 UTC (permalink / raw)
To: linux-spi, broonie
Hello:
The following patches were marked "accepted", because they were applied to
broonie/spi.git (for-next):
Series: mtd: spinand: Winbond continuous read support
Submitter: Miquel Raynal <miquel.raynal@bootlin.com>
Committer: Miquel Raynal <miquel.raynal@bootlin.com>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1087653
Lore link: https://lore.kernel.org/r/20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com
Patches: [v3,01/11] mtd: spinand: Drop a too strong limitation
[v3,02/11] mtd: spinand: Expose spinand_op_is_odtr()
[v3,03/11] mtd: spinand: Drop ECC dirmaps
[v3,04/11] spi: spi-mem: Transform the read operation template
[v3,05/11] spi: spi-mem: Create a secondary read operation
Patch: [v2] spi: xilinx: use FIFO occupancy register to determine buffer size
Submitter: Lars Pöschel <lars.poeschel.linux@edag.com>
Committer: Mark Brown <broonie@kernel.org>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1110579
Lore link: https://lore.kernel.org/r/20260612105244.9076-1-lars.poeschel.linux@edag.com
Series: spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62
Submitter: Miquel Raynal <miquel.raynal@bootlin.com>
Committer: Miquel Raynal <miquel.raynal@bootlin.com>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1073081
Lore link: https://lore.kernel.org/r/20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com
Patches: [1/4] spi: spi-mem: Add a no_cs_assertion capability
Patch: spi: spi-mem: Fix spi_controller_mem_ops kdoc
Submitter: Miquel Raynal <miquel.raynal@bootlin.com>
Committer: Mark Brown <broonie@kernel.org>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1110528
Lore link: https://lore.kernel.org/r/20260612-perso-fix-no-cs-assertion-kdoc-v1-1-626b2d6d0d9b@bootlin.com
Total patches: 8
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^ permalink raw reply
* Re: [PATCH v1 1/2] dt-bindings: spi: snps,dw-apb-ssi: Add support for snps,dwc-ssi-2.00a
From: Conor Dooley @ 2026-06-12 16:46 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown,
linux-spi, linux-kernel, devicetree
In-Reply-To: <20260612125856.8530-2-changhuang.liang@starfivetech.com>
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On Fri, Jun 12, 2026 at 05:58:55AM -0700, Changhuang Liang wrote:
> Add a new compatible string "snps,dwc-ssi-2.00a" for the Synopsys
> DesignWare SSI controller version 2.00a.
Two things. Firstly, driver patch suggests a fallback to 1.01a is
possible. Why haven't you added one?
Secondly, I am going to expect that when your starfive user for this
appears in my inbox that it has a device-specific compatible, so you may
as well add that now.
pw-bot: changes-requested
Cheers,
Conor.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index 8ebebcebca16..fb74243d4bdf 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -41,6 +41,7 @@ properties:
> enum:
> - snps,dw-apb-ssi
> - snps,dwc-ssi-1.01a
> + - snps,dwc-ssi-2.00a
> - description: Microchip Sparx5 SoC SPI Controller
> const: microchip,sparx5-spi
> - description: Amazon Alpine SPI Controller
> --
> 2.25.1
>
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* [PATCH v1 1/2] dt-bindings: spi: snps,dw-apb-ssi: Add support for snps,dwc-ssi-2.00a
From: Changhuang Liang @ 2026-06-12 12:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown
Cc: linux-spi, linux-kernel, devicetree, Changhuang Liang
In-Reply-To: <20260612125856.8530-1-changhuang.liang@starfivetech.com>
Add a new compatible string "snps,dwc-ssi-2.00a" for the Synopsys
DesignWare SSI controller version 2.00a.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index 8ebebcebca16..fb74243d4bdf 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -41,6 +41,7 @@ properties:
enum:
- snps,dw-apb-ssi
- snps,dwc-ssi-1.01a
+ - snps,dwc-ssi-2.00a
- description: Microchip Sparx5 SoC SPI Controller
const: microchip,sparx5-spi
- description: Amazon Alpine SPI Controller
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v4 2/3] spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler
From: Mark Brown @ 2026-06-12 16:08 UTC (permalink / raw)
To: Vishwaroop A
Cc: Thierry Reding, Jon Hunter, Laxman Dewangan, Sowjanya Komatineni,
Breno Leitao, Suresh Mangipudi, Krishna Yarlagadda, linux-tegra,
linux-spi, linux-kernel
In-Reply-To: <2ed90a7d175f7967e621943b772115da655c477d.1781037385.git.va@nvidia.com>
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On Wed, Jun 10, 2026 at 06:24:01AM +0000, Vishwaroop A wrote:
> - tegra_qspi_isr() reads QSPI_FIFO_STATUS and QSPI_TRANS_STATUS,
> derives tx_status / rx_status, then publishes them via WRITE_ONCE()
> and the trans_status cache via smp_store_release() before masking
> and acking the controller IRQ.
> - tegra_qspi_handle_timeout() consumes trans_status with a paired
> smp_load_acquire(). The release/acquire pair guarantees that a
> timeout handler which observes a non-zero trans_status also
> observes the matching status_reg / tx_status / rx_status updates.
> - tegra_qspi_setup_transfer_one() clears the cache with
> smp_store_release() under the spinlock before unmasking the IRQ
> for the new transfer, so a stale RDY bit from the previous
> transfer cannot fool the timeout handler.
It looks like the CPU based transfer function supports multiple
interrupts per transfer, though the copybreak for switching to DMA is
FIFO sized so I'm not clear exactly when that might happen. Can that
happen, and if so don't we need to clear trans_status when we handle the
interrupt as well? It might be that this can't actually happen.
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* Re: [PATCH v3 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI
From: Conor Dooley @ 2026-06-12 15:48 UTC (permalink / raw)
To: Chi-Wen Weng
Cc: broonie, robh, krzk+dt, conor+dt, linux-arm-kernel, linux-spi,
devicetree, linux-kernel, cwweng
In-Reply-To: <0031379c-0cc3-40c8-8145-5b1991b42f05@gmail.com>
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On Fri, Jun 12, 2026 at 08:33:01AM +0800, Chi-Wen Weng wrote:
> Hi Conor,
>
> Thanks for the review.
>
> I will add a default value for num-cs in v4:
>
> num-cs:
> maximum: 2
> default: 2
>
> The controller has two native chip selects and the driver currently uses
> that hardware default.
The driver should handle the property and fall back to the default.
It's not complex to support, so surely there's no reason not to?
Cheers,
Conor.
>
> Best regards,
> Chi-Wen
>
> Conor Dooley 於 2026/6/12 上午 01:34 寫道:
> > On Thu, Jun 11, 2026 at 05:12:45PM +0800, Chi-Wen Weng wrote:
> > > From: Chi-Wen Weng <cwweng@nuvoton.com>
> > >
> > > Add a devicetree binding for the Quad SPI controller found in
> > > Nuvoton MA35D1 SoCs.
> > >
> > > The controller supports SPI memory devices such as SPI NOR and SPI NAND
> > > flashes. It has one register range, one clock input and one reset line,
> > > and supports up to two chip selects.
> > >
> > > Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com>
> > > ---
> > > .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 62 +++++++++++++++++++
> > > 1 file changed, 62 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> > > new file mode 100644
> > > index 000000000000..d3b36e612eb0
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> > > @@ -0,0 +1,62 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Nuvoton MA35D1 Quad SPI Controller
> > > +
> > > +maintainers:
> > > + - Chi-Wen Weng <cwweng@nuvoton.com>
> > > +
> > > +allOf:
> > > + - $ref: /schemas/spi/spi-controller.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + const: nuvoton,ma35d1-qspi
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + num-cs:
> > > + maximum: 2
> > Missing a default of 2, unless you make the property required.
> > FWIW, your driver doesn't appear to read this value.
> >
> > pw-bot: changes-requested
> >
> > Cheers,
> > Conor.
> >
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - clocks
> > > + - resets
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> > > + #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + spi@40680000 {
> > > + compatible = "nuvoton,ma35d1-qspi";
> > > + reg = <0 0x40680000 0 0x100>;
> > > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk QSPI0_GATE>;
> > > + resets = <&sys MA35D1_RESET_QSPI0>;
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + };
> > > + };
> > > +
> > > --
> > > 2.25.1
> > >
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* Re: [PATCH v4 1/3] spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue
From: Mark Brown @ 2026-06-12 15:29 UTC (permalink / raw)
To: Vishwaroop A
Cc: Thierry Reding, Jon Hunter, Laxman Dewangan, Sowjanya Komatineni,
Breno Leitao, Suresh Mangipudi, Krishna Yarlagadda, linux-tegra,
linux-spi, linux-kernel
In-Reply-To: <552afd84ee31c9e475ed1344ea9349af01eacfa1.1781037385.git.va@nvidia.com>
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On Wed, Jun 10, 2026 at 06:24:00AM +0000, Vishwaroop A wrote:
> @@ -1506,6 +1508,19 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi)
> long wait_status;
> int num_errors = 0;
>
> + /*
> + * Snapshot curr_xfer under the lock before the (potentially long)
> + * DMA waits below. The timeout path can clear tqspi->curr_xfer
> + * concurrently; using the local copy keeps the subsequent dma_unmap
> + * and FIFO-drain steps consistent with the transfer that actually
> + * started, and lets us bail safely if cleanup already happened.
> + */
> + spin_lock_irqsave(&tqspi->lock, flags);
> + t = tqspi->curr_xfer;
> + spin_unlock_irqrestore(&tqspi->lock, flags);
> + if (!t)
> + return IRQ_HANDLED;
> +
> if (tqspi->cur_direction & DATA_DIR_TX) {
> if (tqspi->tx_status) {
> if (tqspi->tx_dma_chan)
This can be called from both tegra_qspi_work_handler() and
tegra_qspi_handle_timeout() - I can't see what stops them both handling
and completing the same transfer simultaneously?
> +static void tegra_qspi_work_handler(struct work_struct *work)
> {
> - struct tegra_qspi *tqspi = context_data;
> + * Check if the timeout handler already processed this transfer.
> + * Can happen if the workqueue was delayed and the timeout fired
> + * first. In that case there is nothing to do: tegra_qspi_start_
> + * {cpu,dma}_based_transfer() at the start of the next transfer
> + * (or the next message) re-enables interrupts.
> */
> - spin_lock_irqsave(&tqspi->lock, flags);
> if (!tqspi->curr_xfer) {
> spin_unlock_irqrestore(&tqspi->lock, flags);
> - /* Spurious interrupt - transfer not ready */
> - if (!(status & QSPI_RDY))
> - return IRQ_NONE;
> - /* Real interrupt, already handled by timeout path */
> - return IRQ_HANDLED;
> + return;
> }
Can't the timeout handler also be running at the same time as this
rather than already having handled things?
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* Patchwork summary for: spi-devel-general
From: patchwork-bot+spi-devel-general @ 2026-06-12 14:40 UTC (permalink / raw)
To: linux-spi, broonie
Hello:
The following patches were marked "accepted", because they were applied to
broonie/spi.git (for-next):
Patch: spi: xilinx: let transfers timeout in case of no IRQ
Submitter: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Committer: Mark Brown <broonie@kernel.org>
Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=1109556
Lore link: https://lore.kernel.org/r/20260610222843.782337-1-vadim.fedorenko@linux.dev
Total patches: 1
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* [PATCH v1 0/2] Add support for Synopsys DesignWare SSI controller version 2.00a
From: Changhuang Liang @ 2026-06-12 12:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown
Cc: linux-spi, linux-kernel, devicetree, Changhuang Liang
Add support for Synopsys DesignWare SSI controller version 2.00a,
which is used on the JHB100 SoC.
Changhuang Liang (2):
dt-bindings: spi: snps,dw-apb-ssi: Add support for snps,dwc-ssi-2.00a
spi: dw: Add support for snps,dwc-ssi-2.00a
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
drivers/spi/spi-dw-mmio.c | 1 +
2 files changed, 2 insertions(+)
--
2.25.1
^ permalink raw reply
* Re: [PATCH v1 1/2] dt-bindings: spi: snps,dw-apb-ssi: Add support for snps,dwc-ssi-2.00a
From: Mark Brown @ 2026-06-12 13:31 UTC (permalink / raw)
To: Changhuang Liang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-spi,
linux-kernel, devicetree
In-Reply-To: <20260612125856.8530-2-changhuang.liang@starfivetech.com>
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On Fri, Jun 12, 2026 at 05:58:55AM -0700, Changhuang Liang wrote:
> Add a new compatible string "snps,dwc-ssi-2.00a" for the Synopsys
> DesignWare SSI controller version 2.00a.
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.
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