From mboxrd@z Thu Jan 1 00:00:00 1970 From: Martin Guy Subject: Re: [PATCH v4 1/2] spi: implemented driver for Cirrus EP93xx SPI controller Date: Mon, 26 Apr 2010 13:58:54 +0100 Message-ID: References: <0D753D10438DA54287A00B0270842697636D9B7E4F@AUSP01VMBX24.collaborationhost.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: "spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org" , Mika Westerberg , "ryan-7Wk5F4Od5/oYd5yxfr4S2w@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" To: H Hartley Sweeten Return-path: In-Reply-To: <0D753D10438DA54287A00B0270842697636D9B7E4F-gaq956PjLg32KbjnnMDalRurcAul1UnsRrxOEX5GOmysTnJN9+BGXg@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org On 4/25/10, H Hartley Sweeten wrote: > > - /* clear the interrupt */ > > - ep93xx_spi_write_u8(espi, SSPICR, 0); > > > > /* > > * If we got ROR (receive overrun) interrupt we know that something is > > * wrong. Just abort the message. > > */ > > if (unlikely(irq_status & SSPIIR_RORIS)) { > > + /* clear the overrun interrupt */ > > + ep93xx_spi_write_u8(espi, SSPICR, 0); > > dev_warn(&espi->pdev->dev, > > "receive overrun, aborting the message\n"); > > espi->current_msg->status = -EIO; > > } else { > > With this patch the interrupts only get cleared if it's a ROR interrupt. > > Do the RIS/TIS interrupts get cleared by the upper layers? If so, do we > really need to clear the ROR interrupt here? RX/TX interrupts are cleared by emptying the RX FIFO or filling the TX FIFO to less/more than half full. There is no explicit clearing of the IRQ. The ROR interrupt instead remains active until you explicitly clear it by writing (anything( to SSPICR, so it would remain on forever otherwise. M ------------------------------------------------------------------------------