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From: Mikko Perttunen <mperttunen@nvidia.com>
To: Svyatoslav Ryhel <clamor95@gmail.com>,
 Thierry Reding <thierry.reding@gmail.com>,
 Thierry Reding <treding@nvidia.com>, David Airlie <airlied@gmail.com>,
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 Sowjanya Komatineni <skomatineni@nvidia.com>,
 Luca Ceresoli <luca.ceresoli@bootlin.com>,
 Mauro Carvalho Chehab <mchehab@kernel.org>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
 Hans Verkuil <hverkuil+cisco@kernel.org>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
 linux-tegra@vger.kernel.org, linux-media@vger.kernel.org,
 linux-staging@lists.linux.dev
Subject:
 Re: [PATCH v7 05/15] gpu: host1x: convert MIPI to use operation function
 pointers
Date: Thu, 19 Mar 2026 11:20:58 +0900
Message-ID: <10139201.lOV4Wx5bFT@senjougahara>
In-Reply-To: <31e56301-2764-4d3b-bc21-555227248e5f@kernel.org>
References:
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 <20260303084239.15007-6-clamor95@gmail.com>
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On Tuesday, March 17, 2026 10:07=E2=80=AFPM Hans Verkuil wrote:
> Hi Svyatoslav, Mikko, Thierry,
>=20
> On 03/03/2026 09:42, Svyatoslav Ryhel wrote:
> > Convert existing MIPI code to use operation function pointers, a necess=
ary
> > step for supporting Tegra20/Tegra30 SoCs. All common MIPI configuration
> > that is SoC-independent remains in mipi.c, while all SoC-specific code =
is
> > moved to tegra114-mipi.c (The naming matches the first SoC generation w=
ith
> > a dedicated calibration block). Shared structures and function calls ar=
e
> > placed into tegra-mipi-cal.h.
> >=20
> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, paralle=
l
> > camera Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > Acked-by: Mikko Perttunen <mperttunen@nvidia.com>
>=20
> I would like to merge this series, but in the v5 series there was a
> discussion about this host1x split:
>=20
> https://lore.kernel.org/linux-media/CAPVz0n0fkMYV-O4xWTBELd6HtKR83wrs+DS1=
wTV
> DOXdWuAK2OA@mail.gmail.com/
>=20
> Mikko Acked this patch, but Thierry objected. However, I saw no further
> updates on this, and I do agree with Svyatoslav that this patch makes
> sense.
>=20
> If there are no objections, then I plan to merge series this on Monday fo=
r
> v7.1.

Please do, I believe we ended up resolving that discussion offline.

Thanks,
Mikko

>=20
> Regards,
>=20
> 	Hans
>=20
> > ---
> >=20
> >  drivers/gpu/drm/tegra/dsi.c             |   1 +
> >  drivers/gpu/host1x/Makefile             |   1 +
> >  drivers/gpu/host1x/mipi.c               | 592 +++++-------------------
> >  drivers/gpu/host1x/tegra114-mipi.c      | 483 +++++++++++++++++++
> >  drivers/staging/media/tegra-video/csi.c |   1 +
> >  include/linux/host1x.h                  |  10 -
> >  include/linux/tegra-mipi-cal.h          |  57 +++
> >  7 files changed, 666 insertions(+), 479 deletions(-)
> >  create mode 100644 drivers/gpu/host1x/tegra114-mipi.c
> >  create mode 100644 include/linux/tegra-mipi-cal.h
> >=20
> > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> > index 2c5aefe9621a..7f25c50621c9 100644
> > --- a/drivers/gpu/drm/tegra/dsi.c
> > +++ b/drivers/gpu/drm/tegra/dsi.c
> > @@ -14,6 +14,7 @@
> >=20
> >  #include <linux/pm_runtime.h>
> >  #include <linux/regulator/consumer.h>
> >  #include <linux/reset.h>
> >=20
> > +#include <linux/tegra-mipi-cal.h>
> >=20
> >  #include <video/mipi_display.h>
> >=20
> > diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
> > index ee5286ffe08d..fead483af0b4 100644
> > --- a/drivers/gpu/host1x/Makefile
> > +++ b/drivers/gpu/host1x/Makefile
> > @@ -9,6 +9,7 @@ host1x-y =3D \
> >=20
> >  	job.o \
> >  	debug.o \
> >  	mipi.o \
> >=20
> > +	tegra114-mipi.o \
> >=20
> >  	fence.o \
> >  	hw/host1x01.o \
> >  	hw/host1x02.o \
> >=20
> > diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
> > index fea9f491df66..01513b775d89 100644
> > --- a/drivers/gpu/host1x/mipi.c
> > +++ b/drivers/gpu/host1x/mipi.c
> > @@ -1,215 +1,110 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> >=20
> >  /*
> > =20
> >   * Copyright (C) 2013 NVIDIA Corporation
> >=20
> > - *
> > - * Permission to use, copy, modify, distribute, and sell this software
> > and its - * documentation for any purpose is hereby granted without fee=
,
> > provided that - * the above copyright notice appear in all copies and
> > that both that copyright - * notice and this permission notice appear i=
n
> > supporting documentation, and - * that the name of the copyright holder=
s
> > not be used in advertising or - * publicity pertaining to distribution =
of
> > the software without specific, - * written prior permission.  The
> > copyright holders make no representations - * about the suitability of
> > this software for any purpose.  It is provided "as - * is" without
> > express or implied warranty.
> > - *
> > - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS
> > SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
> > FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY
> > SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVE=
R
> > RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION O=
F
> > CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN
> > CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE.
> > + * Copyright (C) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
> >=20
> >   */
> > =20
> >  #include <linux/clk.h>
> >=20
> > -#include <linux/host1x.h>
> >=20
> >  #include <linux/io.h>
> >  #include <linux/iopoll.h>
> >=20
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> >=20
> >  #include <linux/of_platform.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/slab.h>
> >=20
> > +#include <linux/tegra-mipi-cal.h>
> >=20
> > -#include "dev.h"
> > -
> > -#define MIPI_CAL_CTRL			0x00
> > -#define MIPI_CAL_CTRL_NOISE_FILTER(x)	(((x) & 0xf) << 26)
> > -#define MIPI_CAL_CTRL_PRESCALE(x)	(((x) & 0x3) << 24)
> > -#define MIPI_CAL_CTRL_CLKEN_OVR		(1 << 4)
> > -#define MIPI_CAL_CTRL_START		(1 << 0)
> > -
> > -#define MIPI_CAL_AUTOCAL_CTRL		0x01
> > -
> > -#define MIPI_CAL_STATUS			0x02
> > -#define MIPI_CAL_STATUS_DONE		(1 << 16)
> > -#define MIPI_CAL_STATUS_ACTIVE		(1 <<  0)
> > -
> > -#define MIPI_CAL_CONFIG_CSIA		0x05
> > -#define MIPI_CAL_CONFIG_CSIB		0x06
> > -#define MIPI_CAL_CONFIG_CSIC		0x07
> > -#define MIPI_CAL_CONFIG_CSID		0x08
> > -#define MIPI_CAL_CONFIG_CSIE		0x09
> > -#define MIPI_CAL_CONFIG_CSIF		0x0a
> > -#define MIPI_CAL_CONFIG_DSIA		0x0e
> > -#define MIPI_CAL_CONFIG_DSIB		0x0f
> > -#define MIPI_CAL_CONFIG_DSIC		0x10
> > -#define MIPI_CAL_CONFIG_DSID		0x11
> > -
> > -#define MIPI_CAL_CONFIG_DSIA_CLK	0x19
> > -#define MIPI_CAL_CONFIG_DSIB_CLK	0x1a
> > -#define MIPI_CAL_CONFIG_CSIAB_CLK	0x1b
> > -#define MIPI_CAL_CONFIG_DSIC_CLK	0x1c
> > -#define MIPI_CAL_CONFIG_CSICD_CLK	0x1c
> > -#define MIPI_CAL_CONFIG_DSID_CLK	0x1d
> > -#define MIPI_CAL_CONFIG_CSIE_CLK	0x1d
> > -
> > -/* for data and clock lanes */
> > -#define MIPI_CAL_CONFIG_SELECT		(1 << 21)
> > -
> > -/* for data lanes */
> > -#define MIPI_CAL_CONFIG_HSPDOS(x)	(((x) & 0x1f) << 16)
> > -#define MIPI_CAL_CONFIG_HSPUOS(x)	(((x) & 0x1f) <<  8)
> > -#define MIPI_CAL_CONFIG_TERMOS(x)	(((x) & 0x1f) <<  0)
> > -
> > -/* for clock lanes */
> > -#define MIPI_CAL_CONFIG_HSCLKPDOSD(x)	(((x) & 0x1f) <<  8)
> > -#define MIPI_CAL_CONFIG_HSCLKPUOSD(x)	(((x) & 0x1f) <<  0)
> > -
> > -#define MIPI_CAL_BIAS_PAD_CFG0		0x16
> > -#define MIPI_CAL_BIAS_PAD_PDVCLAMP	(1 << 1)
> > -#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF	(1 << 0)
> > -
> > -#define MIPI_CAL_BIAS_PAD_CFG1		0x17
> > -#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
> > -#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
> > -
> > -#define MIPI_CAL_BIAS_PAD_CFG2		0x18
> > -#define MIPI_CAL_BIAS_PAD_VCLAMP(x)	(((x) & 0x7) << 16)
> > -#define MIPI_CAL_BIAS_PAD_VAUXP(x)	(((x) & 0x7) << 4)
> > -#define MIPI_CAL_BIAS_PAD_PDVREG	(1 << 1)
> > -
> > -struct tegra_mipi_pad {
> > -	unsigned long data;
> > -	unsigned long clk;
> > -};
> > -
> > -struct tegra_mipi_soc {
> > -	bool has_clk_lane;
> > -	const struct tegra_mipi_pad *pads;
> > -	unsigned int num_pads;
> > -
> > -	bool clock_enable_override;
> > -	bool needs_vclamp_ref;
> > -
> > -	/* bias pad configuration settings */
> > -	u8 pad_drive_down_ref;
> > -	u8 pad_drive_up_ref;
> > +/* only need to support one provider */
> > +static struct {
> > +	struct device_node *np;
> > +	const struct tegra_mipi_ops *ops;
> > +} provider;
> >=20
> > -	u8 pad_vclamp_level;
> > -	u8 pad_vauxp_level;
> > -
> > -	/* calibration settings for data lanes */
> > -	u8 hspdos;
> > -	u8 hspuos;
> > -	u8 termos;
> > -
> > -	/* calibration settings for clock lanes */
> > -	u8 hsclkpdos;
> > -	u8 hsclkpuos;
> > -};
> > -
> > -struct tegra_mipi {
> > -	const struct tegra_mipi_soc *soc;
> > -	struct device *dev;
> > -	void __iomem *regs;
> > -	struct mutex lock;
> > -	struct clk *clk;
> > -
> > -	unsigned long usage_count;
> > -};
> > -
> > -struct tegra_mipi_device {
> > -	struct platform_device *pdev;
> > -	struct tegra_mipi *mipi;
> > -	struct device *device;
> > -	unsigned long pads;
> > -};
> > -
> > -static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
> > -				   unsigned long offset)
> > +/**
> > + * tegra_mipi_enable - Enable the Tegra MIPI calibration device.
> > + * @device: Handle to the Tegra MIPI calibration device.
> > + *
> > + * This calls the enable sequence for the Tegra MIPI calibration devic=
e.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int tegra_mipi_enable(struct tegra_mipi_device *device)
> >=20
> >  {
> >=20
> > -	return readl(mipi->regs + (offset << 2));
> > -}
> > +	if (device->ops->enable)
> > +		return device->ops->enable(device);
> >=20
> > -static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 valu=
e,
> > -				     unsigned long offset)
> > -{
> > -	writel(value, mipi->regs + (offset << 2));
> > +	return 0;
> >=20
> >  }
> >=20
> > +EXPORT_SYMBOL(tegra_mipi_enable);
> >=20
> > -static int tegra_mipi_power_up(struct tegra_mipi *mipi)
> > +/**
> > + * tegra_mipi_disable - Disable the Tegra MIPI calibration device.
> > + * @device: Handle to the Tegra MIPI calibration device.
> > + *
> > + * This calls the disable sequence for the Tegra MIPI calibration devi=
ce.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int tegra_mipi_disable(struct tegra_mipi_device *device)
> >=20
> >  {
> >=20
> > -	u32 value;
> > -	int err;
> > -
> > -	err =3D clk_enable(mipi->clk);
> > -	if (err < 0)
> > -		return err;
> > -
> > -	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
> > -	value &=3D ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
> > -
> > -	if (mipi->soc->needs_vclamp_ref)
> > -		value |=3D MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
> > -
> > -	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
> > -
> > -	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > -	value &=3D ~MIPI_CAL_BIAS_PAD_PDVREG;
> > -	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > -
> > -	clk_disable(mipi->clk);
> > +	if (device->ops->disable)
> > +		return device->ops->disable(device);
> >=20
> >  	return 0;
> > =20
> >  }
> >=20
> > +EXPORT_SYMBOL(tegra_mipi_disable);
> >=20
> > -static int tegra_mipi_power_down(struct tegra_mipi *mipi)
> > +/**
> > + * tegra_mipi_start_calibration - Start the Tegra MIPI calibration
> > sequence. + * @device: Handle to the Tegra MIPI calibration device.
> > + *
> > + * This initiates the calibration of CSI/DSI interfaces via the Tegra
> > MIPI
> > + * calibration device.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
> >=20
> >  {
> >=20
> > -	u32 value;
> > -	int err;
> > -
> > -	err =3D clk_enable(mipi->clk);
> > -	if (err < 0)
> > -		return err;
> > -
> > -	/*
> > -	 * The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
> > -	 * supplies the DSI pads. This must be kept enabled until none of the
> > -	 * DSI lanes are used anymore.
> > -	 */
> > -	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > -	value |=3D MIPI_CAL_BIAS_PAD_PDVREG;
> > -	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > -
> > -	/*
> > -	 * MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
> > -	 * control a regulator that supplies current to the pre-driver logic.
> > -	 * Powering down this regulator causes DSI to fail, so it must remain
> > -	 * powered on until none of the DSI lanes are used anymore.
> > -	 */
> > -	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
> > +	if (device->ops->start_calibration)
> > +		return device->ops->start_calibration(device);
> >=20
> > -	if (mipi->soc->needs_vclamp_ref)
> > -		value &=3D ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(tegra_mipi_start_calibration);
> >=20
> > -	value |=3D MIPI_CAL_BIAS_PAD_PDVCLAMP;
> > -	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
> > +/**
> > + * tegra_mipi_finish_calibration - Finish the Tegra MIPI calibration
> > sequence. + * @device: Handle to the Tegra MIPI calibration device.
> > + *
> > + * This completes the calibration of CSI/DSI interfaces via the Tegra
> > MIPI
> > + * calibration device.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int tegra_mipi_finish_calibration(struct tegra_mipi_device *device)
> > +{
> > +	if (device->ops->finish_calibration)
> > +		return device->ops->finish_calibration(device);
> >=20
> >  	return 0;
> > =20
> >  }
> >=20
> > +EXPORT_SYMBOL(tegra_mipi_finish_calibration);
> >=20
> > +/**
> > + * tegra_mipi_request - Request a Tegra MIPI calibration device.
> > + * @device: Handle of the device requesting the MIPI calibration
> > function.
> > + * @np: Device node pointer of the device requesting the MIPI calibrat=
ion
> > + *	function.
> > + *
> > + * This function requests a reference to a Tegra MIPI calibration devi=
ce.
> > + *
> > + * Returns a pointer to the Tegra MIPI calibration device on success,
> > + * or an ERR_PTR-encoded error code on failure.
> > + */
> >=20
> >  struct tegra_mipi_device *tegra_mipi_request(struct device *device,
> > =20
> >  					     struct device_node *np)
> > =20
> >  {
> >=20
> > -	struct tegra_mipi_device *dev;
> > +	struct tegra_mipi_device *mipidev;
> >=20
> >  	struct of_phandle_args args;
> >  	int err;
> >=20
> > @@ -219,321 +114,80 @@ struct tegra_mipi_device *tegra_mipi_request(str=
uct
> > device *device,>=20
> >  	if (err < 0)
> >  =09
> >  		return ERR_PTR(err);
> >=20
> > -	dev =3D kzalloc_obj(*dev);
> > -	if (!dev) {
> > +	if (provider.np !=3D args.np)
> > +		return ERR_PTR(-ENODEV);
> > +
> > +	mipidev =3D kzalloc_obj(*mipidev);
> > +	if (!mipidev) {
> >=20
> >  		err =3D -ENOMEM;
> >  		goto out;
> >  =09
> >  	}
> >=20
> > -	dev->pdev =3D of_find_device_by_node(args.np);
> > -	if (!dev->pdev) {
> > +	mipidev->pdev =3D of_find_device_by_node(args.np);
> > +	if (!mipidev->pdev) {
> >=20
> >  		err =3D -ENODEV;
> >  		goto free;
> >  =09
> >  	}
> >=20
> > -	dev->mipi =3D platform_get_drvdata(dev->pdev);
> > -	if (!dev->mipi) {
> > -		err =3D -EPROBE_DEFER;
> > -		goto put;
> > -	}
> > -
> >=20
> >  	of_node_put(args.np);
> >=20
> > -	dev->pads =3D args.args[0];
> > -	dev->device =3D device;
> > +	mipidev->ops =3D provider.ops;
> > +	mipidev->pads =3D args.args[0];
> >=20
> > -	return dev;
> > +	return mipidev;
> >=20
> > -put:
> > -	platform_device_put(dev->pdev);
> >=20
> >  free:
> > -	kfree(dev);
> > +	kfree(mipidev);
> >=20
> >  out:
> >  	of_node_put(args.np);
> >  	return ERR_PTR(err);
> > =20
> >  }
> >  EXPORT_SYMBOL(tegra_mipi_request);
> >=20
> > -void tegra_mipi_free(struct tegra_mipi_device *device)
> > +/**
> > + * tegra_mipi_free - Free a Tegra MIPI calibration device.
> > + * @mipidev: Handle to the Tegra MIPI calibration device.
> > + *
> > + * This function releases a reference to a Tegra MIPI calibration devi=
ce
> > + * previously requested by tegra_mipi_request().
> > + */
> > +void tegra_mipi_free(struct tegra_mipi_device *mipidev)
> >=20
> >  {
> >=20
> > -	platform_device_put(device->pdev);
> > -	kfree(device);
> > +	platform_device_put(mipidev->pdev);
> > +	kfree(mipidev);
> >=20
> >  }
> >  EXPORT_SYMBOL(tegra_mipi_free);
> >=20
> > -int tegra_mipi_enable(struct tegra_mipi_device *dev)
> > +static void tegra_mipi_remove_provider(void *data)
> >=20
> >  {
> >=20
> > -	int err =3D 0;
> > -
> > -	mutex_lock(&dev->mipi->lock);
> > -
> > -	if (dev->mipi->usage_count++ =3D=3D 0)
> > -		err =3D tegra_mipi_power_up(dev->mipi);
> > -
> > -	mutex_unlock(&dev->mipi->lock);
> > -
> > -	return err;
> > -
> > -}
> > -EXPORT_SYMBOL(tegra_mipi_enable);
> > -
> > -int tegra_mipi_disable(struct tegra_mipi_device *dev)
> > -{
> > -	int err =3D 0;
> > -
> > -	mutex_lock(&dev->mipi->lock);
> > -
> > -	if (--dev->mipi->usage_count =3D=3D 0)
> > -		err =3D tegra_mipi_power_down(dev->mipi);
> > -
> > -	mutex_unlock(&dev->mipi->lock);
> > -
> > -	return err;
> > -
> > -}
> > -EXPORT_SYMBOL(tegra_mipi_disable);
> > -
> > -int tegra_mipi_finish_calibration(struct tegra_mipi_device *device)
> > -{
> > -	struct tegra_mipi *mipi =3D device->mipi;
> > -	void __iomem *status_reg =3D mipi->regs + (MIPI_CAL_STATUS << 2);
> > -	u32 value;
> > -	int err;
> > -
> > -	err =3D readl_relaxed_poll_timeout(status_reg, value,
> > -					 !(value &=20
MIPI_CAL_STATUS_ACTIVE) &&
> > -					 (value & MIPI_CAL_STATUS_DONE),=20
50,
> > -					 250000);
> > -	mutex_unlock(&device->mipi->lock);
> > -	clk_disable(device->mipi->clk);
> > -
> > -	return err;
> > +	provider.np =3D NULL;
> > +	provider.ops =3D NULL;
> >=20
> >  }
> >=20
> > -EXPORT_SYMBOL(tegra_mipi_finish_calibration);
> > -
> > -int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
> > -{
> > -	const struct tegra_mipi_soc *soc =3D device->mipi->soc;
> > -	unsigned int i;
> > -	u32 value;
> > -	int err;
> > -
> > -	err =3D clk_enable(device->mipi->clk);
> > -	if (err < 0)
> > -		return err;
> > -
> > -	mutex_lock(&device->mipi->lock);
> > -
> > -	value =3D MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
> > -		MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
> > -	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
> > -
> > -	value =3D tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > -	value &=3D ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
> > -	value &=3D ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
> > -	value |=3D MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
> > -	value |=3D MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
> > -	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > -
> > -	for (i =3D 0; i < soc->num_pads; i++) {
> > -		u32 clk =3D 0, data =3D 0;
> > -
> > -		if (device->pads & BIT(i)) {
> > -			data =3D MIPI_CAL_CONFIG_SELECT |
> > -			       MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
> > -			       MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
> > -			       MIPI_CAL_CONFIG_TERMOS(soc->termos);
> > -			clk =3D MIPI_CAL_CONFIG_SELECT |
> > -			      MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
> > -			      MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
> > -		}
> >=20
> > -		tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
> > -
> > -		if (soc->has_clk_lane && soc->pads[i].clk !=3D 0)
> > -			tegra_mipi_writel(device->mipi, clk, soc-
>pads[i].clk);
> > -	}
> > -
> > -	value =3D tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
> > -	value &=3D ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
> > -	value &=3D ~MIPI_CAL_CTRL_PRESCALE(0x3);
> > -	value |=3D MIPI_CAL_CTRL_NOISE_FILTER(0xa);
> > -	value |=3D MIPI_CAL_CTRL_PRESCALE(0x2);
> > -
> > -	if (!soc->clock_enable_override)
> > -		value &=3D ~MIPI_CAL_CTRL_CLKEN_OVR;
> > -	else
> > -		value |=3D MIPI_CAL_CTRL_CLKEN_OVR;
> > -
> > -	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
> > -
> > -	/* clear any pending status bits */
> > -	value =3D tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
> > -	tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
> > -
> > -	value =3D tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
> > -	value |=3D MIPI_CAL_CTRL_START;
> > -	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
> > -
> > -	/*
> > -	 * Wait for min 72uS to let calibration logic finish calibration
> > -	 * sequence codes before waiting for pads idle state to apply the
> > -	 * results.
> > -	 */
> > -	usleep_range(75, 80);
> > -
> > -	return 0;
> > -}
> > -EXPORT_SYMBOL(tegra_mipi_start_calibration);
> > -
> > -static const struct tegra_mipi_pad tegra114_mipi_pads[] =3D {
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIA },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIB },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIC },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSID },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIE },
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIA },
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIB },
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIC },
> > -	{ .data =3D MIPI_CAL_CONFIG_DSID },
> > -};
> > -
> > -static const struct tegra_mipi_soc tegra114_mipi_soc =3D {
> > -	.has_clk_lane =3D false,
> > -	.pads =3D tegra114_mipi_pads,
> > -	.num_pads =3D ARRAY_SIZE(tegra114_mipi_pads),
> > -	.clock_enable_override =3D true,
> > -	.needs_vclamp_ref =3D true,
> > -	.pad_drive_down_ref =3D 0x2,
> > -	.pad_drive_up_ref =3D 0x0,
> > -	.pad_vclamp_level =3D 0x0,
> > -	.pad_vauxp_level =3D 0x0,
> > -	.hspdos =3D 0x0,
> > -	.hspuos =3D 0x4,
> > -	.termos =3D 0x5,
> > -	.hsclkpdos =3D 0x0,
> > -	.hsclkpuos =3D 0x4,
> > -};
> > -
> > -static const struct tegra_mipi_pad tegra124_mipi_pads[] =3D {
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIA, .clk =3D MIPI_CAL_CONFIG_CSIAB_CLK =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIB, .clk =3D MIPI_CAL_CONFIG_CSIAB_CLK =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIC, .clk =3D MIPI_CAL_CONFIG_CSICD_CLK =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_CSID, .clk =3D MIPI_CAL_CONFIG_CSICD_CLK =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIE, .clk =3D MIPI_CAL_CONFIG_CSIE_CLK  =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIA, .clk =3D MIPI_CAL_CONFIG_DSIA_CLK  =
},
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIB, .clk =3D MIPI_CAL_CONFIG_DSIB_CLK  =
},
> > -};
> > -
> > -static const struct tegra_mipi_soc tegra124_mipi_soc =3D {
> > -	.has_clk_lane =3D true,
> > -	.pads =3D tegra124_mipi_pads,
> > -	.num_pads =3D ARRAY_SIZE(tegra124_mipi_pads),
> > -	.clock_enable_override =3D true,
> > -	.needs_vclamp_ref =3D true,
> > -	.pad_drive_down_ref =3D 0x2,
> > -	.pad_drive_up_ref =3D 0x0,
> > -	.pad_vclamp_level =3D 0x0,
> > -	.pad_vauxp_level =3D 0x0,
> > -	.hspdos =3D 0x0,
> > -	.hspuos =3D 0x0,
> > -	.termos =3D 0x0,
> > -	.hsclkpdos =3D 0x1,
> > -	.hsclkpuos =3D 0x2,
> > -};
> > -
> > -static const struct tegra_mipi_soc tegra132_mipi_soc =3D {
> > -	.has_clk_lane =3D true,
> > -	.pads =3D tegra124_mipi_pads,
> > -	.num_pads =3D ARRAY_SIZE(tegra124_mipi_pads),
> > -	.clock_enable_override =3D false,
> > -	.needs_vclamp_ref =3D false,
> > -	.pad_drive_down_ref =3D 0x0,
> > -	.pad_drive_up_ref =3D 0x3,
> > -	.pad_vclamp_level =3D 0x0,
> > -	.pad_vauxp_level =3D 0x0,
> > -	.hspdos =3D 0x0,
> > -	.hspuos =3D 0x0,
> > -	.termos =3D 0x0,
> > -	.hsclkpdos =3D 0x3,
> > -	.hsclkpuos =3D 0x2,
> > -};
> > -
> > -static const struct tegra_mipi_pad tegra210_mipi_pads[] =3D {
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIA, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIB, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIC, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSID, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIE, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_CSIF, .clk =3D 0 },
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIA, .clk =3D MIPI_CAL_CONFIG_DSIA_CLK }=
,
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIB, .clk =3D MIPI_CAL_CONFIG_DSIB_CLK }=
,
> > -	{ .data =3D MIPI_CAL_CONFIG_DSIC, .clk =3D MIPI_CAL_CONFIG_DSIC_CLK }=
,
> > -	{ .data =3D MIPI_CAL_CONFIG_DSID, .clk =3D MIPI_CAL_CONFIG_DSID_CLK }=
,
> > -};
> > -
> > -static const struct tegra_mipi_soc tegra210_mipi_soc =3D {
> > -	.has_clk_lane =3D true,
> > -	.pads =3D tegra210_mipi_pads,
> > -	.num_pads =3D ARRAY_SIZE(tegra210_mipi_pads),
> > -	.clock_enable_override =3D true,
> > -	.needs_vclamp_ref =3D false,
> > -	.pad_drive_down_ref =3D 0x0,
> > -	.pad_drive_up_ref =3D 0x3,
> > -	.pad_vclamp_level =3D 0x1,
> > -	.pad_vauxp_level =3D 0x1,
> > -	.hspdos =3D 0x0,
> > -	.hspuos =3D 0x2,
> > -	.termos =3D 0x0,
> > -	.hsclkpdos =3D 0x0,
> > -	.hsclkpuos =3D 0x2,
> > -};
> > -
> > -static const struct of_device_id tegra_mipi_of_match[] =3D {
> > -	{ .compatible =3D "nvidia,tegra114-mipi", .data =3D &tegra114_mipi_so=
c },
> > -	{ .compatible =3D "nvidia,tegra124-mipi", .data =3D &tegra124_mipi_so=
c },
> > -	{ .compatible =3D "nvidia,tegra132-mipi", .data =3D &tegra132_mipi_so=
c },
> > -	{ .compatible =3D "nvidia,tegra210-mipi", .data =3D &tegra210_mipi_so=
c },
> > -	{ },
> > -};
> > -
> > -static int tegra_mipi_probe(struct platform_device *pdev)
> > +/**
> > + * devm_tegra_mipi_add_provider - Managed registration of a Tegra MIPI
> > + *				  calibration function provider.
> > + * @device: Handle to the device providing the MIPI calibration functi=
on.
> > + * @np: Device node pointer of the device providing the MIPI calibrati=
on
> > + *	function.
> > + * @ops: Operations supported by the MIPI calibration device.
> > + *
> > + * This registers a device that provides MIPI calibration functions.
> > + * For Tegra20 and Tegra30, this is the CSI block, while Tegra114 and
> > + * newer SoC generations have a dedicated hardware block for these
> > + * functions.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int devm_tegra_mipi_add_provider(struct device *device, struct
> > device_node *np, +				 const struct=20
tegra_mipi_ops *ops)
> >=20
> >  {
> >=20
> > -	const struct of_device_id *match;
> > -	struct tegra_mipi *mipi;
> > -
> > -	match =3D of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
> > -	if (!match)
> > -		return -ENODEV;
> > +	if (provider.np)
> > +		return -EBUSY;
> >=20
> > -	mipi =3D devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
> > -	if (!mipi)
> > -		return -ENOMEM;
> > +	provider.np =3D np;
> > +	provider.ops =3D ops;
> >=20
> > -	mipi->soc =3D match->data;
> > -	mipi->dev =3D &pdev->dev;
> > -
> > -	mipi->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
> > -	if (IS_ERR(mipi->regs))
> > -		return PTR_ERR(mipi->regs);
> > -
> > -	mutex_init(&mipi->lock);
> > -
> > -	mipi->clk =3D devm_clk_get_prepared(&pdev->dev, NULL);
> > -	if (IS_ERR(mipi->clk)) {
> > -		dev_err(&pdev->dev, "failed to get clock\n");
> > -		return PTR_ERR(mipi->clk);
> > -	}
> > -
> > -	platform_set_drvdata(pdev, mipi);
> > -
> > -	return 0;
> > +	return devm_add_action_or_reset(device, tegra_mipi_remove_provider,
> > NULL);>=20
> >  }
> >=20
> > -
> > -struct platform_driver tegra_mipi_driver =3D {
> > -	.driver =3D {
> > -		.name =3D "tegra-mipi",
> > -		.of_match_table =3D tegra_mipi_of_match,
> > -	},
> > -	.probe =3D tegra_mipi_probe,
> > -};
> > +EXPORT_SYMBOL(devm_tegra_mipi_add_provider);
> > diff --git a/drivers/gpu/host1x/tegra114-mipi.c
> > b/drivers/gpu/host1x/tegra114-mipi.c new file mode 100644
> > index 000000000000..c084a09784d1
> > --- /dev/null
> > +++ b/drivers/gpu/host1x/tegra114-mipi.c
> > @@ -0,0 +1,483 @@
> > +/*
> > + * Copyright (C) 2013 NVIDIA Corporation
> > + *
> > + * Permission to use, copy, modify, distribute, and sell this software
> > and its + * documentation for any purpose is hereby granted without fee=
,
> > provided that + * the above copyright notice appear in all copies and
> > that both that copyright + * notice and this permission notice appear i=
n
> > supporting documentation, and + * that the name of the copyright holder=
s
> > not be used in advertising or + * publicity pertaining to distribution =
of
> > the software without specific, + * written prior permission.  The
> > copyright holders make no representations + * about the suitability of
> > this software for any purpose.  It is provided "as + * is" without
> > express or implied warranty.
> > + *
> > + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS
> > SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
> > FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY
> > SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVE=
R
> > RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION O=
F
> > CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN
> > CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/host1x.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/tegra-mipi-cal.h>
> > +
> > +#include "dev.h"
> > +
> > +#define MIPI_CAL_CTRL			0x00
> > +#define MIPI_CAL_CTRL_NOISE_FILTER(x)	(((x) & 0xf) << 26)
> > +#define MIPI_CAL_CTRL_PRESCALE(x)	(((x) & 0x3) << 24)
> > +#define MIPI_CAL_CTRL_CLKEN_OVR		BIT(4)
> > +#define MIPI_CAL_CTRL_START		BIT(0)
> > +
> > +#define MIPI_CAL_AUTOCAL_CTRL		0x01
> > +
> > +#define MIPI_CAL_STATUS			0x02
> > +#define MIPI_CAL_STATUS_DONE		BIT(16)
> > +#define MIPI_CAL_STATUS_ACTIVE		BIT(0)
> > +
> > +#define MIPI_CAL_CONFIG_CSIA		0x05
> > +#define MIPI_CAL_CONFIG_CSIB		0x06
> > +#define MIPI_CAL_CONFIG_CSIC		0x07
> > +#define MIPI_CAL_CONFIG_CSID		0x08
> > +#define MIPI_CAL_CONFIG_CSIE		0x09
> > +#define MIPI_CAL_CONFIG_CSIF		0x0a
> > +#define MIPI_CAL_CONFIG_DSIA		0x0e
> > +#define MIPI_CAL_CONFIG_DSIB		0x0f
> > +#define MIPI_CAL_CONFIG_DSIC		0x10
> > +#define MIPI_CAL_CONFIG_DSID		0x11
> > +
> > +#define MIPI_CAL_CONFIG_DSIA_CLK	0x19
> > +#define MIPI_CAL_CONFIG_DSIB_CLK	0x1a
> > +#define MIPI_CAL_CONFIG_CSIAB_CLK	0x1b
> > +#define MIPI_CAL_CONFIG_DSIC_CLK	0x1c
> > +#define MIPI_CAL_CONFIG_CSICD_CLK	0x1c
> > +#define MIPI_CAL_CONFIG_DSID_CLK	0x1d
> > +#define MIPI_CAL_CONFIG_CSIE_CLK	0x1d
> > +
> > +/* for data and clock lanes */
> > +#define MIPI_CAL_CONFIG_SELECT		BIT(21)
> > +
> > +/* for data lanes */
> > +#define MIPI_CAL_CONFIG_HSPDOS(x)	(((x) & 0x1f) << 16)
> > +#define MIPI_CAL_CONFIG_HSPUOS(x)	(((x) & 0x1f) <<  8)
> > +#define MIPI_CAL_CONFIG_TERMOS(x)	(((x) & 0x1f) <<  0)
> > +
> > +/* for clock lanes */
> > +#define MIPI_CAL_CONFIG_HSCLKPDOSD(x)	(((x) & 0x1f) <<  8)
> > +#define MIPI_CAL_CONFIG_HSCLKPUOSD(x)	(((x) & 0x1f) <<  0)
> > +
> > +#define MIPI_CAL_BIAS_PAD_CFG0		0x16
> > +#define MIPI_CAL_BIAS_PAD_PDVCLAMP	BIT(1)
> > +#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF	BIT(0)
> > +
> > +#define MIPI_CAL_BIAS_PAD_CFG1		0x17
> > +#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
> > +#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
> > +
> > +#define MIPI_CAL_BIAS_PAD_CFG2		0x18
> > +#define MIPI_CAL_BIAS_PAD_VCLAMP(x)	(((x) & 0x7) << 16)
> > +#define MIPI_CAL_BIAS_PAD_VAUXP(x)	(((x) & 0x7) << 4)
> > +#define MIPI_CAL_BIAS_PAD_PDVREG	BIT(1)
> > +
> > +struct tegra_mipi_pad {
> > +	unsigned long data;
> > +	unsigned long clk;
> > +};
> > +
> > +struct tegra_mipi_soc {
> > +	bool has_clk_lane;
> > +	const struct tegra_mipi_pad *pads;
> > +	unsigned int num_pads;
> > +
> > +	bool clock_enable_override;
> > +	bool needs_vclamp_ref;
> > +
> > +	/* bias pad configuration settings */
> > +	u8 pad_drive_down_ref;
> > +	u8 pad_drive_up_ref;
> > +
> > +	u8 pad_vclamp_level;
> > +	u8 pad_vauxp_level;
> > +
> > +	/* calibration settings for data lanes */
> > +	u8 hspdos;
> > +	u8 hspuos;
> > +	u8 termos;
> > +
> > +	/* calibration settings for clock lanes */
> > +	u8 hsclkpdos;
> > +	u8 hsclkpuos;
> > +};
> > +
> > +struct tegra_mipi {
> > +	const struct tegra_mipi_soc *soc;
> > +	struct device *dev;
> > +	void __iomem *regs;
> > +	struct mutex lock; /* for register access */
> > +	struct clk *clk;
> > +
> > +	unsigned long usage_count;
> > +};
> > +
> > +static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
> > +				   unsigned long offset)
> > +{
> > +	return readl(mipi->regs + (offset << 2));
> > +}
> > +
> > +static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 valu=
e,
> > +				     unsigned long offset)
> > +{
> > +	writel(value, mipi->regs + (offset << 2));
> > +}
> > +
> > +static int tegra114_mipi_power_up(struct tegra_mipi *mipi)
> > +{
> > +	u32 value;
> > +	int err;
> > +
> > +	err =3D clk_enable(mipi->clk);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
> > +	value &=3D ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
> > +
> > +	if (mipi->soc->needs_vclamp_ref)
> > +		value |=3D MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
> > +
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
> > +
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > +	value &=3D ~MIPI_CAL_BIAS_PAD_PDVREG;
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > +
> > +	clk_disable(mipi->clk);
> > +
> > +	return 0;
> > +}
> > +
> > +static int tegra114_mipi_power_down(struct tegra_mipi *mipi)
> > +{
> > +	u32 value;
> > +	int err;
> > +
> > +	err =3D clk_enable(mipi->clk);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	/*
> > +	 * The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
> > +	 * supplies the DSI pads. This must be kept enabled until none of the
> > +	 * DSI lanes are used anymore.
> > +	 */
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > +	value |=3D MIPI_CAL_BIAS_PAD_PDVREG;
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > +
> > +	/*
> > +	 * MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
> > +	 * control a regulator that supplies current to the pre-driver logic.
> > +	 * Powering down this regulator causes DSI to fail, so it must remain
> > +	 * powered on until none of the DSI lanes are used anymore.
> > +	 */
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
> > +
> > +	if (mipi->soc->needs_vclamp_ref)
> > +		value &=3D ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
> > +
> > +	value |=3D MIPI_CAL_BIAS_PAD_PDVCLAMP;
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
> > +
> > +	return 0;
> > +}
> > +
> > +static int tegra114_mipi_enable(struct tegra_mipi_device *mipidev)
> > +{
> > +	struct tegra_mipi *mipi =3D platform_get_drvdata(mipidev->pdev);
> > +	int err =3D 0;
> > +
> > +	mutex_lock(&mipi->lock);
> > +
> > +	if (mipi->usage_count++ =3D=3D 0)
> > +		err =3D tegra114_mipi_power_up(mipi);
> > +
> > +	mutex_unlock(&mipi->lock);
> > +
> > +	return err;
> > +}
> > +
> > +static int tegra114_mipi_disable(struct tegra_mipi_device *mipidev)
> > +{
> > +	struct tegra_mipi *mipi =3D platform_get_drvdata(mipidev->pdev);
> > +	int err =3D 0;
> > +
> > +	mutex_lock(&mipi->lock);
> > +
> > +	if (--mipi->usage_count =3D=3D 0)
> > +		err =3D tegra114_mipi_power_down(mipi);
> > +
> > +	mutex_unlock(&mipi->lock);
> > +
> > +	return err;
> > +}
> > +
> > +static int tegra114_mipi_finish_calibration(struct tegra_mipi_device
> > *mipidev) +{
> > +	struct tegra_mipi *mipi =3D platform_get_drvdata(mipidev->pdev);
> > +	void __iomem *status_reg =3D mipi->regs + (MIPI_CAL_STATUS << 2);
> > +	u32 value;
> > +	int err;
> > +
> > +	err =3D readl_relaxed_poll_timeout(status_reg, value,
> > +					 !(value &=20
MIPI_CAL_STATUS_ACTIVE) &&
> > +					 (value & MIPI_CAL_STATUS_DONE),=20
50,
> > +					 250000);
> > +	mutex_unlock(&mipi->lock);
> > +	clk_disable(mipi->clk);
> > +
> > +	return err;
> > +}
> > +
> > +static int tegra114_mipi_start_calibration(struct tegra_mipi_device
> > *mipidev) +{
> > +	struct tegra_mipi *mipi =3D platform_get_drvdata(mipidev->pdev);
> > +	const struct tegra_mipi_soc *soc =3D mipi->soc;
> > +	unsigned int i;
> > +	u32 value;
> > +	int err;
> > +
> > +	err =3D clk_enable(mipi->clk);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	mutex_lock(&mipi->lock);
> > +
> > +	value =3D MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
> > +		MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
> > +
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
> > +	value &=3D ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
> > +	value &=3D ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
> > +	value |=3D MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
> > +	value |=3D MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
> > +
> > +	for (i =3D 0; i < soc->num_pads; i++) {
> > +		u32 clk =3D 0, data =3D 0;
> > +
> > +		if (mipidev->pads & BIT(i)) {
> > +			data =3D MIPI_CAL_CONFIG_SELECT |
> > +			       MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
> > +			       MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
> > +			       MIPI_CAL_CONFIG_TERMOS(soc->termos);
> > +			clk =3D MIPI_CAL_CONFIG_SELECT |
> > +			      MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
> > +			      MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
> > +		}
> > +
> > +		tegra_mipi_writel(mipi, data, soc->pads[i].data);
> > +
> > +		if (soc->has_clk_lane && soc->pads[i].clk !=3D 0)
> > +			tegra_mipi_writel(mipi, clk, soc->pads[i].clk);
> > +	}
> > +
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_CTRL);
> > +	value &=3D ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
> > +	value &=3D ~MIPI_CAL_CTRL_PRESCALE(0x3);
> > +	value |=3D MIPI_CAL_CTRL_NOISE_FILTER(0xa);
> > +	value |=3D MIPI_CAL_CTRL_PRESCALE(0x2);
> > +
> > +	if (!soc->clock_enable_override)
> > +		value &=3D ~MIPI_CAL_CTRL_CLKEN_OVR;
> > +	else
> > +		value |=3D MIPI_CAL_CTRL_CLKEN_OVR;
> > +
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_CTRL);
> > +
> > +	/* clear any pending status bits */
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_STATUS);
> > +
> > +	value =3D tegra_mipi_readl(mipi, MIPI_CAL_CTRL);
> > +	value |=3D MIPI_CAL_CTRL_START;
> > +	tegra_mipi_writel(mipi, value, MIPI_CAL_CTRL);
> > +
> > +	/*
> > +	 * Wait for min 72uS to let calibration logic finish calibration
> > +	 * sequence codes before waiting for pads idle state to apply the
> > +	 * results.
> > +	 */
> > +	usleep_range(75, 80);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct tegra_mipi_ops tegra114_mipi_ops =3D {
> > +	.enable =3D tegra114_mipi_enable,
> > +	.disable =3D tegra114_mipi_disable,
> > +	.start_calibration =3D tegra114_mipi_start_calibration,
> > +	.finish_calibration =3D tegra114_mipi_finish_calibration,
> > +};
> > +
> > +static const struct tegra_mipi_pad tegra114_mipi_pads[] =3D {
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIA },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIB },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIC },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSID },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIE },
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIA },
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIB },
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIC },
> > +	{ .data =3D MIPI_CAL_CONFIG_DSID },
> > +};
> > +
> > +static const struct tegra_mipi_soc tegra114_mipi_soc =3D {
> > +	.has_clk_lane =3D false,
> > +	.pads =3D tegra114_mipi_pads,
> > +	.num_pads =3D ARRAY_SIZE(tegra114_mipi_pads),
> > +	.clock_enable_override =3D true,
> > +	.needs_vclamp_ref =3D true,
> > +	.pad_drive_down_ref =3D 0x2,
> > +	.pad_drive_up_ref =3D 0x0,
> > +	.pad_vclamp_level =3D 0x0,
> > +	.pad_vauxp_level =3D 0x0,
> > +	.hspdos =3D 0x0,
> > +	.hspuos =3D 0x4,
> > +	.termos =3D 0x5,
> > +	.hsclkpdos =3D 0x0,
> > +	.hsclkpuos =3D 0x4,
> > +};
> > +
> > +static const struct tegra_mipi_pad tegra124_mipi_pads[] =3D {
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIA, .clk =3D MIPI_CAL_CONFIG_CSIAB_CLK =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIB, .clk =3D MIPI_CAL_CONFIG_CSIAB_CLK =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIC, .clk =3D MIPI_CAL_CONFIG_CSICD_CLK =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_CSID, .clk =3D MIPI_CAL_CONFIG_CSICD_CLK =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIE, .clk =3D MIPI_CAL_CONFIG_CSIE_CLK  =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIA, .clk =3D MIPI_CAL_CONFIG_DSIA_CLK  =
},
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIB, .clk =3D MIPI_CAL_CONFIG_DSIB_CLK  =
},
> > +};
> > +
> > +static const struct tegra_mipi_soc tegra124_mipi_soc =3D {
> > +	.has_clk_lane =3D true,
> > +	.pads =3D tegra124_mipi_pads,
> > +	.num_pads =3D ARRAY_SIZE(tegra124_mipi_pads),
> > +	.clock_enable_override =3D true,
> > +	.needs_vclamp_ref =3D true,
> > +	.pad_drive_down_ref =3D 0x2,
> > +	.pad_drive_up_ref =3D 0x0,
> > +	.pad_vclamp_level =3D 0x0,
> > +	.pad_vauxp_level =3D 0x0,
> > +	.hspdos =3D 0x0,
> > +	.hspuos =3D 0x0,
> > +	.termos =3D 0x0,
> > +	.hsclkpdos =3D 0x1,
> > +	.hsclkpuos =3D 0x2,
> > +};
> > +
> > +static const struct tegra_mipi_soc tegra132_mipi_soc =3D {
> > +	.has_clk_lane =3D true,
> > +	.pads =3D tegra124_mipi_pads,
> > +	.num_pads =3D ARRAY_SIZE(tegra124_mipi_pads),
> > +	.clock_enable_override =3D false,
> > +	.needs_vclamp_ref =3D false,
> > +	.pad_drive_down_ref =3D 0x0,
> > +	.pad_drive_up_ref =3D 0x3,
> > +	.pad_vclamp_level =3D 0x0,
> > +	.pad_vauxp_level =3D 0x0,
> > +	.hspdos =3D 0x0,
> > +	.hspuos =3D 0x0,
> > +	.termos =3D 0x0,
> > +	.hsclkpdos =3D 0x3,
> > +	.hsclkpuos =3D 0x2,
> > +};
> > +
> > +static const struct tegra_mipi_pad tegra210_mipi_pads[] =3D {
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIA, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIB, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIC, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSID, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIE, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_CSIF, .clk =3D 0 },
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIA, .clk =3D MIPI_CAL_CONFIG_DSIA_CLK }=
,
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIB, .clk =3D MIPI_CAL_CONFIG_DSIB_CLK }=
,
> > +	{ .data =3D MIPI_CAL_CONFIG_DSIC, .clk =3D MIPI_CAL_CONFIG_DSIC_CLK }=
,
> > +	{ .data =3D MIPI_CAL_CONFIG_DSID, .clk =3D MIPI_CAL_CONFIG_DSID_CLK }=
,
> > +};
> > +
> > +static const struct tegra_mipi_soc tegra210_mipi_soc =3D {
> > +	.has_clk_lane =3D true,
> > +	.pads =3D tegra210_mipi_pads,
> > +	.num_pads =3D ARRAY_SIZE(tegra210_mipi_pads),
> > +	.clock_enable_override =3D true,
> > +	.needs_vclamp_ref =3D false,
> > +	.pad_drive_down_ref =3D 0x0,
> > +	.pad_drive_up_ref =3D 0x3,
> > +	.pad_vclamp_level =3D 0x1,
> > +	.pad_vauxp_level =3D 0x1,
> > +	.hspdos =3D 0x0,
> > +	.hspuos =3D 0x2,
> > +	.termos =3D 0x0,
> > +	.hsclkpdos =3D 0x0,
> > +	.hsclkpuos =3D 0x2,
> > +};
> > +
> > +static const struct of_device_id tegra_mipi_of_match[] =3D {
> > +	{ .compatible =3D "nvidia,tegra114-mipi", .data =3D &tegra114_mipi_so=
c },
> > +	{ .compatible =3D "nvidia,tegra124-mipi", .data =3D &tegra124_mipi_so=
c },
> > +	{ .compatible =3D "nvidia,tegra132-mipi", .data =3D &tegra132_mipi_so=
c },
> > +	{ .compatible =3D "nvidia,tegra210-mipi", .data =3D &tegra210_mipi_so=
c },
> > +	{ },
> > +};
> > +
> > +static int tegra_mipi_probe(struct platform_device *pdev)
> > +{
> > +	const struct of_device_id *match;
> > +	struct tegra_mipi *mipi;
> > +
> > +	match =3D of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
> > +	if (!match)
> > +		return -ENODEV;
> > +
> > +	mipi =3D devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
> > +	if (!mipi)
> > +		return -ENOMEM;
> > +
> > +	mipi->soc =3D match->data;
> > +	mipi->dev =3D &pdev->dev;
> > +
> > +	mipi->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
> > +	if (IS_ERR(mipi->regs))
> > +		return PTR_ERR(mipi->regs);
> > +
> > +	mutex_init(&mipi->lock);
> > +
> > +	mipi->clk =3D devm_clk_get_prepared(&pdev->dev, NULL);
> > +	if (IS_ERR(mipi->clk)) {
> > +		dev_err(&pdev->dev, "failed to get clock\n");
> > +		return PTR_ERR(mipi->clk);
> > +	}
> > +
> > +	platform_set_drvdata(pdev, mipi);
> > +
> > +	return devm_tegra_mipi_add_provider(&pdev->dev, pdev->dev.of_node,
> > +					    &tegra114_mipi_ops);
> > +}
> > +
> > +struct platform_driver tegra_mipi_driver =3D {
> > +	.driver =3D {
> > +		.name =3D "tegra-mipi",
> > +		.of_match_table =3D tegra_mipi_of_match,
> > +	},
> > +	.probe =3D tegra_mipi_probe,
> > +};
> > diff --git a/drivers/staging/media/tegra-video/csi.c
> > b/drivers/staging/media/tegra-video/csi.c index
> > f858c05ce6c9..bcaea20c3025 100644
> > --- a/drivers/staging/media/tegra-video/csi.c
> > +++ b/drivers/staging/media/tegra-video/csi.c
> > @@ -12,6 +12,7 @@
> >=20
> >  #include <linux/of_graph.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/pm_runtime.h>
> >=20
> > +#include <linux/tegra-mipi-cal.h>
> >=20
> >  #include <media/v4l2-fwnode.h>
> >=20
> > diff --git a/include/linux/host1x.h b/include/linux/host1x.h
> > index 5e7a63143a4a..1f5f55917d1c 100644
> > --- a/include/linux/host1x.h
> > +++ b/include/linux/host1x.h
> > @@ -453,16 +453,6 @@ void host1x_client_unregister(struct host1x_client
> > *client);>=20
> >  int host1x_client_suspend(struct host1x_client *client);
> >  int host1x_client_resume(struct host1x_client *client);
> >=20
> > -struct tegra_mipi_device;
> > -
> > -struct tegra_mipi_device *tegra_mipi_request(struct device *device,
> > -					     struct device_node *np);
> > -void tegra_mipi_free(struct tegra_mipi_device *device);
> > -int tegra_mipi_enable(struct tegra_mipi_device *device);
> > -int tegra_mipi_disable(struct tegra_mipi_device *device);
> > -int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
> > -int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
> > -
> >=20
> >  /* host1x memory contexts */
> > =20
> >  struct host1x_memory_context {
> >=20
> > diff --git a/include/linux/tegra-mipi-cal.h
> > b/include/linux/tegra-mipi-cal.h new file mode 100644
> > index 000000000000..2a540b50f65d
> > --- /dev/null
> > +++ b/include/linux/tegra-mipi-cal.h
> > @@ -0,0 +1,57 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +
> > +#ifndef __TEGRA_MIPI_CAL_H_
> > +#define __TEGRA_MIPI_CAL_H_
> > +
> > +struct tegra_mipi_device {
> > +	const struct tegra_mipi_ops *ops;
> > +	struct platform_device *pdev;
> > +	unsigned long pads;
> > +};
> > +
> > +/**
> > + * Operations for Tegra MIPI calibration device
> > + */
> > +struct tegra_mipi_ops {
> > +	/**
> > +	 * @enable:
> > +	 *
> > +	 * Enable MIPI calibration device
> > +	 */
> > +	int (*enable)(struct tegra_mipi_device *device);
> > +
> > +	/**
> > +	 * @disable:
> > +	 *
> > +	 * Disable MIPI calibration device
> > +	 */
> > +	int (*disable)(struct tegra_mipi_device *device);
> > +
> > +	/**
> > +	 * @start_calibration:
> > +	 *
> > +	 * Start MIPI calibration
> > +	 */
> > +	int (*start_calibration)(struct tegra_mipi_device *device);
> > +
> > +	/**
> > +	 * @finish_calibration:
> > +	 *
> > +	 * Finish MIPI calibration
> > +	 */
> > +	int (*finish_calibration)(struct tegra_mipi_device *device);
> > +};
> > +
> > +int devm_tegra_mipi_add_provider(struct device *device, struct
> > device_node *np, +				 const struct=20
tegra_mipi_ops *ops);
> > +
> > +struct tegra_mipi_device *tegra_mipi_request(struct device *device,
> > +					     struct device_node *np);
> > +void tegra_mipi_free(struct tegra_mipi_device *device);
> > +
> > +int tegra_mipi_enable(struct tegra_mipi_device *device);
> > +int tegra_mipi_disable(struct tegra_mipi_device *device);
> > +int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
> > +int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
> > +
> > +#endif /* __TEGRA_MIPI_CAL_H_ */