From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95E6B6D1B for ; Tue, 17 Aug 2021 01:30:05 +0000 (UTC) Received: by mail-lj1-f175.google.com with SMTP id y6so13443290lje.2 for ; Mon, 16 Aug 2021 18:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rIIbTdgH+pfcdvXJM3PhuR8TNGLF8k42ZN+r4fmcuaM=; b=TEvCrByVx93JYtGn78GAWLt1bT9YxkCjzq93w+IwY4bwmNpr8DkqPH5ayGAOGtfdBV fa+PhOX8+Qv36UXTnCsov+5UtufMjjh1IQTsr3L1FNx5Z/9b8e5LHDnkh8zZiizJ1WxP 72DYqArQVIy6I7VydaLBJNQPAL6zLFmYydaw4GQya90iFoiojJno0XaF7wd33gN6EgjY ToIrEapwVxW6bFJckYH1XQchGwszb7+T5HWZyUwfD27L/z4VoG6qChBzAuhbyJOqWUVj x5NU/f826zMfHMQZEfhLHMO5sTHgiqC+FBkhDgX0rwRgKwkKkbgbO3jXereixuNrMAkT Mieg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rIIbTdgH+pfcdvXJM3PhuR8TNGLF8k42ZN+r4fmcuaM=; b=A2g8JSJThAdNdkCWnsutJRv2UN7wWo0dCmeNSu9DF8x4tOZ+c+xz2tbe/V1UXLSiQL ZtwDKENK32889ZG3NBx2E+nv7g/sGjiwUDWtskLC50R+PoP1aXQDHrL+8cHZqL2XL74f xNdBWVA2WoWn0mx2AWmAqHnLoDikAr6s/UfDfjWNrmMiYIec7dC97tx4okU5122zner0 jjHr0hzwssHYZ4soWEhckcOtKEEWSV/O7HTtLoAycqewiVDZQMPtlJ0nM0no6VPMQjvQ qr3SqPLy2pPTcZKVIDsDIl3XVkYtBSFkbxzcXqDcRG4nA9uIuqnQxEAWKbeAlEZe35cI Y0Gw== X-Gm-Message-State: AOAM533xE7evmG1Isfq91BefpJ6dc8uP8thN5wIlWtXNcn9mMCiJ9EBJ uwy9YkpgwqnJFZMURIcDZC7M1HJ4iLQ= X-Google-Smtp-Source: ABdhPJzx2Bm7jx/Cai6FZzL4KCpIVLSHzlBwFdZrnxkJdr2Ws/VmVzSpQZLFmKjJZCDYkbxY7twb+w== X-Received: by 2002:a2e:9c16:: with SMTP id s22mr863254lji.255.1629163803825; Mon, 16 Aug 2021 18:30:03 -0700 (PDT) Received: from localhost.localdomain (46-138-85-91.dynamic.spd-mgts.ru. [46.138.85.91]) by smtp.gmail.com with ESMTPSA id g30sm46607lfj.298.2021.08.16.18.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Aug 2021 18:30:03 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , Viresh Kumar , Stephen Boyd , Peter De Schrijver , Mikko Perttunen , Peter Chen , Mark Brown , Lee Jones , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Nishanth Menon , Vignesh Raghavendra , Richard Weinberger , Miquel Raynal , Lucas Stach , Stefan Agner , Adrian Hunter , Mauro Carvalho Chehab , Rob Herring , Michael Turquette Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-spi@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mtd@lists.infradead.org, linux-mmc@vger.kernel.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v8 02/34] soc/tegra: pmc: Disable PMC state syncing Date: Tue, 17 Aug 2021 04:27:22 +0300 Message-Id: <20210817012754.8710-3-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210817012754.8710-1-digetx@gmail.com> References: <20210817012754.8710-1-digetx@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Disable PMC state syncing in order to ensure that we won't break older kernels once device-trees will be updated with the addition of the power domains. Previously this was unnecessary because the plan was to make clk device that will attach to the domain for each clock, but the plan changed and now we're going make a better GENPD implementation that will require to update each device driver with the runtime PM and OPP support before we could safely enable the state syncing. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 50091c4ec948..fb8faf7b226a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -360,6 +360,7 @@ struct tegra_pmc_soc { unsigned int num_pmc_clks; bool has_blink_output; bool has_usb_sleepwalk; + bool supports_core_domain; }; /** @@ -3041,6 +3042,7 @@ static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, } static const struct tegra_pmc_soc tegra20_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra20_powergates), .powergates = tegra20_powergates, .num_cpu_powergates = 0, @@ -3101,6 +3103,7 @@ static const char * const tegra30_reset_sources[] = { }; static const struct tegra_pmc_soc tegra30_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra30_powergates), .powergates = tegra30_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), @@ -3157,6 +3160,7 @@ static const u8 tegra114_cpu_powergates[] = { }; static const struct tegra_pmc_soc tegra114_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra114_powergates), .powergates = tegra114_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), @@ -3273,6 +3277,7 @@ static const struct pinctrl_pin_desc tegra124_pin_descs[] = { }; static const struct tegra_pmc_soc tegra124_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra124_powergates), .powergates = tegra124_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), @@ -3398,6 +3403,7 @@ static const struct tegra_wake_event tegra210_wake_events[] = { }; static const struct tegra_pmc_soc tegra210_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), @@ -3555,6 +3561,7 @@ static const struct tegra_wake_event tegra186_wake_events[] = { }; static const struct tegra_pmc_soc tegra186_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3689,6 +3696,7 @@ static const struct tegra_wake_event tegra194_wake_events[] = { }; static const struct tegra_pmc_soc tegra194_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3757,6 +3765,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_pmc_soc tegra234_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3803,6 +3812,14 @@ static void tegra_pmc_sync_state(struct device *dev) { int err; + /* + * Newer device-trees have power domains, but we need to prepare all + * device drivers with runtime PM and OPP support first, otherwise + * state syncing is unsafe. + */ + if (!pmc->soc->supports_core_domain) + return; + /* * Older device-trees don't have core PD, and thus, there are * no dependencies that will block the state syncing. We shouldn't -- 2.32.0