From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D81612FC015 for ; Wed, 8 Oct 2025 07:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759908718; cv=none; b=WfRc4EHVZl/QMFJyVrh7KcUl0WuynYSnXPGEZLHS2GFGaW2/wd9yDK89WzSVmXRPDKGObXbf2neImSfEtNTcARZAT+nkvncGDSjn3P3oZn1uTEzJw1xADQ10xgTPquvlouzvaOpFapbLc/ANGQC1u7j5Ghbp1VKSXmXXFRsxfUU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759908718; c=relaxed/simple; bh=iiHfTmqTpfmKU38rkhczSgtC8/xhyV+ts8JmJCC3QqE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uaz9adkJwcXQJfz9mIrdU5lN7xQxpRzR2xRfRSwDpj1UZyp4vp2cTQUJRgbPz50vQ0N9DsKpCgg+lByTTRZj/zwF49BHI2Y/oLaZAM+dcYOfqrBCgYSNDno7gahXlQfq959TR34wz50mFtiPZvf68AiGQIj3UJONDcWUPwO7Tkc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KRBI9nUA; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KRBI9nUA" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-579d7104c37so8926885e87.3 for ; Wed, 08 Oct 2025 00:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759908712; x=1760513512; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ihAxrvGeeqbDGS2s2nWoaKnfeN+9tvG68aYZNvqbzNU=; b=KRBI9nUA1KPGFp5ZtweeMOUbvvu7uK2/X3PkcONyYOiw5GpDVk04b0k4D61e9dvM3g Ak9sYYiMhT2+GczlWDezh34tC7a4xa8zE3O+W+2nlvlej1z+EAEx8PE0Jbo+slLcQQ59 S7L8inJvUHV8PkI5NAmThH82QeTeOmZMo5rAJtHKcZRUFnXAAvPU0btwisWs91FobBNn DfebdojoBo4Q/5Z+tdLaC7S4Gif3+4el089PwTBG0mHutMhXgmk8dByJxq2zXZXBqDgX dZ2So/C7z0amv+QAbS4l4gI4Z2sh48m/ULWgCQV8/RaPVnHu+rDFx9KzWUIpD+myAW01 plwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759908712; x=1760513512; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ihAxrvGeeqbDGS2s2nWoaKnfeN+9tvG68aYZNvqbzNU=; b=SwFbyaEgVsnHoveP4U29sign9xwVOvodkrTEewNDJDu6jd3WrdDJNGgVG7uc5e64jr SQXsozCAjGiG0zohG4CQzJNrFrYbfWHZuXPgPrMKohd4MdhCJATgeAdLzcUoS+qTfNPk eDIeu1UV1FkBGSn+N/0MR5O+uSGFnqn7N8m+Ht0tECxYlGCZNvpf7+XuAU+UBXbNGiwQ k8qJXu+43odjZkFhdQfAAlb6FVaG5vznCXfe7Sk1X4DRn8sBwRtwBoaPu5KgaxHnvgkB LiiyrwBYPjla90I4eqGmdjT35YIuyvaSEbM3sABhFh6MY26mfZmmcmSdpAg9MO7ovZxU o54w== X-Forwarded-Encrypted: i=1; AJvYcCVl/s7D6nCQVnS8StKvgWYqu4jaGXv+3MBNGL97H0lIQOtjN0/Iq54D7vxQcgXKeJshQ3SDh1UTNfBpUZBU@lists.linux.dev X-Gm-Message-State: AOJu0YwJUE+dYL4vTwiXg+kBTC1kJaS8sukPYm02DRRrYizmSROgRyOH ipgUwoDf9fhJbsNecc7e1pu4b8j3Prx2z3rMqkIn4Rb/3eRKbxj06FE8 X-Gm-Gg: ASbGncs5F3fJGEhO1dM+jEgOgnb6ai6wGYveANE4rXVmvj6bUe9OTWip7UlKc/cUbEW syINR0Kjh1p6Rov/yZgENhAtERr7OlQlfOonxSVXOSNAptacIUr94+zismecB9cnsLIk7gu4Bun jBfqVw9nG/1Nx8AHYqDJJxk0o+i5BQcYVmoe0SAwBwZNzJvsvTE9ff1/+PbP/74DDK6JfnsDXeC ktS3LaRUYNUfB50TsDPndnN/GQjz7LfDLoXUM3vnPHOpxN0FHD6E6Cnje/osOR3lkLCT0Y+wHWn aYvaFEI5qIQsrqwrmb+eypgwrGKvrotLlFwqezYr02j2VGjFRPOqJA7SbhYDH1xoj5KkEkpj0l9 AalcntJ+vt651/ogdDaotntaQ5LzBWvsa15W0lA== X-Google-Smtp-Source: AGHT+IHLfcoP/CF+9Jgh7CWd/VCkL/1kWm6zkDko2dBTHVx0gAsAz99mKegLte9a4Cyd6nve7U60ng== X-Received: by 2002:a05:6512:3d0d:b0:57f:492:3263 with SMTP id 2adb3069b0e04-5906d87b37cmr670856e87.1.1759908712166; Wed, 08 Oct 2025 00:31:52 -0700 (PDT) Received: from xeon.. ([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58b0118d22bsm6911016e87.85.2025.10.08.00.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 00:31:51 -0700 (PDT) From: Svyatoslav Ryhel To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , Linus Walleij , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= , Dmitry Osipenko , Charan Pedumuru , Diogo Ivo , Aaron Kling , Arnd Bergmann Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v4 23/24] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Date: Wed, 8 Oct 2025 10:30:45 +0300 Message-ID: <20251008073046.23231-24-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251008073046.23231-1-clamor95@gmail.com> References: <20251008073046.23231-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add CSI node to Tegra20 and Tegra30 device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 19 ++++++++++++++++++- arch/arm/boot/dts/nvidia/tegra30.dtsi | 24 ++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index 6ae07b316c8a..5cdbf1246cf8 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ mpe@54040000 { vi@54080000 { compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; + reg = <0x54080000 0x00000800>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; @@ -72,6 +72,23 @@ vi@54080000 { power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra20-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index 20b3248d4d2f..be752a245a55 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -150,8 +150,8 @@ mpe@54040000 { }; vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; + compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi"; + reg = <0x54080000 0x00000800>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; @@ -162,6 +162,26 @@ vi@54080000 { iommus = <&mc TEGRA_SWGROUP_VI>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra30-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names = "csi", "csia-pad", "csib-pad"; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { -- 2.48.1