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Date: Fri, 30 Jan 2026 19:44:42 +0530 Message-ID: <20260130141442.139640-1-harshdaniel66356@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Harsh Daniel Add device tree bindings for the compatible strings used in the staging/most/dim2 driver to resolve checkpatch warnings: - fsl,imx6q-mlb150 - renesas,mlp and renesas,rcar-gen3-mlp - xlnx,axi4-os62420_3pin-1.00.a and xlnx,axi4-os62420_6pin-1.00.a These bindings document the MediaLB DIM2 module found in Freescale i.MX6Q, Renesas R-Car, and Xilinx FPGA platforms. Signed-off-by: Harsh Daniel --- .../bindings/media/fsl,imx6q-mlb150.yaml | 73 +++++++++++++++++++ .../bindings/media/renesas,mlp.yaml | 65 +++++++++++++++++ .../media/xilinx/xlnx,axi4-os62420.yaml | 60 +++++++++++++++ MAINTAINERS | 3 + 4 files changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/fsl,imx6q-mlb150.yaml create mode 100644 Documentation/devicetree/bindings/media/renesas,mlp.yaml create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,axi4-os62420.yaml diff --git a/Documentation/devicetree/bindings/media/fsl,imx6q-mlb150.yaml b/Documentation/devicetree/bindings/media/fsl,imx6q-mlb150.yaml new file mode 100644 index 000000000000..2d0aab3d2286 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx6q-mlb150.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6q-mlb150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6Q MediaLB DIM2 Controller + +maintainers: + - Andrey Shvetsov + +description: | + MediaLB DIM2 module found in Freescale i.MX6Q SoCs. + +properties: + compatible: + const: fsl,imx6q-mlb150 + + reg: + maxItems: 1 + + interrupts: + items: + - description: MediaLB Interrupt + - description: AHB0 Interrupt + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: mlb + - const: pll8_mlb + + microchip,clock-speed: + $ref: /schemas/types.yaml#/definitions/string + enum: + - 256fs + - 512fs + - 1024fs + - 2048fs + - 3072fs + - 4096fs + - 6144fs + - 8192fs + description: DIM2 clock speed. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - microchip,clock-speed + +additionalProperties: false + +examples: + - | + #include + + mlb@218e000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0218e000 0x4000>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 1>, <&clks 2>; + clock-names = "mlb", "pll8_mlb"; + microchip,clock-speed = "2048fs"; + }; diff --git a/Documentation/devicetree/bindings/media/renesas,mlp.yaml b/Documentation/devicetree/bindings/media/renesas,mlp.yaml new file mode 100644 index 000000000000..dfd9045d87f2 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,mlp.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,mlp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MediaLB DIM2 Controller + +maintainers: + - Andrey Shvetsov + +description: | + MediaLB DIM2 module found in Renesas R-Car Gen2 and Gen3 SoCs. + +properties: + compatible: + enum: + - renesas,mlp + - renesas,rcar-gen3-mlp + + reg: + maxItems: 1 + + interrupts: + items: + - description: MediaLB Interrupt + - description: AHB0 Interrupt + + clocks: + maxItems: 1 + + microchip,clock-speed: + $ref: /schemas/types.yaml#/definitions/string + enum: + - 256fs + - 512fs + - 1024fs + - 2048fs + - 3072fs + - 4096fs + - 6144fs + - 8192fs + description: DIM2 clock speed. + +required: + - compatible + - reg + - interrupts + - clocks + - microchip,clock-speed + +additionalProperties: false + +examples: + - | + #include + + mlp@e6050000 { + compatible = "renesas,mlp"; + reg = <0xe6050000 0x1000>; + interrupts = , + ; + clocks = <&cpg 123>; + microchip,clock-speed = "2048fs"; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,axi4-os62420.yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,axi4-os62420.yaml new file mode 100644 index 000000000000..dd4ac5c6ccf3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,axi4-os62420.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/xilinx/xlnx,axi4-os62420.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx MediaLB DIM2 Controller + +maintainers: + - Andrey Shvetsov + +description: | + MediaLB DIM2 module found in Xilinx FPGAs. + +properties: + compatible: + enum: + - xlnx,axi4-os62420_3pin-1.00.a + - xlnx,axi4-os62420_6pin-1.00.a + + reg: + maxItems: 1 + + interrupts: + items: + - description: MediaLB Interrupt + - description: AHB0 Interrupt + + microchip,clock-speed: + $ref: /schemas/types.yaml#/definitions/string + enum: + - 256fs + - 512fs + - 1024fs + - 2048fs + - 3072fs + - 4096fs + - 6144fs + - 8192fs + description: DIM2 clock speed. + +required: + - compatible + - reg + - interrupts + - microchip,clock-speed + +additionalProperties: false + +examples: + - | + #include + + dim2@e6050000 { + compatible = "xlnx,axi4-os62420_3pin-1.00.a"; + reg = <0x43c00000 0x10000>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>, + <0 145 IRQ_TYPE_LEVEL_HIGH>; + microchip,clock-speed = "2048fs"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..914693621b3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17650,6 +17650,9 @@ M: Christian Gromm S: Maintained F: Documentation/ABI/testing/configfs-most F: Documentation/ABI/testing/sysfs-bus-most +F: Documentation/devicetree/bindings/media/fsl,imx6q-mlb150.yaml +F: Documentation/devicetree/bindings/media/renesas,mlp.yaml +F: Documentation/devicetree/bindings/media/xilinx/xlnx,axi4-os62420.yaml F: drivers/most/ F: drivers/staging/most/ F: include/linux/most.h -- 2.52.0