[PATCH] Changes udelay to usleep_range in rtl8723bs files and resolves checkpatch warnings.

[PATCH] Changes udelay to usleep_range in rtl8723bs files and resolves checkpatch warnings.

[Lukas Kraft]

Signed-off-by: Lukas Kraft <rebootrequired42@gmail.com>
---
 drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c  | 36 +++++++++----------
 .../rtl8723bs/hal/odm_RegConfig8723B.c        | 28 +++++++--------
 .../staging/rtl8723bs/hal/rtl8723b_hal_init.c |  2 +-
 .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   |  8 ++---
 .../staging/rtl8723bs/hal/rtl8723b_rf6052.c   | 14 ++++----
 5 files changed, 39 insertions(+), 49 deletions(-)

diff --git a/drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c b/drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c
index 86404b5e6c52..f66057a39ff6 100644
--- a/drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c
+++ b/drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c
@@ -4,26 +4,22 @@
  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  *
  ******************************************************************************/
-/*++
-Copyright (c) Realtek Semiconductor Corp. All rights reserved.
-
-Module Name:
-	HalPwrSeqCmd.c
-
-Abstract:
-	Implement HW Power sequence configuration CMD handling routine for Realtek devices.
-
-Major Change History:
-	When       Who               What
-	---------- ---------------   -------------------------------
-	2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
-	2011-07-07 Roger            Create.
-
---*/
+/**
+ * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
+ *
+ * Module Name: HalPwrSeqCmd.c
+ *
+ * Implement HW Power sequence configuration CMD handling routine for Realtek devices.
+ *
+ * Major Change History:
+ *  When       Who               What
+ *  ---------- ---------------   -------------------------------
+ *  2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
+ *  2011-07-07 Roger            Create.
+ */
 #include <drv_types.h>
 #include <HalPwrSeqCmd.h>
 
-
 /*  */
 /*  Description: */
 /*  This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
@@ -113,7 +109,7 @@ u8 HalPwrSeqCmdParsing(
 					)
 						bPollingBit = true;
 					else
-						udelay(10);
+						usleep_range(10, 20);
 
 					if (pollingCount++ > maxPollingCnt)
 						return false;
@@ -124,9 +120,9 @@ u8 HalPwrSeqCmdParsing(
 
 			case PWR_CMD_DELAY:
 				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
-					udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
+					usleep_range(GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_OFFSET(PwrCfgCmd) + 10);
 				else
-					udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
+					usleep_range(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000, GET_PWR_CFG_OFFSET(PwrCfgCmd) 1000 + 10);
 				break;
 
 			case PWR_CMD_END:
diff --git a/drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c b/drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c
index 1df42069bd5c..734f58dc420d 100644
--- a/drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c
+++ b/drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c
@@ -20,7 +20,7 @@ void odm_ConfigRFReg_8723B(
 	else {
 		PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
 		/*  Add 1us delay between BB/RF register setting. */
-		udelay(1);
+		usleep_range(1, 2);
 
 		/* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
 		if (Addr == 0xb6) {
@@ -31,12 +31,12 @@ void odm_ConfigRFReg_8723B(
 				pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
 			);
 
-			udelay(1);
+			usleep_range(1, 2);
 
 			while ((getvalue>>8) != (Data>>8)) {
 				count++;
 				PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
-				udelay(1);
+				usleep_range(1, 2);
 				getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
 				if (count > 5)
 					break;
@@ -51,7 +51,7 @@ void odm_ConfigRFReg_8723B(
 				pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
 			);
 
-			udelay(1);
+			usleep_range(1, 2);
 
 			while (getvalue != Data) {
 				count++;
@@ -62,7 +62,7 @@ void odm_ConfigRFReg_8723B(
 					bRFRegOffsetMask,
 					Data
 				);
-				udelay(1);
+				usleep_range(1, 2);
 				/* Do LCK againg */
 				PHY_SetRFReg(
 					pDM_Odm->Adapter,
@@ -71,7 +71,7 @@ void odm_ConfigRFReg_8723B(
 					bRFRegOffsetMask,
 					0x0fc07
 				);
-				udelay(1);
+				usleep_range(1, 2);
 				getvalue = PHY_QueryRFReg(
 					pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
 				);
@@ -112,7 +112,7 @@ void odm_ConfigBB_AGC_8723B(
 {
 	PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
 	/*  Add 1us delay between BB/RF register setting. */
-	udelay(1);
+	usleep_range(1, 2);
 }
 
 void odm_ConfigBB_PHY_REG_PG_8723B(
@@ -125,9 +125,8 @@ void odm_ConfigBB_PHY_REG_PG_8723B(
 {
 	if (Addr == 0xfe || Addr == 0xffe)
 		msleep(50);
-	else {
+	else
 		PHY_StoreTxPowerByRate(pDM_Odm->Adapter, RfPath, Addr, Bitmask, Data);
-	}
 }
 
 void odm_ConfigBB_PHY_8723B(
@@ -144,17 +143,16 @@ void odm_ConfigBB_PHY_8723B(
 	else if (Addr == 0xfc)
 		mdelay(1);
 	else if (Addr == 0xfb)
-		udelay(50);
+		usleep_range(50, 60);
 	else if (Addr == 0xfa)
-		udelay(5);
+		usleep_range(5, 10);
 	else if (Addr == 0xf9)
-		udelay(1);
-	else {
+		usleep_range(1, 2);
+	else
 		PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
-	}
 
 	/*  Add 1us delay between BB/RF register setting. */
-	udelay(1);
+	usleep_range(1, 2);
 }
 
 void odm_ConfigBB_TXPWR_LMT_8723B(
diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c
index 8d259820f103..1c013c78a2d1 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c
@@ -273,7 +273,7 @@ void rtl8723b_FirmwareSelfReset(struct adapter *padapter)
 			Delay--;
 			if (Delay == 0)
 				break;
-			udelay(50);
+			usleep_range(50, 60);
 			val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
 		}
 
diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
index 6d5e531505f9..6416093037ec 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
@@ -122,11 +122,7 @@ static u32 phy_RFSerialRead_8723B(
 	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 
-	udelay(10);
-
-	for (i = 0; i < 2; i++)
-		udelay(MAX_STALL_TIME);
-	udelay(10);
+	usleep_range((MAX_STALL_TIME * 2) + 10, MAX_STALL_TIME * 3);
 
 	if (eRFPath == RF_PATH_A)
 		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
@@ -391,7 +387,7 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
 
 	rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
 
-	msleep(1);
+	usleep_range(1000, 1100);
 
 	PHY_SetRFReg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
 
diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c b/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c
index ffb35e1ace62..92aca9116824 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c
@@ -24,7 +24,7 @@
  * 11/05/2008	MHC		Add API for tw power setting.
  *
  *
-******************************************************************************/
+ *****************************************************************************/
 
 #include <rtl8723b_hal.h>
 
@@ -40,7 +40,7 @@
 /*  2008/11/20 MH For Debug only, RF */
 /*------------------------Define local variable------------------------------*/
 
-/*-----------------------------------------------------------------------------
+/**
  * Function:    PHY_RF6052SetBandwidth()
  *
  * Overview:    This function is called by SetBWModeCallback8190Pci() only
@@ -53,7 +53,7 @@
  * Return:      NONE
  *
  * Note:		For RF type 0222D
- *---------------------------------------------------------------------------*/
+ */
 void PHY_RF6052SetBandwidth8723B(
 	struct adapter *Adapter, enum channel_width Bandwidth
 ) /* 20M or 40M */
@@ -106,18 +106,18 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
 
 		/*----Set RF_ENV enable----*/
 		PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
-		udelay(1);/* PlatformStallExecution(1); */
+		usleep_range(1, 2);/* PlatformStallExecution(1); */
 
 		/*----Set RF_ENV output high----*/
 		PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
-		udelay(1);/* PlatformStallExecution(1); */
+		usleep_range(1, 2);/* PlatformStallExecution(1); */
 
 		/* Set bit number of Address and Data for RF register */
 		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);	/*  Set 1 to 4 bits for 8255 */
-		udelay(1);/* PlatformStallExecution(1); */
+		usleep_range(1, 2);/* PlatformStallExecution(1); */
 
 		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	/*  Set 0 to 12  bits for 8255 */
-		udelay(1);/* PlatformStallExecution(1); */
+		usleep_range(1, 2);/* PlatformStallExecution(1); */
 
 		/*----Initialize RF fom connfiguration file----*/
 		switch (eRFPath) {
-- 
2.51.0

Re: [PATCH] Changes udelay to usleep_range in rtl8723bs files and resolves checkpatch warnings.

[Greg KH]

On Wed, Mar 11, 2026 at 11:33:44PM +0100, Lukas Kraft wrote:
> Signed-off-by: Lukas Kraft <rebootrequired42@gmail.com>
> ---
>  drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c  | 36 +++++++++----------
>  .../rtl8723bs/hal/odm_RegConfig8723B.c        | 28 +++++++--------
>  .../staging/rtl8723bs/hal/rtl8723b_hal_init.c |  2 +-
>  .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   |  8 ++---
>  .../staging/rtl8723bs/hal/rtl8723b_rf6052.c   | 14 ++++----
>  5 files changed, 39 insertions(+), 49 deletions(-)

Hi,

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