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[150.9.40.201]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-82cf9ca14b3sm23344993b3a.54.2026.04.08.03.32.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 03:32:12 -0700 (PDT) From: osjin83@gmail.com To: Greg Kroah-Hartman Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, osjin83@gmail.com Subject: [PATCH 1/3] staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c Date: Wed, 8 Apr 2026 19:32:06 +0900 Message-ID: <20260408103208.7682-2-osjin83@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260408103208.7682-1-osjin83@gmail.com> References: <20260408103208.7682-1-osjin83@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: tas0dev Fix various spacing issues reported by checkpatch.pl to improve code readability and conform to the Linux kernel coding style. Specifically, this patch: - Adds missing spaces around binary operators (| , >> , << , + , &). - Corrects the spacing in bitwise expressions within function calls. - Ensures consistent use of whitespace in arithmetic operations. These changes are purely cosmetic and do not alter the functional behavior of the driver. Signed-off-by: tas0dev --- .../staging/rtl8723bs/hal/rtl8723b_phycfg.c | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c index 7fac1c2ba8e0..cfa00775341b 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c @@ -19,7 +19,7 @@ static u32 phy_CalculateBitShift(u32 BitMask) u32 i; for (i = 0; i <= 31; i++) { - if (((BitMask>>i) & 0x1) == 1) + if (((BitMask >> i) & 0x1) == 1) break; } return i; @@ -109,18 +109,18 @@ static u32 phy_RFSerialRead_8723B( NewOffset = Offset; if (eRFPath == RF_PATH_A) { - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } else { - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord); - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); udelay(10); @@ -129,16 +129,16 @@ static u32 phy_RFSerialRead_8723B( udelay(10); if (eRFPath == RF_PATH_A) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); + RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8); else if (eRFPath == RF_PATH_B) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); + RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8); if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData); + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData); } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData); + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData); } return retValue; @@ -203,7 +203,7 @@ static void phy_RFSerialWrite_8723B( /* */ /* Put write addr in [5:0] and write data in [31:16] */ /* */ - DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */ + DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */ /* */ /* Write Operation */ /* */ @@ -266,7 +266,7 @@ void PHY_SetRFReg_8723B( if (BitMask != bRFRegOffsetMask) { Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr); BitShift = phy_CalculateBitShift(BitMask); - Data = ((Original_Value & (~BitMask)) | (Data<nCur40MhzPrimeSC>>1)); + PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); break; default: break; -- 2.53.0