* [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c
@ 2026-04-09 3:48 Pranav Desai
2026-04-09 3:48 ` [PATCH 2/2] staging: rtl8723bs: fix comment style " Pranav Desai
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Pranav Desai @ 2026-04-09 3:48 UTC (permalink / raw)
To: gregkh; +Cc: linux-staging, straube.linux, b9788213, bera, Pranav Desai
Remove commented-out code blocks
Signed-off-by: Pranav Desai <contact.pranavdesai@gmail.com>
---
.../staging/rtl8723bs/hal/HalPhyRf_8723B.c | 85 -------------------
1 file changed, 85 deletions(-)
diff --git a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
index 8f6849f2277e..63c848ebd661 100644
--- a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
+++ b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
@@ -361,9 +361,6 @@ static u8 phy_PathA_IQK_8723B(
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
- /* disable path B PA in TXIQK mode */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
/* 1 Tx IQK */
/* IQK setting */
@@ -374,7 +371,6 @@ static u8 phy_PathA_IQK_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
@@ -401,8 +397,6 @@ static u8 phy_PathA_IQK_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -462,7 +456,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
/* LNA2 off, PA on for Dcut */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
/* IQK setting */
@@ -475,7 +468,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
@@ -502,8 +494,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -546,7 +536,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
/* LAN2 on, PA off for Dcut */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
/* PA, PAD setting */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
@@ -563,7 +552,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
@@ -589,8 +577,6 @@ static u8 phy_PathA_RxIQK8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -642,12 +628,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
/* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* in TXIQK mode */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
- /* enable path B PA in TXIQK mode */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
@@ -663,7 +643,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
@@ -677,7 +656,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
/* switch to path B */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
/* GNT_BT = 0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
@@ -686,8 +664,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -757,7 +733,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
@@ -771,7 +746,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* switch to path B */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
/* GNT_BT = 0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
@@ -781,8 +755,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -825,16 +797,11 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
/* open PA S1 & close SMIXER */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
- /* PA, PAD setting */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
-
/* IQK setting */
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
@@ -845,7 +812,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
@@ -858,7 +824,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* switch to path B */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
/* GNT_BT = 0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
@@ -867,8 +832,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
- /* delay x ms */
- /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* restore Ant Path */
@@ -883,12 +846,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
- /* PA/PAD controlled by 0x0 */
- /* leave IQK mode */
-/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
-
-
/* Allen 20131125 */
tmp = (regEAC & 0x03FF0000)>>16;
@@ -960,7 +917,6 @@ static void _PHY_PathAFillIQKMatrix8723B(
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
-/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
return;
}
@@ -1020,8 +976,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
/* 2 Tx IQC */
PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
-/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
-/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
@@ -1035,7 +989,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
if (bTxOnly) {
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
-/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
@@ -1051,7 +1004,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
reg = (result[final_candidate][7] >> 6) & 0xF;
-/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
}
@@ -1353,11 +1305,6 @@ static void phy_IQCalibrate_8723B(
_PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T);
-/* no serial mode */
-
- /* save RF path for 8723B */
-/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
-/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
/* MAC settings */
_PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
@@ -1370,14 +1317,6 @@ static void phy_IQCalibrate_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
-/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
-/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
-/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
-/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
-
-
-/* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
-
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
@@ -1389,7 +1328,6 @@ static void phy_IQCalibrate_8723B(
/* path A TX IQK */
for (i = 0 ; i < retryCount ; i++) {
PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
-/* if (PathAOK == 0x03) { */
if (PathAOK == 0x01) {
/* Path A Tx IQK Success */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
@@ -1407,8 +1345,6 @@ static void phy_IQCalibrate_8723B(
for (i = 0 ; i < retryCount ; i++) {
PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
if (PathAOK == 0x03) {
-/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
-/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
break;
@@ -1439,8 +1375,6 @@ static void phy_IQCalibrate_8723B(
for (i = 0 ; i < retryCount ; i++) {
PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
if (PathBOK == 0x03) {
-/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
-/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
break;
@@ -1462,9 +1396,6 @@ static void phy_IQCalibrate_8723B(
_PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
- /* Reload RF path */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
/* Allen initial gain 0xc50 */
/* Restore RX initial gain */
@@ -1642,14 +1573,6 @@ void PHY_IQCalibrate_8723B(
/* save default GNT_BT */
GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
- /* Save RF Path */
-/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
-/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
-
- /* set GNT_BT = 0, pause BT traffic */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
-
for (i = 0; i < 8; i++) {
result[0][i] = 0;
@@ -1742,10 +1665,6 @@ void PHY_IQCalibrate_8723B(
/* restore GNT_BT */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
- /* Restore RF Path */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
-/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
-
/* Resotr RX mode table parameter */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
@@ -1754,10 +1673,6 @@ void PHY_IQCalibrate_8723B(
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
- /* set GNT_BT = HW control */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
-/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
-
if (Is2ant) {
if (RF_Path == 0x0) /* S1 */
ODM_SetIQCbyRFpath(pDM_Odm, 0);
--
2.53.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] staging: rtl8723bs: fix comment style in HalPhyRf_8723B.c
2026-04-09 3:48 [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c Pranav Desai
@ 2026-04-09 3:48 ` Pranav Desai
2026-04-09 14:03 ` Luka Gejak
2026-04-09 13:14 ` [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code " Bera Yüzlü
2026-04-09 13:57 ` Luka Gejak
2 siblings, 1 reply; 5+ messages in thread
From: Pranav Desai @ 2026-04-09 3:48 UTC (permalink / raw)
To: gregkh; +Cc: linux-staging, straube.linux, b9788213, bera, Pranav Desai
removed extra spaces for comments and formated them to be more readable
Signed-off-by: Pranav Desai <contact.pranavdesai@gmail.com>
---
.../staging/rtl8723bs/hal/HalPhyRf_8723B.c | 120 +++++++++---------
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
index 63c848ebd661..d4e8ec172658 100644
--- a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
+++ b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
@@ -8,8 +8,8 @@
#include <drv_types.h>
#include "odm_precomp.h"
-/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
-#define PATH_S0 1 /* RF_PATH_B */
+/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
+#define PATH_S0 1 /* RF_PATH_B */
#define IDX_0xC94 0
#define IDX_0xC80 1
#define IDX_0xC14 0
@@ -17,8 +17,8 @@
#define KEY 0
#define VAL 1
-/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
-#define PATH_S1 0 /* RF_PATH_A */
+/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
+#define PATH_S1 0 /* RF_PATH_A */
#define IDX_0xC4C 2
/*---------------------------Define Local Constant---------------------------*/
@@ -210,7 +210,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
- /* Adjust BB swing by OFDM IQ matrix */
+ /* Adjust BB swing by OFDM IQ matrix */
if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
else if (Final_OFDM_Swing_Index <= 0)
@@ -269,7 +269,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
- } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
+ } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
setCCKFilterCoefficient(pDM_Odm, 0);
pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
@@ -284,7 +284,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
}
}
} else
- return; /* This method is not supported. */
+ return; /* This method is not supported. */
}
static void GetDeltaSwingTable_8723B(
@@ -350,17 +350,18 @@ static u8 phy_PathA_IQK_8723B(
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
- /* Save RF Path */
+ /* Save RF Path */
Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
/* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* enable path A PA in TXIQK mode */
+ /* enable path A PA in TXIQK mode */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
+ /* disable path B PA in TXIQK mode */
/* 1 Tx IQK */
/* IQK setting */
@@ -384,10 +385,10 @@ static u8 phy_PathA_IQK_8723B(
/* Ant switch */
if (configPathB || (RF_Path == 0))
- /* wifi switch to S1 */
+ /* wifi switch to S1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
else
- /* wifi switch to S0 */
+ /* wifi switch to S0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
/* GNT_BT = 0 */
@@ -408,7 +409,7 @@ static u8 phy_PathA_IQK_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
@@ -444,7 +445,7 @@ static u8 phy_PathA_RxIQK8723B(
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
- /* Save RF Path */
+ /* Save RF Path */
Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
/* leave IQK mode */
@@ -481,10 +482,10 @@ static u8 phy_PathA_RxIQK8723B(
/* Ant switch */
if (configPathB || (RF_Path == 0))
- /* wifi switch to S1 */
+ /* wifi switch to S1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
else
- /* wifi switch to S0 */
+ /* wifi switch to S0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
/* GNT_BT = 0 */
@@ -504,7 +505,7 @@ static u8 phy_PathA_RxIQK8723B(
/* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
@@ -564,10 +565,10 @@ static u8 phy_PathA_RxIQK8723B(
/* Ant switch */
if (configPathB || (RF_Path == 0))
- /* wifi switch to S1 */
+ /* wifi switch to S1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
else
- /* wifi switch to S0 */
+ /* wifi switch to S0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
/* GNT_BT = 0 */
@@ -584,14 +585,14 @@ static u8 phy_PathA_RxIQK8723B(
/* GNT_BT = 1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
- /* PA/PAD controlled by 0x0 */
+ /* PA/PAD controlled by 0x0 */
/* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
@@ -622,10 +623,10 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
- /* Save RF Path */
+ /* Save RF Path */
Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
@@ -671,10 +672,10 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
/* GNT_BT = 1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
@@ -705,9 +706,9 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
- /* Save RF Path */
+ /* Save RF Path */
Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
/* switch to path B */
@@ -741,7 +742,7 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* LO calibration setting */
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
- /* enter IQK mode */
+ /* enter IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
/* switch to path B */
@@ -762,10 +763,10 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* GNT_BT = 1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
@@ -819,7 +820,7 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* LO calibration setting */
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
- /* enter IQK mode */
+ /* enter IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
/* switch to path B */
@@ -839,10 +840,10 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
/* GNT_BT = 1 */
PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
- /* leave IQK mode */
+ /* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
- /* Check failed */
+ /* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
@@ -913,7 +914,7 @@ static void _PHY_PathAFillIQKMatrix8723B(
pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
if (bTxOnly) {
- /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
+ /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
@@ -1009,10 +1010,10 @@ static void _PHY_PathBFillIQKMatrix8723B(
}
}
-/* */
-/* 2011/07/26 MH Add an API for testing IQK fail case. */
-/* */
-/* MP Already declare in odm.c */
+/* */
+/* 2011/07/26 MH Add an API for testing IQK fail case. */
+/* */
+/* MP Already declare in odm.c */
void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath)
{
@@ -1290,14 +1291,14 @@ static void phy_IQCalibrate_8723B(
};
const u32 retryCount = 2;
- /* Note: IQ calibration must be performed after loading */
- /* PHY_REG.txt , and radio_a, radio_b.txt */
+ /* Note: IQ calibration must be performed after loading */
+ /* PHY_REG.txt , and radio_a, radio_b.txt */
/* u32 bbvalue; */
if (t == 0) {
- /* Save ADDA parameters, turn Path A ADDA on */
+ /* Save ADDA parameters, turn Path A ADDA on */
_PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
_PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
@@ -1325,11 +1326,11 @@ static void phy_IQCalibrate_8723B(
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
-/* path A TX IQK */
+ /* path A TX IQK */
for (i = 0 ; i < retryCount ; i++) {
PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
if (PathAOK == 0x01) {
- /* Path A Tx IQK Success */
+ /* Path A Tx IQK Success */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x8, bRFRegOffsetMask);
@@ -1361,7 +1362,7 @@ static void phy_IQCalibrate_8723B(
for (i = 0 ; i < retryCount ; i++) {
PathBOK = phy_PathB_IQK_8723B(padapter);
if (PathBOK == 0x01) {
- /* Path B Tx IQK Success */
+ /* Path B Tx IQK Success */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask);
@@ -1388,17 +1389,16 @@ static void phy_IQCalibrate_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
if (t != 0) {
- /* Reload ADDA power saving parameters */
+ /* Reload ADDA power saving parameters */
_PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
- /* Reload MAC parameters */
+ /* Reload MAC parameters */
_PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
_PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
-
/* Allen initial gain 0xc50 */
- /* Restore RX initial gain */
+ /* Restore RX initial gain */
PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
if (is2T) {
@@ -1426,8 +1426,8 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
- else /* Deal with Packet TX case */
- rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
+ else /* Deal with Packet TX case */
+ rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
if ((tmpReg&0x70) != 0) {
/* 1. Read original RF mode */
@@ -1451,14 +1451,14 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
LC_Cal = PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
/* 4. Set LC calibration begin bit15 */
- PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
+ PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
mdelay(100);
- PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
+ PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
- /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
+ /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
}
@@ -1472,7 +1472,7 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
/* Path-B */
if (is2T)
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
- } else /* Deal with Packet TX case */
+ } else /* Deal with Packet TX case */
rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
}
@@ -1516,7 +1516,7 @@ void PHY_IQCalibrate_8723B(
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
return;
- /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
+ /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
if (bSingleTone || bCarrierSuppression)
return;
@@ -1533,7 +1533,7 @@ void PHY_IQCalibrate_8723B(
path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_PATH_B;
- /* Restore TX IQK */
+ /* Restore TX IQK */
for (i = 0; i < 3; ++i) {
offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
@@ -1544,7 +1544,7 @@ void PHY_IQCalibrate_8723B(
PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
}
- /* Restore RX IQK */
+ /* Restore RX IQK */
for (i = 0; i < 2; ++i) {
offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
@@ -1654,8 +1654,8 @@ void PHY_IQCalibrate_8723B(
_PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
}
-/* To Fix BSOD when final_candidate is 0xff */
-/* by sherry 20120321 */
+ /* To Fix BSOD when final_candidate is 0xff */
+ /* by sherry 20120321 */
if (final_candidate < 4) {
for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] = result[final_candidate][i];
@@ -1692,7 +1692,7 @@ void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm)
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
return;
- /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
+ /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
if (bSingleTone || bCarrierSuppression)
return;
--
2.53.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/2] staging: rtl8723bs: fix comment style in HalPhyRf_8723B.c
2026-04-09 3:48 ` [PATCH 2/2] staging: rtl8723bs: fix comment style " Pranav Desai
@ 2026-04-09 14:03 ` Luka Gejak
0 siblings, 0 replies; 5+ messages in thread
From: Luka Gejak @ 2026-04-09 14:03 UTC (permalink / raw)
To: Pranav Desai, gregkh; +Cc: linux-staging, straube.linux, b9788213, bera
On Thu Apr 9, 2026 at 5:48 AM CEST, Pranav Desai wrote:
> removed extra spaces for comments and formated them to be more readable
>
> Signed-off-by: Pranav Desai <contact.pranavdesai@gmail.com>
> ---
> .../staging/rtl8723bs/hal/HalPhyRf_8723B.c | 120 +++++++++---------
> 1 file changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> index 63c848ebd661..d4e8ec172658 100644
> --- a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> +++ b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> @@ -8,8 +8,8 @@
> #include <drv_types.h>
> #include "odm_precomp.h"
>
> -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
> -#define PATH_S0 1 /* RF_PATH_B */
> +/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
> +#define PATH_S0 1 /* RF_PATH_B */
> #define IDX_0xC94 0
> #define IDX_0xC80 1
> #define IDX_0xC14 0
> @@ -17,8 +17,8 @@
> #define KEY 0
> #define VAL 1
>
> -/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
> -#define PATH_S1 0 /* RF_PATH_A */
> +/* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
> +#define PATH_S1 0 /* RF_PATH_A */
> #define IDX_0xC4C 2
>
> /*---------------------------Define Local Constant---------------------------*/
> @@ -210,7 +210,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
> Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
> Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
>
> - /* Adjust BB swing by OFDM IQ matrix */
> + /* Adjust BB swing by OFDM IQ matrix */
> if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
> Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
> else if (Final_OFDM_Swing_Index <= 0)
> @@ -269,7 +269,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
> setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
> pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
> PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
> - } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
> + } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
> pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
> setCCKFilterCoefficient(pDM_Odm, 0);
> pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
> @@ -284,7 +284,7 @@ void ODM_TxPwrTrackSetPwr_8723B(
> }
> }
> } else
> - return; /* This method is not supported. */
> + return; /* This method is not supported. */
> }
>
> static void GetDeltaSwingTable_8723B(
> @@ -350,17 +350,18 @@ static u8 phy_PathA_IQK_8723B(
> struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
> struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
>
> - /* Save RF Path */
> + /* Save RF Path */
> Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
>
> /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* enable path A PA in TXIQK mode */
> + /* enable path A PA in TXIQK mode */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
> + /* disable path B PA in TXIQK mode */
The code that actually disabled Path B was the dead code removed in
patch 1. By adding this comment back in patch 2 at the end of the
block, you leave a dangling, highly confusing comment that implies the
preceding RF_PATH_A code is disabling PATH_B. This is dangerous for
future maintainers trying to understand the hardware configuration. In
this patch, ensure you are only reformatting existing, valid comments.
Do not introduce dangling comments for code that no longer exists.
Best regards,
Luka Gejak
>
> /* 1 Tx IQK */
> /* IQK setting */
> @@ -384,10 +385,10 @@ static u8 phy_PathA_IQK_8723B(
>
> /* Ant switch */
> if (configPathB || (RF_Path == 0))
> - /* wifi switch to S1 */
> + /* wifi switch to S1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
> else
> - /* wifi switch to S0 */
> + /* wifi switch to S0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
>
> /* GNT_BT = 0 */
> @@ -408,7 +409,7 @@ static u8 phy_PathA_IQK_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
> regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
> @@ -444,7 +445,7 @@ static u8 phy_PathA_RxIQK8723B(
> struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
> struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
>
> - /* Save RF Path */
> + /* Save RF Path */
> Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
>
> /* leave IQK mode */
> @@ -481,10 +482,10 @@ static u8 phy_PathA_RxIQK8723B(
>
> /* Ant switch */
> if (configPathB || (RF_Path == 0))
> - /* wifi switch to S1 */
> + /* wifi switch to S1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
> else
> - /* wifi switch to S0 */
> + /* wifi switch to S0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
>
> /* GNT_BT = 0 */
> @@ -504,7 +505,7 @@ static u8 phy_PathA_RxIQK8723B(
> /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
> regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
> @@ -564,10 +565,10 @@ static u8 phy_PathA_RxIQK8723B(
>
> /* Ant switch */
> if (configPathB || (RF_Path == 0))
> - /* wifi switch to S1 */
> + /* wifi switch to S1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
> else
> - /* wifi switch to S0 */
> + /* wifi switch to S0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
>
> /* GNT_BT = 0 */
> @@ -584,14 +585,14 @@ static u8 phy_PathA_RxIQK8723B(
> /* GNT_BT = 1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
>
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
>
> - /* PA/PAD controlled by 0x0 */
> + /* PA/PAD controlled by 0x0 */
> /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
> @@ -622,10 +623,10 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
> struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
> struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
>
> - /* Save RF Path */
> + /* Save RF Path */
> Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
>
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
> @@ -671,10 +672,10 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
> /* GNT_BT = 1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
>
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
> regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
> @@ -705,9 +706,9 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
> struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
>
> - /* Save RF Path */
> + /* Save RF Path */
> Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> /* switch to path B */
> @@ -741,7 +742,7 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> /* LO calibration setting */
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
>
> - /* enter IQK mode */
> + /* enter IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
>
> /* switch to path B */
> @@ -762,10 +763,10 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> /* GNT_BT = 1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
>
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
> regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
> @@ -819,7 +820,7 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> /* LO calibration setting */
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
>
> - /* enter IQK mode */
> + /* enter IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
>
> /* switch to path B */
> @@ -839,10 +840,10 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> /* GNT_BT = 1 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
>
> - /* leave IQK mode */
> + /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* Check failed */
> + /* Check failed */
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
>
> @@ -913,7 +914,7 @@ static void _PHY_PathAFillIQKMatrix8723B(
> pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
>
> if (bTxOnly) {
> - /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
> + /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
> @@ -1009,10 +1010,10 @@ static void _PHY_PathBFillIQKMatrix8723B(
> }
> }
>
> -/* */
> -/* 2011/07/26 MH Add an API for testing IQK fail case. */
> -/* */
> -/* MP Already declare in odm.c */
> +/* */
> +/* 2011/07/26 MH Add an API for testing IQK fail case. */
> +/* */
> +/* MP Already declare in odm.c */
>
> void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath)
> {
> @@ -1290,14 +1291,14 @@ static void phy_IQCalibrate_8723B(
> };
> const u32 retryCount = 2;
>
> - /* Note: IQ calibration must be performed after loading */
> - /* PHY_REG.txt , and radio_a, radio_b.txt */
> + /* Note: IQ calibration must be performed after loading */
> + /* PHY_REG.txt , and radio_a, radio_b.txt */
>
> /* u32 bbvalue; */
>
> if (t == 0) {
>
> - /* Save ADDA parameters, turn Path A ADDA on */
> + /* Save ADDA parameters, turn Path A ADDA on */
> _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
> _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
> _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
> @@ -1325,11 +1326,11 @@ static void phy_IQCalibrate_8723B(
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
>
> -/* path A TX IQK */
> + /* path A TX IQK */
> for (i = 0 ; i < retryCount ; i++) {
> PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
> if (PathAOK == 0x01) {
> - /* Path A Tx IQK Success */
> + /* Path A Tx IQK Success */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
> pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x8, bRFRegOffsetMask);
>
> @@ -1361,7 +1362,7 @@ static void phy_IQCalibrate_8723B(
> for (i = 0 ; i < retryCount ; i++) {
> PathBOK = phy_PathB_IQK_8723B(padapter);
> if (PathBOK == 0x01) {
> - /* Path B Tx IQK Success */
> + /* Path B Tx IQK Success */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
> pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask);
>
> @@ -1388,17 +1389,16 @@ static void phy_IQCalibrate_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
>
> if (t != 0) {
> - /* Reload ADDA power saving parameters */
> + /* Reload ADDA power saving parameters */
> _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
>
> - /* Reload MAC parameters */
> + /* Reload MAC parameters */
> _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
>
> _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
>
> -
> /* Allen initial gain 0xc50 */
> - /* Restore RX initial gain */
> + /* Restore RX initial gain */
> PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
> PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
> if (is2T) {
> @@ -1426,8 +1426,8 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
>
> if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
> rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
> - else /* Deal with Packet TX case */
> - rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
> + else /* Deal with Packet TX case */
> + rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
>
> if ((tmpReg&0x70) != 0) {
> /* 1. Read original RF mode */
> @@ -1451,14 +1451,14 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
> LC_Cal = PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
>
> /* 4. Set LC calibration begin bit15 */
> - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
> + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
>
> mdelay(100);
>
> - PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
> + PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
>
> - /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
> + /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
> if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
> }
> @@ -1472,7 +1472,7 @@ static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
> /* Path-B */
> if (is2T)
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
> - } else /* Deal with Packet TX case */
> + } else /* Deal with Packet TX case */
> rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
> }
>
> @@ -1516,7 +1516,7 @@ void PHY_IQCalibrate_8723B(
> if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
> return;
>
> - /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
> + /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
> if (bSingleTone || bCarrierSuppression)
> return;
>
> @@ -1533,7 +1533,7 @@ void PHY_IQCalibrate_8723B(
>
> path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_PATH_B;
>
> - /* Restore TX IQK */
> + /* Restore TX IQK */
> for (i = 0; i < 3; ++i) {
> offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
> data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
> @@ -1544,7 +1544,7 @@ void PHY_IQCalibrate_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
> }
>
> - /* Restore RX IQK */
> + /* Restore RX IQK */
> for (i = 0; i < 2; ++i) {
> offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
> data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
> @@ -1654,8 +1654,8 @@ void PHY_IQCalibrate_8723B(
> _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
> }
>
> -/* To Fix BSOD when final_candidate is 0xff */
> -/* by sherry 20120321 */
> + /* To Fix BSOD when final_candidate is 0xff */
> + /* by sherry 20120321 */
> if (final_candidate < 4) {
> for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
> pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] = result[final_candidate][i];
> @@ -1692,7 +1692,7 @@ void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm)
> if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
> return;
>
> - /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
> + /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
> if (bSingleTone || bCarrierSuppression)
> return;
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c
2026-04-09 3:48 [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c Pranav Desai
2026-04-09 3:48 ` [PATCH 2/2] staging: rtl8723bs: fix comment style " Pranav Desai
@ 2026-04-09 13:14 ` Bera Yüzlü
2026-04-09 13:57 ` Luka Gejak
2 siblings, 0 replies; 5+ messages in thread
From: Bera Yüzlü @ 2026-04-09 13:14 UTC (permalink / raw)
To: contact.pranavdesai; +Cc: b9788213, bera, gregkh, linux-staging, straube.linux
On Thu, 9 Apr 2026 09:18:58 +0530, Pranav Desai wrote:
> Remove commented-out code blocks
>
> Signed-off-by: Pranav Desai <contact.pranavdesai@gmail.com>
> ---
Put a period at the end of the sentence. Patch series needs a cover
letter. Also my mail is not bera@yuzu.li.
Thanks,
Bera
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c
2026-04-09 3:48 [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c Pranav Desai
2026-04-09 3:48 ` [PATCH 2/2] staging: rtl8723bs: fix comment style " Pranav Desai
2026-04-09 13:14 ` [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code " Bera Yüzlü
@ 2026-04-09 13:57 ` Luka Gejak
2 siblings, 0 replies; 5+ messages in thread
From: Luka Gejak @ 2026-04-09 13:57 UTC (permalink / raw)
To: Pranav Desai, gregkh; +Cc: linux-staging, straube.linux, b9788213, bera
On Thu Apr 9, 2026 at 5:48 AM CEST, Pranav Desai wrote:
> Remove commented-out code blocks
>
> Signed-off-by: Pranav Desai <contact.pranavdesai@gmail.com>
Hi Pranav,
This patch removes some comments that describe code that is not
commented-out. Please carefully review this patch to ensure you are
only removing commented-out C code (and comments that explicitly
describe that dead code). Do not remove active comments.
Best regards,
Luka Gejak
> ---
> .../staging/rtl8723bs/hal/HalPhyRf_8723B.c | 85 -------------------
> 1 file changed, 85 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> index 8f6849f2277e..63c848ebd661 100644
> --- a/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> +++ b/drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c
> @@ -361,9 +361,6 @@ static u8 phy_PathA_IQK_8723B(
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
> - /* disable path B PA in TXIQK mode */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
>
> /* 1 Tx IQK */
> /* IQK setting */
> @@ -374,7 +371,6 @@ static u8 phy_PathA_IQK_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> @@ -401,8 +397,6 @@ static u8 phy_PathA_IQK_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -462,7 +456,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
> /* LNA2 off, PA on for Dcut */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
>
> /* IQK setting */
> @@ -475,7 +468,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
>
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> @@ -502,8 +494,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -546,7 +536,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
> /* LAN2 on, PA off for Dcut */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
>
> /* PA, PAD setting */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
> @@ -563,7 +552,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
>
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
> @@ -589,8 +577,6 @@ static u8 phy_PathA_RxIQK8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -642,12 +628,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
> /* leave IQK mode */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
>
> - /* in TXIQK mode */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
> - /* enable path B PA in TXIQK mode */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
>
> @@ -663,7 +643,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
>
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> @@ -677,7 +656,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
>
> /* switch to path B */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
>
> /* GNT_BT = 0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
> @@ -686,8 +664,6 @@ static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -757,7 +733,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
>
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> @@ -771,7 +746,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
>
> /* switch to path B */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
>
> /* GNT_BT = 0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
> @@ -781,8 +755,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -825,16 +797,11 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
>
> /* open PA S1 & close SMIXER */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
>
> - /* PA, PAD setting */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
> -
> /* IQK setting */
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
>
> @@ -845,7 +812,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
>
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
> PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
> PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
> @@ -858,7 +824,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
>
> /* switch to path B */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
>
> /* GNT_BT = 0 */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
> @@ -867,8 +832,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
> PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
>
> - /* delay x ms */
> - /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
> mdelay(IQK_DELAY_TIME_8723B);
>
> /* restore Ant Path */
> @@ -883,12 +846,6 @@ static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
> regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
> regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
>
> - /* PA/PAD controlled by 0x0 */
> - /* leave IQK mode */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
> -
> -
>
> /* Allen 20131125 */
> tmp = (regEAC & 0x03FF0000)>>16;
> @@ -960,7 +917,6 @@ static void _PHY_PathAFillIQKMatrix8723B(
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
> -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
> pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
> return;
> }
> @@ -1020,8 +976,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
>
> /* 2 Tx IQC */
> PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
> -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
> -/* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
> pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
> pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
>
> @@ -1035,7 +989,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
>
> if (bTxOnly) {
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
> -/* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
> @@ -1051,7 +1004,6 @@ static void _PHY_PathBFillIQKMatrix8723B(
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
>
> reg = (result[final_candidate][7] >> 6) & 0xF;
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
> pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
> }
> @@ -1353,11 +1305,6 @@ static void phy_IQCalibrate_8723B(
>
> _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T);
>
> -/* no serial mode */
> -
> - /* save RF path for 8723B */
> -/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
> -/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
>
> /* MAC settings */
> _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
> @@ -1370,14 +1317,6 @@ static void phy_IQCalibrate_8723B(
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
>
>
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
> -
> -
> -/* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
> -
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
> @@ -1389,7 +1328,6 @@ static void phy_IQCalibrate_8723B(
> /* path A TX IQK */
> for (i = 0 ; i < retryCount ; i++) {
> PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
> -/* if (PathAOK == 0x03) { */
> if (PathAOK == 0x01) {
> /* Path A Tx IQK Success */
> PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
> @@ -1407,8 +1345,6 @@ static void phy_IQCalibrate_8723B(
> for (i = 0 ; i < retryCount ; i++) {
> PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
> if (PathAOK == 0x03) {
> -/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
> -/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
> result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
> result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
> break;
> @@ -1439,8 +1375,6 @@ static void phy_IQCalibrate_8723B(
> for (i = 0 ; i < retryCount ; i++) {
> PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
> if (PathBOK == 0x03) {
> -/* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
> -/* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
> result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
> result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
> break;
> @@ -1462,9 +1396,6 @@ static void phy_IQCalibrate_8723B(
>
> _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
>
> - /* Reload RF path */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
>
> /* Allen initial gain 0xc50 */
> /* Restore RX initial gain */
> @@ -1642,14 +1573,6 @@ void PHY_IQCalibrate_8723B(
>
> /* save default GNT_BT */
> GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
> - /* Save RF Path */
> -/* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
> -/* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
> -
> - /* set GNT_BT = 0, pause BT traffic */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
> -
>
> for (i = 0; i < 8; i++) {
> result[0][i] = 0;
> @@ -1742,10 +1665,6 @@ void PHY_IQCalibrate_8723B(
>
> /* restore GNT_BT */
> PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
> - /* Restore RF Path */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
> -/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
> -
> /* Resotr RX mode table parameter */
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
> @@ -1754,10 +1673,6 @@ void PHY_IQCalibrate_8723B(
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
> PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
>
> - /* set GNT_BT = HW control */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
> -/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
> -
> if (Is2ant) {
> if (RF_Path == 0x0) /* S1 */
> ODM_SetIQCbyRFpath(pDM_Odm, 0);
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-04-09 14:04 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-09 3:48 [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code in HalPhyRf_8723B.c Pranav Desai
2026-04-09 3:48 ` [PATCH 2/2] staging: rtl8723bs: fix comment style " Pranav Desai
2026-04-09 14:03 ` Luka Gejak
2026-04-09 13:14 ` [PATCH 1/2] staging: rtl8723bs: remove commented-out dead code " Bera Yüzlü
2026-04-09 13:57 ` Luka Gejak
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