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8bit From: Kenet Jovan Sokoli Signed-off-by: Kenet Jovan Sokoli --- arch/mips/cavium-octeon/executive/Makefile | 8 +- .../executive/cvmx-helper-errata.c | 73 - .../executive/cvmx-helper-jtag.c | 144 - .../executive/cvmx-helper-loop.c | 85 - .../cavium-octeon/executive/cvmx-helper-npi.c | 101 - drivers/staging/octeon/Makefile | 14 + drivers/staging/octeon/cvmx-address.h | 339 ++ drivers/staging/octeon/cvmx-agl-defs.h | 1758 +++++++ drivers/staging/octeon/cvmx-asm.h | 138 + drivers/staging/octeon/cvmx-asxx-defs.h | 565 +++ drivers/staging/octeon/cvmx-bootinfo.h | 427 ++ drivers/staging/octeon/cvmx-bootmem.h | 339 ++ drivers/staging/octeon/cvmx-ciu-defs.h | 175 + drivers/staging/octeon/cvmx-ciu2-defs.h | 47 + drivers/staging/octeon/cvmx-ciu3-defs.h | 353 ++ .../staging/octeon}/cvmx-cmd-queue.c | 205 +- drivers/staging/octeon/cvmx-cmd-queue.h | 620 +++ drivers/staging/octeon/cvmx-config.h | 169 + drivers/staging/octeon/cvmx-coremask.h | 88 + drivers/staging/octeon/cvmx-dbg-defs.h | 100 + drivers/staging/octeon/cvmx-dpi-defs.h | 873 ++++ drivers/staging/octeon/cvmx-fau.h | 618 +++ drivers/staging/octeon/cvmx-fpa-defs.h | 1251 +++++ drivers/staging/octeon/cvmx-fpa.h | 290 ++ drivers/staging/octeon/cvmx-gmxx-defs.h | 2258 +++++++++ drivers/staging/octeon/cvmx-gpio-defs.h | 398 ++ .../staging/octeon}/cvmx-helper-board.c | 197 +- drivers/staging/octeon/cvmx-helper-board.h | 123 + drivers/staging/octeon/cvmx-helper-errata.c | 73 + drivers/staging/octeon/cvmx-helper-errata.h | 32 + drivers/staging/octeon/cvmx-helper-jtag.c | 145 + drivers/staging/octeon/cvmx-helper-jtag.h | 42 + drivers/staging/octeon/cvmx-helper-loop.c | 85 + drivers/staging/octeon/cvmx-helper-loop.h | 59 + drivers/staging/octeon/cvmx-helper-npi.c | 101 + drivers/staging/octeon/cvmx-helper-npi.h | 60 + .../staging/octeon}/cvmx-helper-rgmii.c | 211 +- drivers/staging/octeon/cvmx-helper-rgmii.h | 92 + .../staging/octeon}/cvmx-helper-sgmii.c | 228 +- drivers/staging/octeon/cvmx-helper-sgmii.h | 86 + .../staging/octeon}/cvmx-helper-spi.c | 153 +- drivers/staging/octeon/cvmx-helper-spi.h | 83 + .../staging/octeon}/cvmx-helper-util.c | 216 +- drivers/staging/octeon/cvmx-helper-util.h | 191 + drivers/staging/octeon/cvmx-helper-xaui.c | 322 ++ drivers/staging/octeon/cvmx-helper-xaui.h | 86 + .../staging/octeon}/cvmx-helper.c | 423 +- drivers/staging/octeon/cvmx-helper.h | 170 + drivers/staging/octeon/cvmx-iob-defs.h | 902 ++++ drivers/staging/octeon/cvmx-ipd-defs.h | 1471 ++++++ drivers/staging/octeon/cvmx-ipd.h | 348 ++ drivers/staging/octeon/cvmx-l2c-defs.h | 237 + drivers/staging/octeon/cvmx-l2c.h | 361 ++ drivers/staging/octeon/cvmx-l2d-defs.h | 58 + drivers/staging/octeon/cvmx-l2t-defs.h | 141 + drivers/staging/octeon/cvmx-led-defs.h | 213 + drivers/staging/octeon/cvmx-lmcx-defs.h | 2942 +++++++++++ drivers/staging/octeon/cvmx-mio-defs.h | 4395 +++++++++++++++++ drivers/staging/octeon/cvmx-mixx-defs.h | 429 ++ drivers/staging/octeon/cvmx-npei-defs.h | 3924 +++++++++++++++ drivers/staging/octeon/cvmx-npi-defs.h | 2513 ++++++++++ drivers/staging/octeon/cvmx-packet.h | 68 + drivers/staging/octeon/cvmx-pci-defs.h | 2036 ++++++++ drivers/staging/octeon/cvmx-pciercx-defs.h | 367 ++ drivers/staging/octeon/cvmx-pcsx-defs.h | 825 ++++ drivers/staging/octeon/cvmx-pcsxx-defs.h | 663 +++ drivers/staging/octeon/cvmx-pemx-defs.h | 650 +++ drivers/staging/octeon/cvmx-pescx-defs.h | 578 +++ drivers/staging/octeon/cvmx-pexp-defs.h | 223 + drivers/staging/octeon/cvmx-pip-defs.h | 2733 ++++++++++ drivers/staging/octeon/cvmx-pip.h | 527 ++ drivers/staging/octeon/cvmx-pko-defs.h | 2204 +++++++++ .../staging/octeon}/cvmx-pko.c | 257 +- drivers/staging/octeon/cvmx-pko.h | 645 +++ drivers/staging/octeon/cvmx-pow-defs.h | 1000 ++++ drivers/staging/octeon/cvmx-pow.h | 2219 +++++++++ drivers/staging/octeon/cvmx-rst-defs.h | 277 ++ drivers/staging/octeon/cvmx-scratch.h | 138 + drivers/staging/octeon/cvmx-sli-defs.h | 127 + .../staging/octeon}/cvmx-spi.c | 324 +- drivers/staging/octeon/cvmx-spi.h | 270 + drivers/staging/octeon/cvmx-spxx-defs.h | 445 ++ drivers/staging/octeon/cvmx-sriox-defs.h | 1613 ++++++ drivers/staging/octeon/cvmx-srxx-defs.h | 139 + drivers/staging/octeon/cvmx-stxx-defs.h | 329 ++ drivers/staging/octeon/cvmx-sysinfo.h | 123 + drivers/staging/octeon/cvmx-uctlx-defs.h | 385 ++ drivers/staging/octeon/cvmx-wqe.h | 655 +++ drivers/staging/octeon/cvmx.h | 496 ++ drivers/staging/octeon/ethernet-defines.h | 32 +- drivers/staging/octeon/ethernet-mdio.c | 34 +- drivers/staging/octeon/ethernet-mdio.h | 8 +- drivers/staging/octeon/ethernet-mem.c | 56 +- drivers/staging/octeon/ethernet-mem.h | 8 +- drivers/staging/octeon/ethernet-rgmii.c | 8 +- drivers/staging/octeon/ethernet-rx.c | 54 +- drivers/staging/octeon/ethernet-rx.h | 8 +- drivers/staging/octeon/ethernet-sgmii.c | 8 +- drivers/staging/octeon/ethernet-spi.c | 8 +- drivers/staging/octeon/ethernet-tx.c | 50 +- drivers/staging/octeon/ethernet-tx.h | 8 +- drivers/staging/octeon/ethernet-util.h | 38 +- drivers/staging/octeon/ethernet.c | 84 +- drivers/staging/octeon/octeon-ethernet.h | 56 +- drivers/staging/octeon/octeon-feature.h | 212 + drivers/staging/octeon/octeon-model.h | 408 ++ drivers/staging/octeon/octeon-stubs.h | 1435 ------ drivers/staging/octeon/octeon.h | 364 ++ 108 files changed, 52564 insertions(+), 3179 deletions(-) delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c delete mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-npi.c create mode 100644 drivers/staging/octeon/cvmx-address.h create mode 100644 drivers/staging/octeon/cvmx-agl-defs.h create mode 100644 drivers/staging/octeon/cvmx-asm.h create mode 100644 drivers/staging/octeon/cvmx-asxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-bootinfo.h create mode 100644 drivers/staging/octeon/cvmx-bootmem.h create mode 100644 drivers/staging/octeon/cvmx-ciu-defs.h create mode 100644 drivers/staging/octeon/cvmx-ciu2-defs.h create mode 100644 drivers/staging/octeon/cvmx-ciu3-defs.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-cmd-queue.c (57%) create mode 100644 drivers/staging/octeon/cvmx-cmd-queue.h create mode 100644 drivers/staging/octeon/cvmx-config.h create mode 100644 drivers/staging/octeon/cvmx-coremask.h create mode 100644 drivers/staging/octeon/cvmx-dbg-defs.h create mode 100644 drivers/staging/octeon/cvmx-dpi-defs.h create mode 100644 drivers/staging/octeon/cvmx-fau.h create mode 100644 drivers/staging/octeon/cvmx-fpa-defs.h create mode 100644 drivers/staging/octeon/cvmx-fpa.h create mode 100644 drivers/staging/octeon/cvmx-gmxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-gpio-defs.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper-board.c (61%) create mode 100644 drivers/staging/octeon/cvmx-helper-board.h create mode 100644 drivers/staging/octeon/cvmx-helper-errata.c create mode 100644 drivers/staging/octeon/cvmx-helper-errata.h create mode 100644 drivers/staging/octeon/cvmx-helper-jtag.c create mode 100644 drivers/staging/octeon/cvmx-helper-jtag.h create mode 100644 drivers/staging/octeon/cvmx-helper-loop.c create mode 100644 drivers/staging/octeon/cvmx-helper-loop.h create mode 100644 drivers/staging/octeon/cvmx-helper-npi.c create mode 100644 drivers/staging/octeon/cvmx-helper-npi.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper-rgmii.c (75%) create mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper-sgmii.c (75%) create mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper-spi.c (56%) create mode 100644 drivers/staging/octeon/cvmx-helper-spi.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper-util.c (64%) create mode 100644 drivers/staging/octeon/cvmx-helper-util.h create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.c create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-helper.c (78%) create mode 100644 drivers/staging/octeon/cvmx-helper.h create mode 100644 drivers/staging/octeon/cvmx-iob-defs.h create mode 100644 drivers/staging/octeon/cvmx-ipd-defs.h create mode 100644 drivers/staging/octeon/cvmx-ipd.h create mode 100644 drivers/staging/octeon/cvmx-l2c-defs.h create mode 100644 drivers/staging/octeon/cvmx-l2c.h create mode 100644 drivers/staging/octeon/cvmx-l2d-defs.h create mode 100644 drivers/staging/octeon/cvmx-l2t-defs.h create mode 100644 drivers/staging/octeon/cvmx-led-defs.h create mode 100644 drivers/staging/octeon/cvmx-lmcx-defs.h create mode 100644 drivers/staging/octeon/cvmx-mio-defs.h create mode 100644 drivers/staging/octeon/cvmx-mixx-defs.h create mode 100644 drivers/staging/octeon/cvmx-npei-defs.h create mode 100644 drivers/staging/octeon/cvmx-npi-defs.h create mode 100644 drivers/staging/octeon/cvmx-packet.h create mode 100644 drivers/staging/octeon/cvmx-pci-defs.h create mode 100644 drivers/staging/octeon/cvmx-pciercx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pcsx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pcsxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pemx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pescx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pexp-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip.h create mode 100644 drivers/staging/octeon/cvmx-pko-defs.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-pko.c (71%) create mode 100644 drivers/staging/octeon/cvmx-pko.h create mode 100644 drivers/staging/octeon/cvmx-pow-defs.h create mode 100644 drivers/staging/octeon/cvmx-pow.h create mode 100644 drivers/staging/octeon/cvmx-rst-defs.h create mode 100644 drivers/staging/octeon/cvmx-scratch.h create mode 100644 drivers/staging/octeon/cvmx-sli-defs.h rename {arch/mips/cavium-octeon/executive => drivers/staging/octeon}/cvmx-spi.c (70%) create mode 100644 drivers/staging/octeon/cvmx-spi.h create mode 100644 drivers/staging/octeon/cvmx-spxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-sriox-defs.h create mode 100644 drivers/staging/octeon/cvmx-srxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-stxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-sysinfo.h create mode 100644 drivers/staging/octeon/cvmx-uctlx-defs.h create mode 100644 drivers/staging/octeon/cvmx-wqe.h create mode 100644 drivers/staging/octeon/cvmx.h create mode 100644 drivers/staging/octeon/octeon-feature.h create mode 100644 drivers/staging/octeon/octeon-model.h delete mode 100644 drivers/staging/octeon/octeon-stubs.h create mode 100644 drivers/staging/octeon/octeon.h diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 50b427879465..f738eb1cad4d 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -10,10 +10,4 @@ # obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o -obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ - cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ - cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ - cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o - -obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o +obj-y += cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o cvmx-boot-vector.o diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c deleted file mode 100644 index 4b26fedecf46..000000000000 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c +++ /dev/null @@ -1,73 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Fixes and workaround for Octeon chip errata. This file - * contains functions called by cvmx-helper to workaround known - * chip errata. For the most part, code doesn't need to call - * these functions directly. - * - */ -#include - -#include - -#include - -/** - * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass - * 1 doesn't work properly. The following code disables 2nd order - * CDR for the specified QLM. - * - * @qlm: QLM to disable 2nd order CDR for. - */ -void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm) -{ - int lane; - cvmx_helper_qlm_jtag_init(); - /* We need to load all four lanes of the QLM, a total of 1072 bits */ - for (lane = 0; lane < 4; lane++) { - /* - * Each lane has 268 bits. We need to set - * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> = - * 1. All other bits are zero. Bits go in LSB first, - * so start off with the zeros for bits <63:0>. - */ - cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1); - /* cfg_cdr_incx<67:64>=3 */ - cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3); - /* Zeros for bits <76:68> */ - cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1); - /* cfg_cdr_secord<77>=1 */ - cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1); - /* Zeros for bits <267:78> */ - cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1); - } - cvmx_helper_qlm_jtag_update(qlm); -} -EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr); diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c deleted file mode 100644 index 1fceb7fd2c94..000000000000 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c +++ /dev/null @@ -1,144 +0,0 @@ - -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Helper utilities for qlm_jtag. - * - */ - -#include -#include - - -/** - * Initialize the internal QLM JTAG logic to allow programming - * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions. - * These functions should only be used at the direction of Cavium - * Networks. Programming incorrect values into the JTAG chain - * can cause chip damage. - */ -void cvmx_helper_qlm_jtag_init(void) -{ - union cvmx_ciu_qlm_jtgc jtgc; - uint32_t clock_div = 0; - uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); - divisor = (divisor - 1) >> 2; - /* Convert the divisor into a power of 2 shift */ - while (divisor) { - clock_div++; - divisor = divisor >> 1; - } - - /* - * Clock divider for QLM JTAG operations. eclk is divided by - * 2^(CLK_DIV + 2) - */ - jtgc.u64 = 0; - jtgc.s.clk_div = clock_div; - jtgc.s.mux_sel = 0; - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - jtgc.s.bypass = 0x3; - else - jtgc.s.bypass = 0xf; - cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); - cvmx_read_csr(CVMX_CIU_QLM_JTGC); -} - -/** - * Write up to 32bits into the QLM jtag chain. Bits are shifted - * into the MSB and out the LSB, so you should shift in the low - * order bits followed by the high order bits. The JTAG chain is - * 4 * 268 bits long, or 1072. - * - * @qlm: QLM to shift value into - * @bits: Number of bits to shift in (1-32). - * @data: Data to shift in. Bit 0 enters the chain first, followed by - * bit 1, etc. - * - * Returns The low order bits of the JTAG chain that shifted out of the - * circle. - */ -uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) -{ - union cvmx_ciu_qlm_jtgd jtgd; - jtgd.u64 = 0; - jtgd.s.shift = 1; - jtgd.s.shft_cnt = bits - 1; - jtgd.s.shft_reg = data; - if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) - jtgd.s.select = 1 << qlm; - cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); - do { - jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); - } while (jtgd.s.shift); - return jtgd.s.shft_reg >> (32 - bits); -} - -/** - * Shift long sequences of zeros into the QLM JTAG chain. It is - * common to need to shift more than 32 bits of zeros into the - * chain. This function is a convenience wrapper around - * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of - * zeros at a time. - * - * @qlm: QLM to shift zeros into - * @bits: - */ -void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) -{ - while (bits > 0) { - int n = bits; - if (n > 32) - n = 32; - cvmx_helper_qlm_jtag_shift(qlm, n, 0); - bits -= n; - } -} - -/** - * Program the QLM JTAG chain into all lanes of the QLM. You must - * have already shifted in 268*4, or 1072 bits into the JTAG - * chain. Updating invalid values can possibly cause chip damage. - * - * @qlm: QLM to program - */ -void cvmx_helper_qlm_jtag_update(int qlm) -{ - union cvmx_ciu_qlm_jtgd jtgd; - - /* Update the new data */ - jtgd.u64 = 0; - jtgd.s.update = 1; - if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) - jtgd.s.select = 1 << qlm; - cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); - do { - jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); - } while (jtgd.s.update); -} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c deleted file mode 100644 index bfbd46115e71..000000000000 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c +++ /dev/null @@ -1,85 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for LOOP initialization, configuration, - * and monitoring. - */ -#include - -#include - -#include -#include - -/** - * Probe a LOOP interface and determine the number of ports - * connected to it. The LOOP interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_loop_probe(int interface) -{ - union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; - int num_ports = 4; - int port; - - /* We need to disable length checking so packet < 64 bytes and jumbo - frames don't get errors */ - for (port = 0; port < num_ports; port++) { - union cvmx_pip_prt_cfgx port_cfg; - int ipd_port = cvmx_helper_get_ipd_port(interface, port); - port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - port_cfg.s.maxerr_en = 0; - port_cfg.s.minerr_en = 0; - cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); - } - - /* Disable FCS stripping for loopback ports */ - ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); - ipd_sub_port_fcs.s.port_bit2 = 0; - cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); - return num_ports; -} - -/** - * Bringup and enable a LOOP interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_loop_enable(int interface) -{ - /* Do nothing. */ - return 0; -} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c deleted file mode 100644 index cb210d2ef0c4..000000000000 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c +++ /dev/null @@ -1,101 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for NPI initialization, configuration, - * and monitoring. - */ -#include - -#include - -#include - -#include - -/** - * Probe a NPI interface and determine the number of ports - * connected to it. The NPI interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_npi_probe(int interface) -{ -#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - return 4; - else if (OCTEON_IS_MODEL(OCTEON_CN56XX) - && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) - /* The packet engines didn't exist before pass 2 */ - return 4; - else if (OCTEON_IS_MODEL(OCTEON_CN52XX) - && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) - /* The packet engines didn't exist before pass 2 */ - return 4; -#endif - return 0; -} - -/** - * Bringup and enable a NPI interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_npi_enable(int interface) -{ - /* - * On CN50XX, CN52XX, and CN56XX we need to disable length - * checking so packet < 64 bytes and jumbo frames don't get - * errors. - */ - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && - !OCTEON_IS_MODEL(OCTEON_CN58XX)) { - int num_ports = cvmx_helper_ports_on_interface(interface); - int port; - for (port = 0; port < num_ports; port++) { - union cvmx_pip_prt_cfgx port_cfg; - int ipd_port = - cvmx_helper_get_ipd_port(interface, port); - port_cfg.u64 = - cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - port_cfg.s.maxerr_en = 0; - port_cfg.s.minerr_en = 0; - cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), - port_cfg.u64); - } - } - - /* Enables are controlled by the remote host, so nothing to do here */ - return 0; -} diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index 3887cf5f1e84..6b528c39e1a1 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -17,3 +17,17 @@ octeon-ethernet-y += ethernet-rx.o octeon-ethernet-y += ethernet-sgmii.o octeon-ethernet-y += ethernet-spi.o octeon-ethernet-y += ethernet-tx.o +octeon-ethernet-y += cvmx-pko.o +octeon-ethernet-y += cvmx-helper.o +octeon-ethernet-y += cvmx-helper-board.o +octeon-ethernet-y += cvmx-helper-jtag.o +octeon-ethernet-y += cvmx-helper-util.o +octeon-ethernet-y += cvmx-helper-rgmii.o +octeon-ethernet-y += cvmx-helper-sgmii.o +octeon-ethernet-y += cvmx-helper-xaui.o +octeon-ethernet-y += cvmx-helper-spi.o +octeon-ethernet-y += cvmx-helper-npi.o +octeon-ethernet-y += cvmx-helper-loop.o +octeon-ethernet-y += cvmx-helper-errata.o +octeon-ethernet-y += cvmx-cmd-queue.o +octeon-ethernet-y += cvmx-spi.o diff --git a/drivers/staging/octeon/cvmx-address.h b/drivers/staging/octeon/cvmx-address.h new file mode 100644 index 000000000000..847d4dbfff39 --- /dev/null +++ b/drivers/staging/octeon/cvmx-address.h @@ -0,0 +1,339 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2009 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * Typedefs and defines for working with Octeon physical addresses. + * + */ +#ifndef __CVMX_ADDRESS_H__ +#define __CVMX_ADDRESS_H__ + +#if 0 +typedef enum { + CVMX_MIPS_SPACE_XKSEG = 3LL, + CVMX_MIPS_SPACE_XKPHYS = 2LL, + CVMX_MIPS_SPACE_XSSEG = 1LL, + CVMX_MIPS_SPACE_XUSEG = 0LL +} cvmx_mips_space_t; +#endif + +typedef enum { + CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, + CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, + CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, + CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL +} cvmx_mips_xkseg_space_t; + +/* decodes <14:13> of a kseg3 window address */ +typedef enum { + CVMX_ADD_WIN_SCR = 0L, + /* see cvmx_add_win_dma_dec_t for further decode */ + CVMX_ADD_WIN_DMA = 1L, + CVMX_ADD_WIN_UNUSED = 2L, + CVMX_ADD_WIN_UNUSED2 = 3L +} cvmx_add_win_dec_t; + +/* decode within DMA space */ +typedef enum { + /* + * Add store data to the write buffer entry, allocating it if + * necessary. + */ + CVMX_ADD_WIN_DMA_ADD = 0L, + /* send out the write buffer entry to DRAM */ + CVMX_ADD_WIN_DMA_SENDMEM = 1L, + /* store data must be normal DRAM memory space address in this case */ + /* send out the write buffer entry as an IOBDMA command */ + CVMX_ADD_WIN_DMA_SENDDMA = 2L, + /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ + /* send out the write buffer entry as an IO write */ + CVMX_ADD_WIN_DMA_SENDIO = 3L, + /* store data must be normal IO space address in this case */ + /* send out a single-tick command on the NCB bus */ + CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, + /* no write buffer data needed/used */ +} cvmx_add_win_dma_dec_t; + +/* + * Physical Address Decode + * + * Octeon-I HW never interprets this X (<39:36> reserved + * for future expansion), software should set to 0. + * + * - 0x0 XXX0 0000 0000 to DRAM Cached + * - 0x0 XXX0 0FFF FFFF + * + * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 + * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) + * + * - 0x0 XXX0 2000 0000 to DRAM Cached + * - 0x0 XXXF FFFF FFFF + * + * - 0x1 00X0 0000 0000 to Boot Bus Uncached + * - 0x1 00XF FFFF FFFF + * + * - 0x1 01X0 0000 0000 to Other NCB Uncached + * - 0x1 FFXF FFFF FFFF devices + * + * Decode of all Octeon addresses + */ +typedef union { + u64 u64; +#ifdef __BIG_ENDIAN_BITFIELD + /* mapped or unmapped virtual address */ + struct { + u64 R:2; + u64 offset:62; + } sva; + + /* mapped USEG virtual addresses (typically) */ + struct { + u64 zeroes:33; + u64 offset:31; + } suseg; + + /* mapped or unmapped virtual address */ + struct { + u64 ones:33; + u64 sp:2; + u64 offset:29; + } sxkseg; + + /* + * physical address accessed through xkphys unmapped virtual + * address. + */ + struct { + u64 R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ + u64 cca:3; /* ignored by octeon */ + u64 mbz:10; + u64 pa:49; /* physical address */ + } sxkphys; + + /* physical address */ + struct { + u64 mbz:15; + /* if set, the address is uncached and resides on MCB bus */ + u64 is_io:1; + /* + * the hardware ignores this field when is_io==0, else + * device ID. + */ + u64 did:8; + /* the hardware ignores <39:36> in Octeon I */ + u64 unaddr:4; + u64 offset:36; + } sphys; + + /* physical mem address */ + struct { + /* technically, <47:40> are dont-cares */ + u64 zeroes:24; + /* the hardware ignores <39:36> in Octeon I */ + u64 unaddr:4; + u64 offset:36; + } smem; + + /* physical IO address */ + struct { + u64 mem_region:2; + u64 mbz:13; + /* 1 in this case */ + u64 is_io:1; + /* + * The hardware ignores this field when is_io==0, else + * device ID. + */ + u64 did:8; + /* the hardware ignores <39:36> in Octeon I */ + u64 unaddr:4; + u64 offset:36; + } sio; + + /* + * Scratchpad virtual address - accessed through a window at + * the end of kseg3 + */ + struct { + u64 ones:49; + /* CVMX_ADD_WIN_SCR (0) in this case */ + cvmx_add_win_dec_t csrdec:2; + u64 addr:13; + } sscr; + + /* there should only be stores to IOBDMA space, no loads */ + /* + * IOBDMA virtual address - accessed through a window at the + * end of kseg3 + */ + struct { + u64 ones:49; + u64 csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ + u64 unused2:3; + u64 type:3; + u64 addr:7; + } sdma; + + struct { + u64 didspace:24; + u64 unused:40; + } sfilldidspace; +#else + struct { + u64 offset:62; + u64 R:2; + } sva; + + struct { + u64 offset:31; + u64 zeroes:33; + } suseg; + + struct { + u64 offset:29; + u64 sp:2; + u64 ones:33; + } sxkseg; + + struct { + u64 pa:49; + u64 mbz:10; + u64 cca:3; + u64 R:2; + } sxkphys; + + struct { + u64 offset:36; + u64 unaddr:4; + u64 did:8; + u64 is_io:1; + u64 mbz:15; + } sphys; + + struct { + u64 offset:36; + u64 unaddr:4; + u64 zeroes:24; + } smem; + + struct { + u64 offset:36; + u64 unaddr:4; + u64 did:8; + u64 is_io:1; + u64 mbz:13; + u64 mem_region:2; + } sio; + + struct { + u64 addr:13; + cvmx_add_win_dec_t csrdec:2; + u64 ones:49; + } sscr; + + struct { + u64 addr:7; + u64 type:3; + u64 unused2:3; + u64 csrdec:2; + u64 ones:49; + } sdma; + + struct { + u64 unused:40; + u64 didspace:24; + } sfilldidspace; +#endif + +} cvmx_addr_t; + +/* These macros for used by 32 bit applications */ + +#define CVMX_MIPS32_SPACE_KSEG0 1l +#define CVMX_ADD_SEG32(segment, add) \ + (((int32_t)segment << 31) | (int32_t)(add)) + +/* + * Currently all IOs are performed using XKPHYS addressing. Linux uses + * the CvmMemCtl register to enable XKPHYS addressing to IO space from + * user mode. Future OSes may need to change the upper bits of IO + * addresses. The following define controls the upper two bits for all + * IO addresses generated by the simple executive library. + */ +#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS + +/* These macros simplify the process of creating common IO addresses */ +#define CVMX_ADD_SEG(segment, add) ((((u64)segment) << 62) | (add)) +#ifndef CVMX_ADD_IO_SEG +#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) +#endif +#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) +#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) +#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) + + /* from include/ncb_rsl_id.v */ +#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ +#define CVMX_OCT_DID_GMX0 1ULL +#define CVMX_OCT_DID_GMX1 2ULL +#define CVMX_OCT_DID_PCI 3ULL +#define CVMX_OCT_DID_KEY 4ULL +#define CVMX_OCT_DID_FPA 5ULL +#define CVMX_OCT_DID_DFA 6ULL +#define CVMX_OCT_DID_ZIP 7ULL +#define CVMX_OCT_DID_RNG 8ULL +#define CVMX_OCT_DID_IPD 9ULL +#define CVMX_OCT_DID_PKT 10ULL +#define CVMX_OCT_DID_TIM 11ULL +#define CVMX_OCT_DID_TAG 12ULL + /* the rest are not on the IO bus */ +#define CVMX_OCT_DID_L2C 16ULL +#define CVMX_OCT_DID_LMC 17ULL +#define CVMX_OCT_DID_SPX0 18ULL +#define CVMX_OCT_DID_SPX1 19ULL +#define CVMX_OCT_DID_PIP 20ULL +#define CVMX_OCT_DID_ASX0 22ULL +#define CVMX_OCT_DID_ASX1 23ULL +#define CVMX_OCT_DID_IOB 30ULL + +#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) +#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) +#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) +#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) +#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) +#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) +#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) +#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) +#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) +#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) +#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) +#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) +#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) +#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) +#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) +#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) +#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) + +#endif /* __CVMX_ADDRESS_H__ */ diff --git a/drivers/staging/octeon/cvmx-agl-defs.h b/drivers/staging/octeon/cvmx-agl-defs.h new file mode 100644 index 000000000000..52e6e135533c --- /dev/null +++ b/drivers/staging/octeon/cvmx-agl-defs.h @@ -0,0 +1,1758 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_AGL_DEFS_H__ +#define __CVMX_AGL_DEFS_H__ + +#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull)) +#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull)) +#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull)) +#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull)) +#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull)) +#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull)) +#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull)) +#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull)) +#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull)) +#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull)) +#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull)) +#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull)) +#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull)) +#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull)) +#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull)) +#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull)) +#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull)) +#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8) + +union cvmx_agl_gmx_bad_reg { + u64 u64; + struct cvmx_agl_gmx_bad_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 txpsh1:1; + u64 txpop1:1; + u64 ovrflw1:1; + u64 txpsh:1; + u64 txpop:1; + u64 ovrflw:1; + u64 reserved_27_31:5; + u64 statovr:1; + u64 reserved_24_25:2; + u64 loststat:2; + u64 reserved_4_21:18; + u64 out_ovr:2; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 out_ovr:2; + u64 reserved_4_21:18; + u64 loststat:2; + u64 reserved_24_25:2; + u64 statovr:1; + u64 reserved_27_31:5; + u64 ovrflw:1; + u64 txpop:1; + u64 txpsh:1; + u64 ovrflw1:1; + u64 txpop1:1; + u64 txpsh1:1; + u64 reserved_38_63:26; +#endif + } s; + struct cvmx_agl_gmx_bad_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 txpsh1:1; + u64 txpop1:1; + u64 ovrflw1:1; + u64 txpsh:1; + u64 txpop:1; + u64 ovrflw:1; + u64 reserved_27_31:5; + u64 statovr:1; + u64 reserved_23_25:3; + u64 loststat:1; + u64 reserved_4_21:18; + u64 out_ovr:2; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 out_ovr:2; + u64 reserved_4_21:18; + u64 loststat:1; + u64 reserved_23_25:3; + u64 statovr:1; + u64 reserved_27_31:5; + u64 ovrflw:1; + u64 txpop:1; + u64 txpsh:1; + u64 ovrflw1:1; + u64 txpop1:1; + u64 txpsh1:1; + u64 reserved_38_63:26; +#endif + } cn52xx; + struct cvmx_agl_gmx_bad_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 txpsh:1; + u64 txpop:1; + u64 ovrflw:1; + u64 reserved_27_31:5; + u64 statovr:1; + u64 reserved_23_25:3; + u64 loststat:1; + u64 reserved_3_21:19; + u64 out_ovr:1; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 out_ovr:1; + u64 reserved_3_21:19; + u64 loststat:1; + u64 reserved_23_25:3; + u64 statovr:1; + u64 reserved_27_31:5; + u64 ovrflw:1; + u64 txpop:1; + u64 txpsh:1; + u64 reserved_35_63:29; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_bist { + u64 u64; + struct cvmx_agl_gmx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 status:25; +#else + u64 status:25; + u64 reserved_25_63:39; +#endif + } s; + struct cvmx_agl_gmx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 status:10; +#else + u64 status:10; + u64 reserved_10_63:54; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_drv_ctl { + u64 u64; + struct cvmx_agl_gmx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 byp_en1:1; + u64 reserved_45_47:3; + u64 pctl1:5; + u64 reserved_37_39:3; + u64 nctl1:5; + u64 reserved_17_31:15; + u64 byp_en:1; + u64 reserved_13_15:3; + u64 pctl:5; + u64 reserved_5_7:3; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_7:3; + u64 pctl:5; + u64 reserved_13_15:3; + u64 byp_en:1; + u64 reserved_17_31:15; + u64 nctl1:5; + u64 reserved_37_39:3; + u64 pctl1:5; + u64 reserved_45_47:3; + u64 byp_en1:1; + u64 reserved_49_63:15; +#endif + } s; + struct cvmx_agl_gmx_drv_ctl_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 byp_en:1; + u64 reserved_13_15:3; + u64 pctl:5; + u64 reserved_5_7:3; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_7:3; + u64 pctl:5; + u64 reserved_13_15:3; + u64 byp_en:1; + u64 reserved_17_63:47; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_inf_mode { + u64 u64; + struct cvmx_agl_gmx_inf_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 en:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 en:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_agl_gmx_prtx_cfg { + u64 u64; + struct cvmx_agl_gmx_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 tx_idle:1; + u64 rx_idle:1; + u64 reserved_9_11:3; + u64 speed_msb:1; + u64 reserved_7_7:1; + u64 burst:1; + u64 tx_en:1; + u64 rx_en:1; + u64 slottime:1; + u64 duplex:1; + u64 speed:1; + u64 en:1; +#else + u64 en:1; + u64 speed:1; + u64 duplex:1; + u64 slottime:1; + u64 rx_en:1; + u64 tx_en:1; + u64 burst:1; + u64 reserved_7_7:1; + u64 speed_msb:1; + u64 reserved_9_11:3; + u64 rx_idle:1; + u64 tx_idle:1; + u64 reserved_14_63:50; +#endif + } s; + struct cvmx_agl_gmx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 tx_en:1; + u64 rx_en:1; + u64 slottime:1; + u64 duplex:1; + u64 speed:1; + u64 en:1; +#else + u64 en:1; + u64 speed:1; + u64 duplex:1; + u64 slottime:1; + u64 rx_en:1; + u64 tx_en:1; + u64 reserved_6_63:58; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_rxx_adr_cam0 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam1 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam2 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam3 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam4 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam4_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam5 { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam5_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 adr:64; +#else + u64 adr:64; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_cam_en { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_cam_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 en:8; +#else + u64 en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_adr_ctl { + u64 u64; + struct cvmx_agl_gmx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 cam_mode:1; + u64 mcst:2; + u64 bcst:1; +#else + u64 bcst:1; + u64 mcst:2; + u64 cam_mode:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_decision { + u64 u64; + struct cvmx_agl_gmx_rxx_decision_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 cnt:5; +#else + u64 cnt:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_frm_chk { + u64 u64; + struct cvmx_agl_gmx_rxx_frm_chk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_agl_gmx_rxx_frm_chk_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 reserved_1_1:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 reserved_1_1:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_63:55; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_rxx_frm_ctl { + u64 u64; + struct cvmx_agl_gmx_rxx_frm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 ptp_mode:1; + u64 reserved_11_11:1; + u64 null_dis:1; + u64 pre_align:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 pre_align:1; + u64 null_dis:1; + u64 reserved_11_11:1; + u64 ptp_mode:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pre_align:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 pre_align:1; + u64 reserved_10_63:54; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_rxx_frm_max { + u64 u64; + struct cvmx_agl_gmx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 len:16; +#else + u64 len:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_frm_min { + u64 u64; + struct cvmx_agl_gmx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 len:16; +#else + u64 len:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_ifg { + u64 u64; + struct cvmx_agl_gmx_rxx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 ifg:4; +#else + u64 ifg:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_int_en { + u64 u64; + struct cvmx_agl_gmx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_agl_gmx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 reserved_1_1:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 reserved_1_1:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_rxx_int_reg { + u64 u64; + struct cvmx_agl_gmx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_agl_gmx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 reserved_1_1:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 reserved_1_1:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn52xx; +}; + +union cvmx_agl_gmx_rxx_jabber { + u64 u64; + struct cvmx_agl_gmx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt:16; +#else + u64 cnt:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_pause_drop_time { + u64 u64; + struct cvmx_agl_gmx_rxx_pause_drop_time_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 status:16; +#else + u64 status:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_rx_inbnd { + u64 u64; + struct cvmx_agl_gmx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 duplex:1; + u64 speed:2; + u64 status:1; +#else + u64 status:1; + u64 speed:2; + u64 duplex:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_ctl { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 rd_clr:1; +#else + u64 rd_clr:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_octs { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_octs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 cnt:48; +#else + u64 cnt:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_octs_ctl { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 cnt:48; +#else + u64 cnt:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_octs_dmac { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 cnt:48; +#else + u64 cnt:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_octs_drp { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 cnt:48; +#else + u64 cnt:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_pkts { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_pkts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_bad { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_ctl { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_dmac { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_drp { + u64 u64; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_rxx_udd_skp { + u64 u64; + struct cvmx_agl_gmx_rxx_udd_skp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 fcssel:1; + u64 reserved_7_7:1; + u64 len:7; +#else + u64 len:7; + u64 reserved_7_7:1; + u64 fcssel:1; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_agl_gmx_rx_bp_dropx { + u64 u64; + struct cvmx_agl_gmx_rx_bp_dropx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 mark:6; +#else + u64 mark:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_agl_gmx_rx_bp_offx { + u64 u64; + struct cvmx_agl_gmx_rx_bp_offx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 mark:6; +#else + u64 mark:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_agl_gmx_rx_bp_onx { + u64 u64; + struct cvmx_agl_gmx_rx_bp_onx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 mark:9; +#else + u64 mark:9; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_agl_gmx_rx_prt_info { + u64 u64; + struct cvmx_agl_gmx_rx_prt_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 drop:2; + u64 reserved_2_15:14; + u64 commit:2; +#else + u64 commit:2; + u64 reserved_2_15:14; + u64 drop:2; + u64 reserved_18_63:46; +#endif + } s; + struct cvmx_agl_gmx_rx_prt_info_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 drop:1; + u64 reserved_1_15:15; + u64 commit:1; +#else + u64 commit:1; + u64 reserved_1_15:15; + u64 drop:1; + u64 reserved_17_63:47; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_rx_tx_status { + u64 u64; + struct cvmx_agl_gmx_rx_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 tx:2; + u64 reserved_2_3:2; + u64 rx:2; +#else + u64 rx:2; + u64 reserved_2_3:2; + u64 tx:2; + u64 reserved_6_63:58; +#endif + } s; + struct cvmx_agl_gmx_rx_tx_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 tx:1; + u64 reserved_1_3:3; + u64 rx:1; +#else + u64 rx:1; + u64 reserved_1_3:3; + u64 tx:1; + u64 reserved_5_63:59; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_smacx { + u64 u64; + struct cvmx_agl_gmx_smacx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 smac:48; +#else + u64 smac:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_stat_bp { + u64 u64; + struct cvmx_agl_gmx_stat_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 bp:1; + u64 cnt:16; +#else + u64 cnt:16; + u64 bp:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_append { + u64 u64; + struct cvmx_agl_gmx_txx_append_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 force_fcs:1; + u64 fcs:1; + u64 pad:1; + u64 preamble:1; +#else + u64 preamble:1; + u64 pad:1; + u64 fcs:1; + u64 force_fcs:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_clk { + u64 u64; + struct cvmx_agl_gmx_txx_clk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 clk_cnt:6; +#else + u64 clk_cnt:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_ctl { + u64 u64; + struct cvmx_agl_gmx_txx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 xsdef_en:1; + u64 xscol_en:1; +#else + u64 xscol_en:1; + u64 xsdef_en:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_min_pkt { + u64 u64; + struct cvmx_agl_gmx_txx_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 min_size:8; +#else + u64 min_size:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_pause_pkt_interval { + u64 u64; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 interval:16; +#else + u64 interval:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_pause_pkt_time { + u64 u64; + struct cvmx_agl_gmx_txx_pause_pkt_time_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 time:16; +#else + u64 time:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_pause_togo { + u64 u64; + struct cvmx_agl_gmx_txx_pause_togo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 time:16; +#else + u64 time:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_pause_zero { + u64 u64; + struct cvmx_agl_gmx_txx_pause_zero_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 send:1; +#else + u64 send:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_soft_pause { + u64 u64; + struct cvmx_agl_gmx_txx_soft_pause_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 time:16; +#else + u64 time:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat0 { + u64 u64; + struct cvmx_agl_gmx_txx_stat0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 xsdef:32; + u64 xscol:32; +#else + u64 xscol:32; + u64 xsdef:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat1 { + u64 u64; + struct cvmx_agl_gmx_txx_stat1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 scol:32; + u64 mcol:32; +#else + u64 mcol:32; + u64 scol:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat2 { + u64 u64; + struct cvmx_agl_gmx_txx_stat2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat3 { + u64 u64; + struct cvmx_agl_gmx_txx_stat3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pkts:32; +#else + u64 pkts:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat4 { + u64 u64; + struct cvmx_agl_gmx_txx_stat4_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 hist1:32; + u64 hist0:32; +#else + u64 hist0:32; + u64 hist1:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat5 { + u64 u64; + struct cvmx_agl_gmx_txx_stat5_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 hist3:32; + u64 hist2:32; +#else + u64 hist2:32; + u64 hist3:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat6 { + u64 u64; + struct cvmx_agl_gmx_txx_stat6_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 hist5:32; + u64 hist4:32; +#else + u64 hist4:32; + u64 hist5:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat7 { + u64 u64; + struct cvmx_agl_gmx_txx_stat7_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 hist7:32; + u64 hist6:32; +#else + u64 hist6:32; + u64 hist7:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat8 { + u64 u64; + struct cvmx_agl_gmx_txx_stat8_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mcst:32; + u64 bcst:32; +#else + u64 bcst:32; + u64 mcst:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stat9 { + u64 u64; + struct cvmx_agl_gmx_txx_stat9_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 undflw:32; + u64 ctl:32; +#else + u64 ctl:32; + u64 undflw:32; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_stats_ctl { + u64 u64; + struct cvmx_agl_gmx_txx_stats_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 rd_clr:1; +#else + u64 rd_clr:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_agl_gmx_txx_thresh { + u64 u64; + struct cvmx_agl_gmx_txx_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 cnt:6; +#else + u64 cnt:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_bp { + u64 u64; + struct cvmx_agl_gmx_tx_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 bp:2; +#else + u64 bp:2; + u64 reserved_2_63:62; +#endif + } s; + struct cvmx_agl_gmx_tx_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 bp:1; +#else + u64 bp:1; + u64 reserved_1_63:63; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_tx_col_attempt { + u64 u64; + struct cvmx_agl_gmx_tx_col_attempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 limit:5; +#else + u64 limit:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_ifg { + u64 u64; + struct cvmx_agl_gmx_tx_ifg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ifg2:4; + u64 ifg1:4; +#else + u64 ifg1:4; + u64 ifg2:4; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_int_en { + u64 u64; + struct cvmx_agl_gmx_tx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 ptp_lost:2; + u64 reserved_18_19:2; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_19:2; + u64 ptp_lost:2; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_agl_gmx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_63:46; +#endif + } cn52xx; + struct cvmx_agl_gmx_tx_int_en_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 late_col:1; + u64 reserved_13_15:3; + u64 xsdef:1; + u64 reserved_9_11:3; + u64 xscol:1; + u64 reserved_3_7:5; + u64 undflw:1; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:1; + u64 reserved_3_7:5; + u64 xscol:1; + u64 reserved_9_11:3; + u64 xsdef:1; + u64 reserved_13_15:3; + u64 late_col:1; + u64 reserved_17_63:47; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_tx_int_reg { + u64 u64; + struct cvmx_agl_gmx_tx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 ptp_lost:2; + u64 reserved_18_19:2; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_19:2; + u64 ptp_lost:2; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_agl_gmx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_63:46; +#endif + } cn52xx; + struct cvmx_agl_gmx_tx_int_reg_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 late_col:1; + u64 reserved_13_15:3; + u64 xsdef:1; + u64 reserved_9_11:3; + u64 xscol:1; + u64 reserved_3_7:5; + u64 undflw:1; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:1; + u64 reserved_3_7:5; + u64 xscol:1; + u64 reserved_9_11:3; + u64 xsdef:1; + u64 reserved_13_15:3; + u64 late_col:1; + u64 reserved_17_63:47; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_tx_jam { + u64 u64; + struct cvmx_agl_gmx_tx_jam_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 jam:8; +#else + u64 jam:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_lfsr { + u64 u64; + struct cvmx_agl_gmx_tx_lfsr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 lfsr:16; +#else + u64 lfsr:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_ovr_bp { + u64 u64; + struct cvmx_agl_gmx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 en:2; + u64 reserved_6_7:2; + u64 bp:2; + u64 reserved_2_3:2; + u64 ign_full:2; +#else + u64 ign_full:2; + u64 reserved_2_3:2; + u64 bp:2; + u64 reserved_6_7:2; + u64 en:2; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 en:1; + u64 reserved_5_7:3; + u64 bp:1; + u64 reserved_1_3:3; + u64 ign_full:1; +#else + u64 ign_full:1; + u64 reserved_1_3:3; + u64 bp:1; + u64 reserved_5_7:3; + u64 en:1; + u64 reserved_9_63:55; +#endif + } cn56xx; +}; + +union cvmx_agl_gmx_tx_pause_pkt_dmac { + u64 u64; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 dmac:48; +#else + u64 dmac:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_agl_gmx_tx_pause_pkt_type { + u64 u64; + struct cvmx_agl_gmx_tx_pause_pkt_type_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 type:16; +#else + u64 type:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_agl_prtx_ctl { + u64 u64; + struct cvmx_agl_prtx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 drv_byp:1; + u64 reserved_62_62:1; + u64 cmp_pctl:6; + u64 reserved_54_55:2; + u64 cmp_nctl:6; + u64 reserved_46_47:2; + u64 drv_pctl:6; + u64 reserved_38_39:2; + u64 drv_nctl:6; + u64 reserved_29_31:3; + u64 clk_set:5; + u64 clkrx_byp:1; + u64 reserved_21_22:2; + u64 clkrx_set:5; + u64 clktx_byp:1; + u64 reserved_13_14:2; + u64 clktx_set:5; + u64 reserved_5_7:3; + u64 dllrst:1; + u64 comp:1; + u64 enable:1; + u64 clkrst:1; + u64 mode:1; +#else + u64 mode:1; + u64 clkrst:1; + u64 enable:1; + u64 comp:1; + u64 dllrst:1; + u64 reserved_5_7:3; + u64 clktx_set:5; + u64 reserved_13_14:2; + u64 clktx_byp:1; + u64 clkrx_set:5; + u64 reserved_21_22:2; + u64 clkrx_byp:1; + u64 clk_set:5; + u64 reserved_29_31:3; + u64 drv_nctl:6; + u64 reserved_38_39:2; + u64 drv_pctl:6; + u64 reserved_46_47:2; + u64 cmp_nctl:6; + u64 reserved_54_55:2; + u64 cmp_pctl:6; + u64 reserved_62_62:1; + u64 drv_byp:1; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-asm.h b/drivers/staging/octeon/cvmx-asm.h new file mode 100644 index 000000000000..2532232592bc --- /dev/null +++ b/drivers/staging/octeon/cvmx-asm.h @@ -0,0 +1,138 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * This is file defines ASM primitives for the executive. + */ +#ifndef __CVMX_ASM_H__ +#define __CVMX_ASM_H__ + +#include "octeon-model.h" + +/* other useful stuff */ +#define CVMX_SYNC asm volatile ("sync" : : : "memory") +/* String version of SYNCW macro for using in inline asm constructs */ +#define CVMX_SYNCW_STR "syncw\nsyncw\n" +#ifdef __OCTEON__ + +/* Deprecated, will be removed in future release */ +#define CVMX_SYNCIO asm volatile ("nop") + +#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory") + +/* Deprecated, will be removed in future release */ +#define CVMX_SYNCIOALL asm volatile ("nop") + +/* + * We actually use two syncw instructions in a row when we need a write + * memory barrier. This is because the CN3XXX series of Octeons have + * errata Core-401. This can cause a single syncw to not enforce + * ordering under very rare conditions. Even if it is rare, better safe + * than sorry. + */ +#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory") + +/* + * Define new sync instructions to be normal SYNC instructions for + * operating systems that use threads. + */ +#define CVMX_SYNCWS CVMX_SYNCW +#define CVMX_SYNCS CVMX_SYNC +#define CVMX_SYNCWS_STR CVMX_SYNCW_STR +#else +/* + * Not using a Cavium compiler, always use the slower sync so the + * assembler stays happy. + */ +/* Deprecated, will be removed in future release */ +#define CVMX_SYNCIO asm volatile ("nop") + +#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory") + +/* Deprecated, will be removed in future release */ +#define CVMX_SYNCIOALL asm volatile ("nop") + +#define CVMX_SYNCW asm volatile ("sync" : : : "memory") +#define CVMX_SYNCWS CVMX_SYNCW +#define CVMX_SYNCS CVMX_SYNC +#define CVMX_SYNCWS_STR CVMX_SYNCW_STR +#endif + +/* + * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable + * (actually old value or zero) until that byte is stored to (by this or + * another processor. Note that the value of each byte is not only + * unpredictable, but may also change again - up until the point when one + * of the cores stores to the byte. + */ +#define CVMX_PREPARE_FOR_STORE(address, offset) \ + asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ + [rbase] "d" (address)) +/* + * This is a command headed to the L2 controller to tell it to clear + * its dirty bit for a block. Basically, SW is telling HW that the + * current version of the block will not be used. + */ +#define CVMX_DONT_WRITE_BACK(address, offset) \ + asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ + [rbase] "d" (address)) + +/* flush stores, invalidate entire icache */ +#define CVMX_ICACHE_INVALIDATE \ + { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } + +/* flush stores, invalidate entire icache */ +#define CVMX_ICACHE_INVALIDATE2 \ + { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } + +/* complete prefetches, invalidate entire dcache */ +#define CVMX_DCACHE_INVALIDATE \ + { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } + +#define CVMX_CACHE(op, address, offset) \ + asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \ + : : [rbase] "d" (address)) +/* fetch and lock the state. */ +#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) +/* unlock the state. */ +#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) +/* invalidate the cache block and clear the USED bits for the block */ +#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) +/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */ +#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) + +#define CVMX_POP(result, input) \ + asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) +#define CVMX_DPOP(result, input) \ + asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) + +/* some new cop0-like stuff */ +#define CVMX_RDHWR(result, regstr) \ + asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) +#define CVMX_RDHWRNV(result, regstr) \ + asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) +#endif /* __CVMX_ASM_H__ */ diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/drivers/staging/octeon/cvmx-asxx-defs.h new file mode 100644 index 000000000000..022c604cb617 --- /dev/null +++ b/drivers/staging/octeon/cvmx-asxx-defs.h @@ -0,0 +1,565 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_ASXX_DEFS_H__ +#define __CVMX_ASXX_DEFS_H__ + +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) +#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) + +void __cvmx_interrupt_asxx_enable(int block); + +union cvmx_asxx_gmii_rx_clk_set { + u64 u64; + struct cvmx_asxx_gmii_rx_clk_set_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_gmii_rx_dat_set { + u64 u64; + struct cvmx_asxx_gmii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_int_en { + u64 u64; + struct cvmx_asxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 txpsh:4; + u64 txpop:4; + u64 ovrflw:4; +#else + u64 ovrflw:4; + u64 txpop:4; + u64 txpsh:4; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_asxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 txpsh:3; + u64 reserved_7_7:1; + u64 txpop:3; + u64 reserved_3_3:1; + u64 ovrflw:3; +#else + u64 ovrflw:3; + u64 reserved_3_3:1; + u64 txpop:3; + u64 reserved_7_7:1; + u64 txpsh:3; + u64 reserved_11_63:53; +#endif + } cn30xx; +}; + +union cvmx_asxx_int_reg { + u64 u64; + struct cvmx_asxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 txpsh:4; + u64 txpop:4; + u64 ovrflw:4; +#else + u64 ovrflw:4; + u64 txpop:4; + u64 txpsh:4; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_asxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 txpsh:3; + u64 reserved_7_7:1; + u64 txpop:3; + u64 reserved_3_3:1; + u64 ovrflw:3; +#else + u64 ovrflw:3; + u64 reserved_3_3:1; + u64 txpop:3; + u64 reserved_7_7:1; + u64 txpsh:3; + u64 reserved_11_63:53; +#endif + } cn30xx; +}; + +union cvmx_asxx_mii_rx_dat_set { + u64 u64; + struct cvmx_asxx_mii_rx_dat_set_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_prt_loop { + u64 u64; + struct cvmx_asxx_prt_loop_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ext_loop:4; + u64 int_loop:4; +#else + u64 int_loop:4; + u64 ext_loop:4; + u64 reserved_8_63:56; +#endif + } s; + struct cvmx_asxx_prt_loop_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 ext_loop:3; + u64 reserved_3_3:1; + u64 int_loop:3; +#else + u64 int_loop:3; + u64 reserved_3_3:1; + u64 ext_loop:3; + u64 reserved_7_63:57; +#endif + } cn30xx; +}; + +union cvmx_asxx_rld_bypass { + u64 u64; + struct cvmx_asxx_rld_bypass_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 bypass:1; +#else + u64 bypass:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_asxx_rld_bypass_setting { + u64 u64; + struct cvmx_asxx_rld_bypass_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rld_comp { + u64 u64; + struct cvmx_asxx_rld_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 pctl:5; + u64 nctl:4; +#else + u64 nctl:4; + u64 pctl:5; + u64 reserved_9_63:55; +#endif + } s; + struct cvmx_asxx_rld_comp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 pctl:4; + u64 nctl:4; +#else + u64 nctl:4; + u64 pctl:4; + u64 reserved_8_63:56; +#endif + } cn38xx; +}; + +union cvmx_asxx_rld_data_drv { + u64 u64; + struct cvmx_asxx_rld_data_drv_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 pctl:4; + u64 nctl:4; +#else + u64 nctl:4; + u64 pctl:4; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_asxx_rld_fcram_mode { + u64 u64; + struct cvmx_asxx_rld_fcram_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 mode:1; +#else + u64 mode:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_asxx_rld_nctl_strong { + u64 u64; + struct cvmx_asxx_rld_nctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rld_nctl_weak { + u64 u64; + struct cvmx_asxx_rld_nctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rld_pctl_strong { + u64 u64; + struct cvmx_asxx_rld_pctl_strong_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 pctl:5; +#else + u64 pctl:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rld_pctl_weak { + u64 u64; + struct cvmx_asxx_rld_pctl_weak_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 pctl:5; +#else + u64 pctl:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rld_setting { + u64 u64; + struct cvmx_asxx_rld_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 dfaset:5; + u64 dfalag:1; + u64 dfalead:1; + u64 dfalock:1; + u64 setting:5; +#else + u64 setting:5; + u64 dfalock:1; + u64 dfalead:1; + u64 dfalag:1; + u64 dfaset:5; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_asxx_rld_setting_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } cn38xx; +}; + +union cvmx_asxx_rx_clk_setx { + u64 u64; + struct cvmx_asxx_rx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_rx_prt_en { + u64 u64; + struct cvmx_asxx_rx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 prt_en:4; +#else + u64 prt_en:4; + u64 reserved_4_63:60; +#endif + } s; + struct cvmx_asxx_rx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 prt_en:3; +#else + u64 prt_en:3; + u64 reserved_3_63:61; +#endif + } cn30xx; +}; + +union cvmx_asxx_rx_wol { + u64 u64; + struct cvmx_asxx_rx_wol_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 status:1; + u64 enable:1; +#else + u64 enable:1; + u64 status:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_asxx_rx_wol_msk { + u64 u64; + struct cvmx_asxx_rx_wol_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 msk:64; +#else + u64 msk:64; +#endif + } s; +}; + +union cvmx_asxx_rx_wol_powok { + u64 u64; + struct cvmx_asxx_rx_wol_powok_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 powerok:1; +#else + u64 powerok:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_asxx_rx_wol_sig { + u64 u64; + struct cvmx_asxx_rx_wol_sig_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 sig:32; +#else + u64 sig:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_asxx_tx_clk_setx { + u64 u64; + struct cvmx_asxx_tx_clk_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 setting:5; +#else + u64 setting:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_asxx_tx_comp_byp { + u64 u64; + struct cvmx_asxx_tx_comp_byp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_asxx_tx_comp_byp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 bypass:1; + u64 pctl:4; + u64 nctl:4; +#else + u64 nctl:4; + u64 pctl:4; + u64 bypass:1; + u64 reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_asxx_tx_comp_byp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 pctl:4; + u64 nctl:4; +#else + u64 nctl:4; + u64 pctl:4; + u64 reserved_8_63:56; +#endif + } cn38xx; + struct cvmx_asxx_tx_comp_byp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 bypass:1; + u64 reserved_13_15:3; + u64 pctl:5; + u64 reserved_5_7:3; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_7:3; + u64 pctl:5; + u64 reserved_13_15:3; + u64 bypass:1; + u64 reserved_17_63:47; +#endif + } cn50xx; + struct cvmx_asxx_tx_comp_byp_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 pctl:5; + u64 reserved_5_7:3; + u64 nctl:5; +#else + u64 nctl:5; + u64 reserved_5_7:3; + u64 pctl:5; + u64 reserved_13_63:51; +#endif + } cn58xx; +}; + +union cvmx_asxx_tx_hi_waterx { + u64 u64; + struct cvmx_asxx_tx_hi_waterx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 mark:4; +#else + u64 mark:4; + u64 reserved_4_63:60; +#endif + } s; + struct cvmx_asxx_tx_hi_waterx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 mark:3; +#else + u64 mark:3; + u64 reserved_3_63:61; +#endif + } cn30xx; +}; + +union cvmx_asxx_tx_prt_en { + u64 u64; + struct cvmx_asxx_tx_prt_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 prt_en:4; +#else + u64 prt_en:4; + u64 reserved_4_63:60; +#endif + } s; + struct cvmx_asxx_tx_prt_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 prt_en:3; +#else + u64 prt_en:3; + u64 reserved_3_63:61; +#endif + } cn30xx; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-bootinfo.h b/drivers/staging/octeon/cvmx-bootinfo.h new file mode 100644 index 000000000000..0443a6bcb863 --- /dev/null +++ b/drivers/staging/octeon/cvmx-bootinfo.h @@ -0,0 +1,427 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Header file containing the ABI with the bootloader. + */ + +#ifndef __CVMX_BOOTINFO_H__ +#define __CVMX_BOOTINFO_H__ + +#include "cvmx-coremask.h" + +/* + * Current major and minor versions of the CVMX bootinfo block that is + * passed from the bootloader to the application. This is versioned + * so that applications can properly handle multiple bootloader + * versions. + */ +#define CVMX_BOOTINFO_MAJ_VER 1 +#define CVMX_BOOTINFO_MIN_VER 4 + +#if (CVMX_BOOTINFO_MAJ_VER == 1) +#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 +/* + * This structure is populated by the bootloader. For binary + * compatibility the only changes that should be made are + * adding members to the end of the structure, and the minor + * version should be incremented at that time. + * If an incompatible change is made, the major version + * must be incremented, and the minor version should be reset + * to 0. + */ +struct cvmx_bootinfo { +#ifdef __BIG_ENDIAN_BITFIELD + u32 major_version; + u32 minor_version; + + u64 stack_top; + u64 heap_base; + u64 heap_end; + u64 desc_vaddr; + + u32 exception_base_addr; + u32 stack_size; + u32 flags; + u32 core_mask; + /* DRAM size in megabytes */ + u32 dram_size; + /* physical address of free memory descriptor block*/ + u32 phy_mem_desc_addr; + /* used to pass flags from app to debugger */ + u32 debugger_flags_base_addr; + + /* CPU clock speed, in hz */ + u32 eclock_hz; + + /* DRAM clock speed, in hz */ + u32 dclock_hz; + + u32 reserved0; + u16 board_type; + u8 board_rev_major; + u8 board_rev_minor; + u16 reserved1; + u8 reserved2; + u8 reserved3; + char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; + u8 mac_addr_base[6]; + u8 mac_addr_count; +#if (CVMX_BOOTINFO_MIN_VER >= 1) + /* + * Several boards support compact flash on the Octeon boot + * bus. The CF memory spaces may be mapped to different + * addresses on different boards. These are the physical + * addresses, so care must be taken to use the correct + * XKPHYS/KSEG0 addressing depending on the application's + * ABI. These values will be 0 if CF is not present. + */ + u64 compact_flash_common_base_addr; + u64 compact_flash_attribute_base_addr; + /* + * Base address of the LED display (as on EBT3000 board) + * This will be 0 if LED display not present. + */ + u64 led_display_base_addr; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 2) + /* DFA reference clock in hz (if applicable)*/ + u32 dfa_ref_clock_hz; + + /* + * flags indicating various configuration options. These + * flags supersede the 'flags' variable and should be used + * instead if available. + */ + u32 config_flags; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 3) + /* + * Address of the OF Flattened Device Tree structure + * describing the board. + */ + u64 fdt_addr; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 4) + /* + * Coremask used for processors with more than 32 cores + * or with OCI. This replaces core_mask. + */ + struct cvmx_coremask ext_core_mask; +#endif +#else /* __BIG_ENDIAN */ + /* + * Little-Endian: When the CPU mode is switched to + * little-endian, the view of the structure has some of the + * fields swapped. + */ + u32 minor_version; + u32 major_version; + + u64 stack_top; + u64 heap_base; + u64 heap_end; + u64 desc_vaddr; + + u32 stack_size; + u32 exception_base_addr; + + u32 core_mask; + u32 flags; + + u32 phy_mem_desc_addr; + u32 dram_size; + + u32 eclock_hz; + u32 debugger_flags_base_addr; + + u32 reserved0; + u32 dclock_hz; + + u8 reserved3; + u8 reserved2; + u16 reserved1; + u8 board_rev_minor; + u8 board_rev_major; + u16 board_type; + + char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; + u8 mac_addr_base[6]; + u8 mac_addr_count; + u8 pad[5]; + +#if (CVMX_BOOTINFO_MIN_VER >= 1) + u64 compact_flash_common_base_addr; + u64 compact_flash_attribute_base_addr; + u64 led_display_base_addr; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 2) + u32 config_flags; + u32 dfa_ref_clock_hz; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 3) + u64 fdt_addr; +#endif +#if (CVMX_BOOTINFO_MIN_VER >= 4) + struct cvmx_coremask ext_core_mask; +#endif +#endif +}; + +#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST BIT_ULL(0) +#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET BIT_ULL(1) +#define CVMX_BOOTINFO_CFG_FLAG_DEBUG BIT_ULL(2) +#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC BIT_ULL(3) +/* This flag is set if the TLB mappings are not contained in the + * 0x10000000 - 0x20000000 boot bus region. */ +#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING BIT_ULL(4) +#define CVMX_BOOTINFO_CFG_FLAG_BREAK BIT_ULL(5) + +#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ + +/* Type defines for board and chip types */ +enum cvmx_board_types_enum { + CVMX_BOARD_TYPE_NULL = 0, + CVMX_BOARD_TYPE_SIM = 1, + CVMX_BOARD_TYPE_EBT3000 = 2, + CVMX_BOARD_TYPE_KODAMA = 3, + CVMX_BOARD_TYPE_NIAGARA = 4, + CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */ + CVMX_BOARD_TYPE_THUNDER = 6, + CVMX_BOARD_TYPE_TRANTOR = 7, + CVMX_BOARD_TYPE_EBH3000 = 8, + CVMX_BOARD_TYPE_EBH3100 = 9, + CVMX_BOARD_TYPE_HIKARI = 10, + CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11, + CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12, + CVMX_BOARD_TYPE_KBP = 13, + /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */ + CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, + CVMX_BOARD_TYPE_EBT5800 = 15, + CVMX_BOARD_TYPE_NICPRO2 = 16, + CVMX_BOARD_TYPE_EBH5600 = 17, + CVMX_BOARD_TYPE_EBH5601 = 18, + CVMX_BOARD_TYPE_EBH5200 = 19, + CVMX_BOARD_TYPE_BBGW_REF = 20, + CVMX_BOARD_TYPE_NIC_XLE_4G = 21, + CVMX_BOARD_TYPE_EBT5600 = 22, + CVMX_BOARD_TYPE_EBH5201 = 23, + CVMX_BOARD_TYPE_EBT5200 = 24, + CVMX_BOARD_TYPE_CB5600 = 25, + CVMX_BOARD_TYPE_CB5601 = 26, + CVMX_BOARD_TYPE_CB5200 = 27, + /* Special 'generic' board type, supports many boards */ + CVMX_BOARD_TYPE_GENERIC = 28, + CVMX_BOARD_TYPE_EBH5610 = 29, + CVMX_BOARD_TYPE_LANAI2_A = 30, + CVMX_BOARD_TYPE_LANAI2_U = 31, + CVMX_BOARD_TYPE_EBB5600 = 32, + CVMX_BOARD_TYPE_EBB6300 = 33, + CVMX_BOARD_TYPE_NIC_XLE_10G = 34, + CVMX_BOARD_TYPE_LANAI2_G = 35, + CVMX_BOARD_TYPE_EBT5810 = 36, + CVMX_BOARD_TYPE_NIC10E = 37, + CVMX_BOARD_TYPE_EP6300C = 38, + CVMX_BOARD_TYPE_EBB6800 = 39, + CVMX_BOARD_TYPE_NIC4E = 40, + CVMX_BOARD_TYPE_NIC2E = 41, + CVMX_BOARD_TYPE_EBB6600 = 42, + CVMX_BOARD_TYPE_REDWING = 43, + CVMX_BOARD_TYPE_NIC68_4 = 44, + CVMX_BOARD_TYPE_NIC10E_66 = 45, + CVMX_BOARD_TYPE_SNIC10E = 50, + CVMX_BOARD_TYPE_MAX, + + /* + * The range from CVMX_BOARD_TYPE_MAX to + * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future + * SDK use. + */ + + /* + * Set aside a range for customer boards. These numbers are managed + * by Cavium. + */ + CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, + CVMX_BOARD_TYPE_CUST_WSX16 = 10001, + CVMX_BOARD_TYPE_CUST_NS0216 = 10002, + CVMX_BOARD_TYPE_CUST_NB5 = 10003, + CVMX_BOARD_TYPE_CUST_WMR500 = 10004, + CVMX_BOARD_TYPE_CUST_ITB101 = 10005, + CVMX_BOARD_TYPE_CUST_NTE102 = 10006, + CVMX_BOARD_TYPE_CUST_AGS103 = 10007, + CVMX_BOARD_TYPE_CUST_GST104 = 10008, + CVMX_BOARD_TYPE_CUST_GCT105 = 10009, + CVMX_BOARD_TYPE_CUST_AGS106 = 10010, + CVMX_BOARD_TYPE_CUST_SGM107 = 10011, + CVMX_BOARD_TYPE_CUST_GCT108 = 10012, + CVMX_BOARD_TYPE_CUST_AGS109 = 10013, + CVMX_BOARD_TYPE_CUST_GCT110 = 10014, + CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015, + CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016, + CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017, + CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018, + CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019, + CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020, + CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021, + CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, + + /* + * Set aside a range for customer private use. The SDK won't + * use any numbers in this range. + */ + CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, + CVMX_BOARD_TYPE_UBNT_E200 = 20003, + CVMX_BOARD_TYPE_UBNT_E220 = 20005, + CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, + CVMX_BOARD_TYPE_UBNT_E300 = 20300, + CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, + CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, + + /* The remaining range is reserved for future use. */ +}; + +enum cvmx_chip_types_enum { + CVMX_CHIP_TYPE_NULL = 0, + CVMX_CHIP_SIM_TYPE_DEPRECATED = 1, + CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2, + CVMX_CHIP_TYPE_MAX, +}; + +/* Compatibility alias for NAC38 name change, planned to be removed + * from SDK 1.7 */ +#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 + +/* Functions to return string based on type */ +#define ENUM_BRD_TYPE_CASE(x) \ + case x: return (&#x[16]); /* Skip CVMX_BOARD_TYPE_ */ +static inline const char *cvmx_board_type_to_string(enum + cvmx_board_types_enum type) +{ + switch (type) { + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SNIC10E) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) + + /* Customer boards listed here */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) + + /* Customer private range */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) + } + return NULL; +} + +#define ENUM_CHIP_TYPE_CASE(x) \ + case x: return (&#x[15]); /* Skip CVMX_CHIP_TYPE */ +static inline const char *cvmx_chip_type_to_string(enum + cvmx_chip_types_enum type) +{ + switch (type) { + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) + ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) + } + return "Unsupported Chip"; +} + +#endif /* __CVMX_BOOTINFO_H__ */ diff --git a/drivers/staging/octeon/cvmx-bootmem.h b/drivers/staging/octeon/cvmx-bootmem.h new file mode 100644 index 000000000000..d11d757769ad --- /dev/null +++ b/drivers/staging/octeon/cvmx-bootmem.h @@ -0,0 +1,339 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Simple allocate only memory allocator. Used to allocate memory at + * application start time. + */ + +#ifndef __CVMX_BOOTMEM_H__ +#define __CVMX_BOOTMEM_H__ +/* Must be multiple of 8, changing breaks ABI */ +#define CVMX_BOOTMEM_NAME_LEN 128 + +/* Can change without breaking ABI */ +#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 + +/* minimum alignment of bootmem alloced blocks */ +#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) + +/* Flags for cvmx_bootmem_phy_mem* functions */ +/* Allocate from end of block instead of beginning */ +#define CVMX_BOOTMEM_FLAG_END_ALLOC BIT(0) + +/* Don't do any locking. */ +#define CVMX_BOOTMEM_FLAG_NO_LOCKING BIT(1) + +/* First bytes of each free physical block of memory contain this structure, + * which is used to maintain the free memory list. Since the bootloader is + * only 32 bits, there is a union providing 64 and 32 bit versions. The + * application init code converts addresses to 64 bit addresses before the + * application starts. + */ +struct cvmx_bootmem_block_header { + /* + * Note: these are referenced from assembly routines in the + * bootloader, so this structure should not be changed + * without changing those routines as well. + */ + u64 next_block_addr; + u64 size; + +}; + +/* + * Structure for named memory blocks. Number of descriptors available + * can be changed without affecting compatibility, but name length + * changes require a bump in the bootmem descriptor version Note: This + * structure must be naturally 64 bit aligned, as a single memory + * image will be used by both 32 and 64 bit programs. + */ +struct cvmx_bootmem_named_block_desc { + /* Base address of named block */ + u64 base_addr; + /* + * Size actually allocated for named block (may differ from + * requested). + */ + u64 size; + /* name of named block */ + char name[CVMX_BOOTMEM_NAME_LEN]; +}; + +/* Current descriptor versions */ +/* CVMX bootmem descriptor major version */ +#define CVMX_BOOTMEM_DESC_MAJ_VER 3 + +/* CVMX bootmem descriptor minor version */ +#define CVMX_BOOTMEM_DESC_MIN_VER 0 + +/* First three members of cvmx_bootmem_desc_t are left in original + * positions for backwards compatibility. + */ +struct cvmx_bootmem_desc { +#if defined(__BIG_ENDIAN_BITFIELD) || defined(CVMX_BUILD_FOR_LINUX_HOST) + /* spinlock to control access to list */ + u32 lock; + /* flags for indicating various conditions */ + u32 flags; + u64 head_addr; + + /* Incremented when incompatible changes made */ + u32 major_version; + + /* + * Incremented changed when compatible changes made, reset to + * zero when major incremented. + */ + u32 minor_version; + + u64 app_data_addr; + u64 app_data_size; + + /* number of elements in named blocks array */ + u32 named_block_num_blocks; + + /* length of name array in bootmem blocks */ + u32 named_block_name_len; + /* address of named memory block descriptors */ + u64 named_block_array_addr; +#else /* __LITTLE_ENDIAN */ + u32 flags; + u32 lock; + u64 head_addr; + + u32 minor_version; + u32 major_version; + u64 app_data_addr; + u64 app_data_size; + + u32 named_block_name_len; + u32 named_block_num_blocks; + u64 named_block_array_addr; +#endif +}; + +/** + * Initialize the boot alloc memory structures. This is + * normally called inside of cvmx_user_app_init() + * + * @mem_desc_ptr: Address of the free memory list + */ +int cvmx_bootmem_init(void *mem_desc_ptr); + +/** + * Allocate a block of memory from the free list that was + * passed to the application by the bootloader at a specific + * address. This is an allocate-only algorithm, so + * freeing memory is not possible. Allocation will fail if + * memory cannot be allocated at the specified address. + * + * @size: Size in bytes of block to allocate + * @address: Physical address to allocate memory at. If this memory is not + * available, the allocation fails. + * @alignment: Alignment required - must be power of 2 + * Returns pointer to block of memory, NULL on error + */ +void *cvmx_bootmem_alloc_address(u64 size, u64 address, + u64 alignment); + +/** + * Frees a previously allocated named bootmem block. + * + * @name: name of block to free + * + * Returns 0 on failure, + * !0 on success + */ + +/** + * Allocate a block of memory from the free list that was passed + * to the application by the bootloader, and assign it a name in the + * global named block table. (part of the cvmx_bootmem_descriptor_t structure) + * Named blocks can later be freed. + * + * @size: Size in bytes of block to allocate + * @alignment: Alignment required - must be power of 2 + * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes + * + * Returns a pointer to block of memory, NULL on error + */ +void *cvmx_bootmem_alloc_named(u64 size, u64 alignment, + char *name); + +/** + * Allocate a block of memory from a specific range of the free list + * that was passed to the application by the bootloader, and assign it + * a name in the global named block table. (part of the + * cvmx_bootmem_descriptor_t structure) Named blocks can later be + * freed. If request cannot be satisfied within the address range + * specified, NULL is returned + * + * @size: Size in bytes of block to allocate + * @min_addr: minimum address of range + * @max_addr: maximum address of range + * @align: Alignment of memory to be allocated. (must be a power of 2) + * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes + * + * Returns a pointer to block of memory, NULL on error + */ +void *cvmx_bootmem_alloc_named_range(u64 size, u64 min_addr, + u64 max_addr, u64 align, + char *name); + +/** + * Allocate if needed a block of memory from a specific range of the + * free list that was passed to the application by the bootloader, and + * assign it a name in the global named block table. (part of the + * cvmx_bootmem_descriptor_t structure) Named blocks can later be + * freed. If the requested name block is already allocated, return + * the pointer to block of memory. If request cannot be satisfied + * within the address range specified, NULL is returned + * + * @param size Size in bytes of block to allocate + * @param min_addr minimum address of range + * @param max_addr maximum address of range + * @param align Alignment of memory to be allocated. (must be a power of 2) + * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes + * @param init Initialization function + * + * The initialization function is optional, if omitted the named block + * is initialized to all zeros when it is created, i.e. once. + * + * @return pointer to block of memory, NULL on error + */ +void *cvmx_bootmem_alloc_named_range_once(u64 size, + u64 min_addr, + u64 max_addr, + u64 align, + char *name, + void (*init)(void *)); + +int cvmx_bootmem_free_named(char *name); + +/** + * Finds a named bootmem block by name. + * + * @name: name of block to free + * + * Returns pointer to named block descriptor on success + * 0 on failure + */ +struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); + +/** + * Allocates a block of physical memory from the free list, at + * (optional) requested address and alignment. + * + * @req_size: size of region to allocate. All requests are rounded up + * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size + * + * @address_min: Minimum address that block can occupy. + * + * @address_max: Specifies the maximum address_min (inclusive) that + * the allocation can use. + * + * @alignment: Requested alignment of the block. If this alignment + * cannot be met, the allocation fails. This must be a + * power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less than + * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * + * @flags: Flags to control options for the allocation. + * + * Returns physical address of block allocated, or -1 on failure + */ +int64_t cvmx_bootmem_phy_alloc(u64 req_size, u64 address_min, + u64 address_max, u64 alignment, + u32 flags); + +/** + * Allocates a named block of physical memory from the free list, at + * (optional) requested address and alignment. + * + * @param size size of region to allocate. All requests are rounded + * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE + * bytes size + * @param min_addr Minimum address that block can occupy. + * @param max_addr Specifies the maximum address_min (inclusive) that + * the allocation can use. + * @param alignment Requested alignment of the block. If this + * alignment cannot be met, the allocation fails. + * This must be a power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less + * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * @param name name to assign to named block + * @param flags Flags to control options for the allocation. + * + * @return physical address of block allocated, or -1 on failure + */ +int64_t cvmx_bootmem_phy_named_block_alloc(u64 size, u64 min_addr, + u64 max_addr, + u64 alignment, + char *name, u32 flags); + +/** + * Frees a block to the bootmem allocator list. This must + * be used with care, as the size provided must match the size + * of the block that was allocated, or the list will become + * corrupted. + * + * IMPORTANT: This is only intended to be used as part of named block + * frees and initial population of the free memory list. + * * + * + * @phy_addr: physical address of block + * @size: size of block in bytes. + * @flags: flags for passing options + * + * Returns 1 on success, + * 0 on failure + */ +int __cvmx_bootmem_phy_free(u64 phy_addr, u64 size, u32 flags); + +/** + * Locks the bootmem allocator. This is useful in certain situations + * where multiple allocations must be made without being interrupted. + * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. + * + */ +void cvmx_bootmem_lock(void); + +/** + * Unlocks the bootmem allocator. This is useful in certain situations + * where multiple allocations must be made without being interrupted. + * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. + * + */ +void cvmx_bootmem_unlock(void); + +struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void); + +#endif /* __CVMX_BOOTMEM_H__ */ diff --git a/drivers/staging/octeon/cvmx-ciu-defs.h b/drivers/staging/octeon/cvmx-ciu-defs.h new file mode 100644 index 000000000000..dc8514aa0b35 --- /dev/null +++ b/drivers/staging/octeon/cvmx-ciu-defs.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Octeon CIU definitions + * + * Copyright (C) 2003-2018 Cavium, Inc. + */ + +#ifndef __CVMX_CIU_DEFS_H__ +#define __CVMX_CIU_DEFS_H__ + +#include + +#define CVMX_CIU_ADDR(addr, coreid, coremask, offset) \ + (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \ + (((coreid) & (coremask)) * offset)) + +#define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8) +#define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8) +#define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8) +#define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0) +#define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0) +#define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16) +#define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16) +#define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16) +#define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16) +#define CVMX_CIU_INTX_EN1_W1C(c) CVMX_CIU_ADDR(0x2208, c, 0x3F, 16) +#define CVMX_CIU_INTX_EN1_W1S(c) CVMX_CIU_ADDR(0x6208, c, 0x3F, 16) +#define CVMX_CIU_INTX_SUM0(c) CVMX_CIU_ADDR(0x0000, c, 0x3F, 8) +#define CVMX_CIU_NMI CVMX_CIU_ADDR(0x0718, 0, 0x00, 0) +#define CVMX_CIU_PCI_INTA CVMX_CIU_ADDR(0x0750, 0, 0x00, 0) +#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0) +#define CVMX_CIU_PP_DBG CVMX_CIU_ADDR(0x0708, 0, 0x00, 0) +#define CVMX_CIU_PP_RST CVMX_CIU_ADDR(0x0700, 0, 0x00, 0) +#define CVMX_CIU_QLM0 CVMX_CIU_ADDR(0x0780, 0, 0x00, 0) +#define CVMX_CIU_QLM1 CVMX_CIU_ADDR(0x0788, 0, 0x00, 0) +#define CVMX_CIU_QLM_JTGC CVMX_CIU_ADDR(0x0768, 0, 0x00, 0) +#define CVMX_CIU_QLM_JTGD CVMX_CIU_ADDR(0x0770, 0, 0x00, 0) +#define CVMX_CIU_SOFT_BIST CVMX_CIU_ADDR(0x0738, 0, 0x00, 0) +#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_ADDR(0x0758, 0, 0x00, 0) +#define CVMX_CIU_SOFT_PRST CVMX_CIU_ADDR(0x0748, 0, 0x00, 0) +#define CVMX_CIU_SOFT_RST CVMX_CIU_ADDR(0x0740, 0, 0x00, 0) +#define CVMX_CIU_SUM2_PPX_IP4(c) CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8) +#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0) +#define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8) + +static inline u64 CVMX_CIU_MBOX_CLRX(unsigned int coreid) +{ + if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK)) + return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8); + else + return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8); +} + +static inline u64 CVMX_CIU_MBOX_SETX(unsigned int coreid) +{ + if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK)) + return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8); + else + return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8); +} + +static inline u64 CVMX_CIU_PP_POKEX(unsigned int coreid) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8); + case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: + case OCTEON_CN73XX & OCTEON_FAMILY_MASK: + case OCTEON_CN78XX & OCTEON_FAMILY_MASK: + return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) - + 0x60000000000ull; + default: + return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8); + } +} + +static inline u64 CVMX_CIU_WDOGX(unsigned int coreid) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8); + case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: + case OCTEON_CN73XX & OCTEON_FAMILY_MASK: + case OCTEON_CN78XX & OCTEON_FAMILY_MASK: + return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) - + 0x60000000000ull; + default: + return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8); + } +} + +union cvmx_ciu_qlm { + u64 u64; + struct cvmx_ciu_qlm_s { + __BITFIELD_FIELD(u64 g2bypass:1, + __BITFIELD_FIELD(u64 reserved_53_62:10, + __BITFIELD_FIELD(u64 g2deemph:5, + __BITFIELD_FIELD(u64 reserved_45_47:3, + __BITFIELD_FIELD(u64 g2margin:5, + __BITFIELD_FIELD(u64 reserved_32_39:8, + __BITFIELD_FIELD(u64 txbypass:1, + __BITFIELD_FIELD(u64 reserved_21_30:10, + __BITFIELD_FIELD(u64 txdeemph:5, + __BITFIELD_FIELD(u64 reserved_13_15:3, + __BITFIELD_FIELD(u64 txmargin:5, + __BITFIELD_FIELD(u64 reserved_4_7:4, + __BITFIELD_FIELD(u64 lane_en:4, + ;))))))))))))) + } s; +}; + +union cvmx_ciu_qlm_jtgc { + u64 u64; + struct cvmx_ciu_qlm_jtgc_s { + __BITFIELD_FIELD(u64 reserved_17_63:47, + __BITFIELD_FIELD(u64 bypass_ext:1, + __BITFIELD_FIELD(u64 reserved_11_15:5, + __BITFIELD_FIELD(u64 clk_div:3, + __BITFIELD_FIELD(u64 reserved_7_7:1, + __BITFIELD_FIELD(u64 mux_sel:3, + __BITFIELD_FIELD(u64 bypass:4, + ;))))))) + } s; +}; + +union cvmx_ciu_qlm_jtgd { + u64 u64; + struct cvmx_ciu_qlm_jtgd_s { + __BITFIELD_FIELD(u64 capture:1, + __BITFIELD_FIELD(u64 shift:1, + __BITFIELD_FIELD(u64 update:1, + __BITFIELD_FIELD(u64 reserved_45_60:16, + __BITFIELD_FIELD(u64 select:5, + __BITFIELD_FIELD(u64 reserved_37_39:3, + __BITFIELD_FIELD(u64 shft_cnt:5, + __BITFIELD_FIELD(u64 shft_reg:32, + ;)))))))) + } s; +}; + +union cvmx_ciu_soft_prst { + u64 u64; + struct cvmx_ciu_soft_prst_s { + __BITFIELD_FIELD(u64 reserved_3_63:61, + __BITFIELD_FIELD(u64 host64:1, + __BITFIELD_FIELD(u64 npi:1, + __BITFIELD_FIELD(u64 soft_prst:1, + ;)))) + } s; +}; + +union cvmx_ciu_timx { + u64 u64; + struct cvmx_ciu_timx_s { + __BITFIELD_FIELD(u64 reserved_37_63:27, + __BITFIELD_FIELD(u64 one_shot:1, + __BITFIELD_FIELD(u64 len:36, + ;))) + } s; +}; + +union cvmx_ciu_wdogx { + u64 u64; + struct cvmx_ciu_wdogx_s { + __BITFIELD_FIELD(u64 reserved_46_63:18, + __BITFIELD_FIELD(u64 gstopen:1, + __BITFIELD_FIELD(u64 dstop:1, + __BITFIELD_FIELD(u64 cnt:24, + __BITFIELD_FIELD(u64 len:16, + __BITFIELD_FIELD(u64 state:2, + __BITFIELD_FIELD(u64 mode:2, + ;))))))) + } s; +}; + +#endif /* __CVMX_CIU_DEFS_H__ */ diff --git a/drivers/staging/octeon/cvmx-ciu2-defs.h b/drivers/staging/octeon/cvmx-ciu2-defs.h new file mode 100644 index 000000000000..34be28767763 --- /dev/null +++ b/drivers/staging/octeon/cvmx-ciu2-defs.h @@ -0,0 +1,47 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_CIU2_DEFS_H__ +#define __CVMX_CIU2_DEFS_H__ + +#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull)) +#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull) +#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8) +#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8) + +#endif diff --git a/drivers/staging/octeon/cvmx-ciu3-defs.h b/drivers/staging/octeon/cvmx-ciu3-defs.h new file mode 100644 index 000000000000..3719259644c5 --- /dev/null +++ b/drivers/staging/octeon/cvmx-ciu3-defs.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2003-2016 Cavium Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + */ + +#ifndef __CVMX_CIU3_DEFS_H__ +#define __CVMX_CIU3_DEFS_H__ + +#define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull) +#define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull) +#define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull) +#define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull) +#define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8) +#define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8) +#define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull) +#define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8) +#define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8) +#define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull) +#define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull) +#define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull) +#define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull) +#define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull) +#define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8) +#define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8) +#define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8) +#define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull) +#define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8) +#define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8) + +union cvmx_ciu3_bist { + u64 u64; + struct cvmx_ciu3_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63 : 55; + u64 bist : 9; +#else + u64 bist : 9; + u64 reserved_9_63 : 55; +#endif + } s; +}; + +union cvmx_ciu3_const { + u64 u64; + struct cvmx_ciu3_const_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dests_io : 16; + u64 pintsn : 16; + u64 dests_pp : 16; + u64 idt : 16; +#else + u64 idt : 16; + u64 dests_pp : 16; + u64 pintsn : 16; + u64 dests_io : 16; +#endif + } s; +}; + +union cvmx_ciu3_ctl { + u64 u64; + struct cvmx_ciu3_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63 : 59; + u64 mcd_sel : 2; + u64 iscmem_le : 1; + u64 seq_dis : 1; + u64 cclk_dis : 1; +#else + u64 cclk_dis : 1; + u64 seq_dis : 1; + u64 iscmem_le : 1; + u64 mcd_sel : 2; + u64 reserved_5_63 : 59; +#endif + } s; +}; + +union cvmx_ciu3_destx_io_int { + u64 u64; + struct cvmx_ciu3_destx_io_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63 : 12; + u64 intsn : 20; + u64 reserved_10_31 : 22; + u64 intidt : 8; + u64 newint : 1; + u64 intr : 1; +#else + u64 intr : 1; + u64 newint : 1; + u64 intidt : 8; + u64 reserved_10_31 : 22; + u64 intsn : 20; + u64 reserved_52_63 : 12; +#endif + } s; +}; + +union cvmx_ciu3_destx_pp_int { + u64 u64; + struct cvmx_ciu3_destx_pp_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63 : 12; + u64 intsn : 20; + u64 reserved_10_31 : 22; + u64 intidt : 8; + u64 newint : 1; + u64 intr : 1; +#else + u64 intr : 1; + u64 newint : 1; + u64 intidt : 8; + u64 reserved_10_31 : 22; + u64 intsn : 20; + u64 reserved_52_63 : 12; +#endif + } s; +}; + +union cvmx_ciu3_gstop { + u64 u64; + struct cvmx_ciu3_gstop_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63 : 63; + u64 gstop : 1; +#else + u64 gstop : 1; + u64 reserved_1_63 : 63; +#endif + } s; +}; + +union cvmx_ciu3_idtx_ctl { + u64 u64; + struct cvmx_ciu3_idtx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63 : 12; + u64 intsn : 20; + u64 reserved_4_31 : 28; + u64 intr : 1; + u64 newint : 1; + u64 ip_num : 2; +#else + u64 ip_num : 2; + u64 newint : 1; + u64 intr : 1; + u64 reserved_4_31 : 28; + u64 intsn : 20; + u64 reserved_52_63 : 12; +#endif + } s; +}; + +union cvmx_ciu3_idtx_io { + u64 u64; + struct cvmx_ciu3_idtx_io_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63 : 59; + u64 io : 5; +#else + u64 io : 5; + u64 reserved_5_63 : 59; +#endif + } s; +}; + +union cvmx_ciu3_idtx_ppx { + u64 u64; + struct cvmx_ciu3_idtx_ppx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63 : 16; + u64 pp : 48; +#else + u64 pp : 48; + u64 reserved_48_63 : 16; +#endif + } s; +}; + +union cvmx_ciu3_intr_ram_ecc_ctl { + u64 u64; + struct cvmx_ciu3_intr_ram_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63 : 61; + u64 flip_synd : 2; + u64 ecc_ena : 1; +#else + u64 ecc_ena : 1; + u64 flip_synd : 2; + u64 reserved_3_63 : 61; +#endif + } s; +}; + +union cvmx_ciu3_intr_ram_ecc_st { + u64 u64; + struct cvmx_ciu3_intr_ram_ecc_st_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63 : 12; + u64 addr : 20; + u64 reserved_6_31 : 26; + u64 sisc_dbe : 1; + u64 sisc_sbe : 1; + u64 idt_dbe : 1; + u64 idt_sbe : 1; + u64 isc_dbe : 1; + u64 isc_sbe : 1; +#else + u64 isc_sbe : 1; + u64 isc_dbe : 1; + u64 idt_sbe : 1; + u64 idt_dbe : 1; + u64 sisc_sbe : 1; + u64 sisc_dbe : 1; + u64 reserved_6_31 : 26; + u64 addr : 20; + u64 reserved_52_63 : 12; +#endif + } s; +}; + +union cvmx_ciu3_intr_ready { + u64 u64; + struct cvmx_ciu3_intr_ready_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63 : 18; + u64 index : 14; + u64 reserved_1_31 : 31; + u64 ready : 1; +#else + u64 ready : 1; + u64 reserved_1_31 : 31; + u64 index : 14; + u64 reserved_46_63 : 18; +#endif + } s; +}; + +union cvmx_ciu3_intr_slowdown { + u64 u64; + struct cvmx_ciu3_intr_slowdown_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63 : 61; + u64 ctl : 3; +#else + u64 ctl : 3; + u64 reserved_3_63 : 61; +#endif + } s; +}; + +union cvmx_ciu3_iscx_ctl { + u64 u64; + struct cvmx_ciu3_iscx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63 : 40; + u64 idt : 8; + u64 imp : 1; + u64 reserved_2_14 : 13; + u64 en : 1; + u64 raw : 1; +#else + u64 raw : 1; + u64 en : 1; + u64 reserved_2_14 : 13; + u64 imp : 1; + u64 idt : 8; + u64 reserved_24_63 : 40; +#endif + } s; +}; + +union cvmx_ciu3_iscx_w1c { + u64 u64; + struct cvmx_ciu3_iscx_w1c_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63 : 62; + u64 en : 1; + u64 raw : 1; +#else + u64 raw : 1; + u64 en : 1; + u64 reserved_2_63 : 62; +#endif + } s; +}; + +union cvmx_ciu3_iscx_w1s { + u64 u64; + struct cvmx_ciu3_iscx_w1s_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63 : 62; + u64 en : 1; + u64 raw : 1; +#else + u64 raw : 1; + u64 en : 1; + u64 reserved_2_63 : 62; +#endif + } s; +}; + +union cvmx_ciu3_nmi { + u64 u64; + struct cvmx_ciu3_nmi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63 : 16; + u64 nmi : 48; +#else + u64 nmi : 48; + u64 reserved_48_63 : 16; +#endif + } s; +}; + +union cvmx_ciu3_siscx { + u64 u64; + struct cvmx_ciu3_siscx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 en : 64; +#else + u64 en : 64; +#endif + } s; +}; + +union cvmx_ciu3_timx { + u64 u64; + struct cvmx_ciu3_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63 : 27; + u64 one_shot : 1; + u64 len : 36; +#else + u64 len : 36; + u64 one_shot : 1; + u64 reserved_37_63 : 27; +#endif + } s; +}; + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c similarity index 57% rename from arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c rename to drivers/staging/octeon/cvmx-cmd-queue.c index 042a6bc44b5c..61ac7f179e98 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c +++ b/drivers/staging/octeon/cvmx-cmd-queue.c @@ -1,63 +1,62 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Support functions for managing command queues used for - * various hardware blocks. - */ + * Support functions for managing command queues used for + * various hardware blocks. + */ #include -#include +#include "octeon.h" -#include -#include -#include +#include "cvmx-config.h" +#include "cvmx-fpa.h" +#include "cvmx-cmd-queue.h" -#include -#include -#include +#include "cvmx-npei-defs.h" +#include "cvmx-pexp-defs.h" +#include "cvmx-pko-defs.h" /* - * This application uses this pointer to access the global queue - * state. It points to a bootmem named block. - */ + * This application uses this pointer to access the global queue + * state. It points to a bootmem named block. + */ __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr); /* - * Initialize the Global queue state pointer. - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ + * Initialize the Global queue state pointer. + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) { char *alloc_name = "cvmx_cmd_queues"; - extern uint64_t octeon_reserve32_memory; + extern u64 octeon_reserve32_memory; if (likely(__cvmx_cmd_queue_state_ptr)) return CVMX_CMD_QUEUE_SUCCESS; @@ -72,7 +71,7 @@ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) else __cvmx_cmd_queue_state_ptr = cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), - 128, + 128, alloc_name); if (__cvmx_cmd_queue_state_ptr) memset(__cvmx_cmd_queue_state_ptr, 0, @@ -94,28 +93,29 @@ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) } /* - * Initialize a command queue for use. The initial FPA buffer is - * allocated and the hardware unit is configured to point to the - * new command queue. - * - * @queue_id: Hardware command queue to initialize. - * @max_depth: Maximum outstanding commands that can be queued. - * @fpa_pool: FPA pool the command queues should come from. - * @pool_size: Size of each buffer in the FPA pool (bytes) - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, int max_depth, int fpa_pool, int pool_size) { __cvmx_cmd_queue_state_t *qstate; cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr(); + if (result != CVMX_CMD_QUEUE_SUCCESS) return result; qstate = __cvmx_cmd_queue_get_state(queue_id); - if (qstate == NULL) + if (!qstate) return CVMX_CMD_QUEUE_INVALID_PARAM; /* @@ -136,24 +136,18 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, /* See if someone else has already initialized the queue */ if (qstate->base_ptr_div128) { if (max_depth != (int)qstate->max_depth) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "max_depth (%d).\n", - (int)qstate->max_depth); + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different max_depth (%d).\n", + (int)qstate->max_depth); return CVMX_CMD_QUEUE_INVALID_PARAM; } if (fpa_pool != qstate->fpa_pool) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "FPA pool (%u).\n", - qstate->fpa_pool); + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different FPA pool (%u).\n", + qstate->fpa_pool); return CVMX_CMD_QUEUE_INVALID_PARAM; } if ((pool_size >> 3) - 1 != qstate->pool_size_m1) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "FPA pool size (%u).\n", - (qstate->pool_size_m1 + 1) << 3); + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initialized with different FPA pool size (%u).\n", + (qstate->pool_size_m1 + 1) << 3); return CVMX_CMD_QUEUE_INVALID_PARAM; } CVMX_SYNCWS; @@ -164,14 +158,12 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); if (!status.s.enb) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "FPA is not enabled.\n"); + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: FPA is not enabled.\n"); return CVMX_CMD_QUEUE_NO_MEMORY; } buffer = cvmx_fpa_alloc(fpa_pool); - if (buffer == NULL) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Unable to allocate initial buffer.\n"); + if (!buffer) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Unable to allocate initial buffer.\n"); return CVMX_CMD_QUEUE_NO_MEMORY; } @@ -192,33 +184,32 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, } /* - * Shutdown a queue and free its command buffers to the FPA. The - * hardware connected to the queue must be stopped before this - * function is called. - * - * @queue_id: Queue to shutdown - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ + * Shutdown a queue and free its command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) { __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - if (qptr == NULL) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to " - "get queue information.\n"); + + if (!qptr) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to get queue information.\n"); return CVMX_CMD_QUEUE_INVALID_PARAM; } if (cvmx_cmd_queue_length(queue_id) > 0) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still " - "has data in it.\n"); + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still has data in it.\n"); return CVMX_CMD_QUEUE_FULL; } __cvmx_cmd_queue_lock(queue_id, qptr); if (qptr->base_ptr_div128) { cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) qptr->base_ptr_div128 << 7), + ((u64)qptr->base_ptr_div128 << 7), qptr->fpa_pool, 0); qptr->base_ptr_div128 = 0; } @@ -228,13 +219,13 @@ cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) } /* - * Return the number of command words pending in the queue. This - * function may be relatively slow for some hardware units. - * - * @queue_id: Hardware command queue to query - * - * Returns Number of outstanding commands - */ + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) { if (CVMX_ENABLE_PARAMETER_CHECKING) { @@ -246,7 +237,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) * The cast is here so gcc with check that all values in the * cvmx_cmd_queue_id_t enumeration are here. */ - switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) { + switch ((cvmx_cmd_queue_id_t)(queue_id & 0xff0000)) { case CVMX_CMD_QUEUE_PKO_BASE: /* * FIXME: Need atomic lock on @@ -257,10 +248,12 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { union cvmx_pko_mem_debug9 debug9; + debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); return debug9.cn38xx.doorbell; } else { union cvmx_pko_mem_debug8 debug8; + debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); return debug8.cn50xx.doorbell; } @@ -272,6 +265,7 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) case CVMX_CMD_QUEUE_DMA_BASE: { union cvmx_npei_dmax_counts dmax_counts; + dmax_counts.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS (queue_id & 0x7)); @@ -284,20 +278,21 @@ int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) } /* - * Return the command buffer to be written to. The purpose of this - * function is to allow CVMX routine access to the low level buffer - * for initial hardware setup. User applications should not call this - * function directly. - * - * @queue_id: Command queue to query - * - * Returns Command buffer or NULL on failure - */ + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access to the low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) { __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + if (qptr && qptr->base_ptr_div128) - return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7); + return cvmx_phys_to_ptr((u64)qptr->base_ptr_div128 << 7); else return NULL; } diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/drivers/staging/octeon/cvmx-cmd-queue.h new file mode 100644 index 000000000000..9aaba023ede8 --- /dev/null +++ b/drivers/staging/octeon/cvmx-cmd-queue.h @@ -0,0 +1,620 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Support functions for managing command queues used for + * various hardware blocks. + * + * The common command queue infrastructure abstracts out the + * software necessary for adding to Octeon's chained queue + * structures. These structures are used for commands to the + * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each + * hardware unit takes commands and CSRs of different types, + * they all use basic linked command buffers to store the + * pending request. In general, users of the CVMX API don't + * call cvmx-cmd-queue functions directly. Instead the hardware + * unit specific wrapper should be used. The wrappers perform + * unit specific validation and CSR writes to submit the + * commands. + * + * Even though most software will never directly interact with + * cvmx-cmd-queue, knowledge of its internal working can help + * in diagnosing performance problems and help with debugging. + * + * Command queue pointers are stored in a global named block + * called "cvmx_cmd_queues". Except for the PKO queues, each + * hardware queue is stored in its own cache line to reduce SMP + * contention on spin locks. The PKO queues are stored such that + * every 16th queue is next to each other in memory. This scheme + * allows for queues being in separate cache lines when there + * are low number of queues per port. With 16 queues per port, + * the first queue for each port is in the same cache area. The + * second queues for each port are in another area, etc. This + * allows software to implement very efficient lockless PKO with + * 16 queues per port using a minimum of cache lines per core. + * All queues for a given core will be isolated in the same + * cache area. + * + * In addition to the memory pointer layout, cvmx-cmd-queue + * provides an optimized fair ll/sc locking mechanism for the + * queues. The lock uses a "ticket / now serving" model to + * maintain fair order on contended locks. In addition, it uses + * predicted locking time to limit cache contention. When a core + * know it must wait in line for a lock, it spins on the + * internal cycle counter to completely eliminate any causes of + * bus traffic. + * + */ + +#ifndef __CVMX_CMD_QUEUE_H__ +#define __CVMX_CMD_QUEUE_H__ + +#include + +#include + +#include "cvmx-fpa.h" +/** + * By default we disable the max depth support. Most programs + * don't use it and it slows down the command queue processing + * significantly. + */ +#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH +#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0 +#endif + +/** + * Enumeration representing all hardware blocks that use command + * queues. Each hardware block has up to 65536 sub identifiers for + * multiple command queues. Not all chips support all hardware + * units. + */ +typedef enum { + CVMX_CMD_QUEUE_PKO_BASE = 0x00000, + +#define CVMX_CMD_QUEUE_PKO(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff & (queue)))) + + CVMX_CMD_QUEUE_ZIP = 0x10000, + CVMX_CMD_QUEUE_DFA = 0x20000, + CVMX_CMD_QUEUE_RAID = 0x30000, + CVMX_CMD_QUEUE_DMA_BASE = 0x40000, + +#define CVMX_CMD_QUEUE_DMA(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff & (queue)))) + + CVMX_CMD_QUEUE_END = 0x50000, +} cvmx_cmd_queue_id_t; + +/** + * Command write operations can fail if the command queue needs + * a new buffer and the associated FPA pool is empty. It can also + * fail if the number of queued command words reaches the maximum + * set at initialization. + */ +typedef enum { + CVMX_CMD_QUEUE_SUCCESS = 0, + CVMX_CMD_QUEUE_NO_MEMORY = -1, + CVMX_CMD_QUEUE_FULL = -2, + CVMX_CMD_QUEUE_INVALID_PARAM = -3, + CVMX_CMD_QUEUE_ALREADY_SETUP = -4, +} cvmx_cmd_queue_result_t; + +typedef struct { + /* You have lock when this is your ticket */ + u8 now_serving; + u64 unused1:24; + /* Maximum outstanding command words */ + u32 max_depth; + /* FPA pool buffers come from */ + u64 fpa_pool:3; + /* Top of command buffer pointer shifted 7 */ + u64 base_ptr_div128:29; + u64 unused2:6; + /* FPA buffer size in 64bit words minus 1 */ + u64 pool_size_m1:13; + /* Number of commands already used in buffer */ + u64 index:13; +} __cvmx_cmd_queue_state_t; + +/** + * This structure contains the global state of all command queues. + * It is stored in a bootmem named block and shared by all + * applications running on Octeon. Tickets are stored in a different + * cache line that queue information to reduce the contention on the + * ll/sc used to get a ticket. If this is not the case, the update + * of queue state causes the ll/sc to fail quite often. + */ +typedef struct { + u64 ticket[(CVMX_CMD_QUEUE_END >> 16) * 256]; + __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256]; +} __cvmx_cmd_queue_all_state_t; + +/** + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, + int max_depth, int fpa_pool, + int pool_size); + +/** + * Shutdown a queue and free its command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ +int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access to the low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ +void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id); + +/** + * Get the index into the state arrays for the supplied queue id. + * + * @queue_id: Queue ID to get an index for + * + * Returns Index into the state arrays + */ +static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) +{ + /* + * Warning: This code currently only works with devices that + * have 256 queues or less. Devices with more than 16 queues + * are laid out in memory to allow cores quick access to + * every 16th queue. This reduces cache thrashing when you are + * running 16 queues per port to support lockless operation. + */ + int unit = queue_id >> 16; + int q = (queue_id >> 4) & 0xf; + int core = queue_id & 0xf; + + return unit * 256 + core * 16 + q; +} + +/** + * Lock the supplied queue so nobody else is updating it at the same + * time as us. + * + * @queue_id: Queue ID to lock + * @qptr: Pointer to the queue's global state + */ +static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, + __cvmx_cmd_queue_state_t *qptr) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + int tmp; + int my_ticket; + + prefetch(qptr); + asm volatile ( + ".set push\n" + ".set noreorder\n" + "1:\n" + /* Atomic add one to ticket_ptr */ + "ll %[my_ticket], %[ticket_ptr]\n" + /* and store the original value */ + "li %[ticket], 1\n" + /* in my_ticket */ + "baddu %[ticket], %[my_ticket]\n" + "sc %[ticket], %[ticket_ptr]\n" + "beqz %[ticket], 1b\n" + " nop\n" + /* Load the current now_serving ticket */ + "lbu %[ticket], %[now_serving]\n" + "2:\n" + /* Jump out if now_serving == my_ticket */ + "beq %[ticket], %[my_ticket], 4f\n" + /* Find out how many tickets are in front of me */ + " subu %[ticket], %[my_ticket], %[ticket]\n" + /* Use tickets in front of me minus one to delay */ + "subu %[ticket], 1\n" + /* Delay will be ((tickets in front)-1)*32 loops */ + "cins %[ticket], %[ticket], 5, 7\n" + "3:\n" + /* Loop here until our ticket might be up */ + "bnez %[ticket], 3b\n" + " subu %[ticket], 1\n" + /* Jump back up to check out ticket again */ + "b 2b\n" + /* Load the current now_serving ticket */ + " lbu %[ticket], %[now_serving]\n" + "4:\n" + ".set pop\n" : + [ticket_ptr] "=" GCC_OFF_SMALL_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), + [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), + [my_ticket] "=r"(my_ticket) + ); +} + +/** + * Unlock the queue, flushing all writes. + * + * @qptr: Queue to unlock + */ +static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr) +{ + qptr->now_serving++; + CVMX_SYNCWS; +} + +/** + * Get the queue state structure for the given queue id + * + * @queue_id: Queue id to get + * + * Returns Queue structure or NULL on failure + */ +static inline __cvmx_cmd_queue_state_t + *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + return &__cvmx_cmd_queue_state_ptr-> + state[__cvmx_cmd_queue_get_index(queue_id)]; +} + +/** + * Write an arbitrary number of command words to a command queue. + * This is a generic function; the fixed number of command word + * functions yield higher performance. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd_count: Number of command words to write + * @cmds: Array of commands to write + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + int cmd_count, + u64 *cmds) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { + u64 *ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += cmd_count; + while (cmd_count--) + *ptr++ = *cmds++; + } else { + u64 *ptr; + int count; + /* + * We need a new command buffer. Fail if there isn't + * one available. + */ + u64 *new_buffer = + (u64 *)cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(!new_buffer)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + count = qptr->pool_size_m1 - qptr->index; + ptr += qptr->index; + cmd_count -= count; + while (count--) + *ptr++ = *cmds++; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = cmd_count; + ptr = new_buffer; + while (cmd_count--) + *ptr++ = *cmds++; + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write two command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + u64 cmd1, + u64 cmd2) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 2 < qptr->pool_size_m1)) { + u64 *ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 2; + ptr[0] = cmd1; + ptr[1] = cmd2; + } else { + u64 *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new command buffer. Fail if there isn't + * one available. + */ + u64 *new_buffer = + (u64 *)cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(!new_buffer)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (likely(count)) + *ptr++ = cmd2; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + if (unlikely(count == 0)) { + qptr->index = 1; + new_buffer[0] = cmd2; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write three command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * @cmd3: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + u64 cmd1, + u64 cmd2, + u64 cmd3) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 3 < qptr->pool_size_m1)) { + u64 *ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 3; + ptr[0] = cmd1; + ptr[1] = cmd2; + ptr[2] = cmd3; + } else { + u64 *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new command buffer. Fail if there isn't + * one available + */ + u64 *new_buffer = + (u64 *)cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(!new_buffer)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (u64 *)cvmx_phys_to_ptr((u64)qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (count) { + *ptr++ = cmd2; + if (count > 1) + *ptr++ = cmd3; + } + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + ptr = new_buffer; + if (count == 0) { + *ptr++ = cmd2; + qptr->index++; + } + if (count < 2) { + *ptr++ = cmd3; + qptr->index++; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +#endif /* __CVMX_CMD_QUEUE_H__ */ diff --git a/drivers/staging/octeon/cvmx-config.h b/drivers/staging/octeon/cvmx-config.h new file mode 100644 index 000000000000..9d3512b51c1f --- /dev/null +++ b/drivers/staging/octeon/cvmx-config.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CVMX_CONFIG_H__ +#define __CVMX_CONFIG_H__ + +/************************* Config Specific Defines ************************/ +#define CVMX_LLM_NUM_PORTS 1 +#define CVMX_NULL_POINTER_PROTECT 1 +#define CVMX_ENABLE_DEBUG_PRINTS 1 +/* PKO queues per port for interface 0 (ports 0-15) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 +/* PKO queues per port for interface 1 (ports 16-31) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 +/* Limit on the number of PKO ports enabled for interface 0 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 +/* Limit on the number of PKO ports enabled for interface 1 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 +/* PKO queues per port for PCI (ports 32-35) */ +#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 +/* PKO queues per port for Loop devices (ports 36-39) */ +#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 + +/************************* FPA allocation *********************************/ +/* Pool sizes in bytes, must be multiple of a cache line */ +#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) + +/* Pools in use */ +/* Packet buffers */ +#define CVMX_FPA_PACKET_POOL (0) +#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE +/* Work queue entries */ +#define CVMX_FPA_WQE_POOL (1) +#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE +/* PKO queue command buffers */ +#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE + +/************************* FAU allocation ********************************/ +/* The fetch and add registers are allocated here. They are arranged + * in order of descending size so that all alignment constraints are + * automatically met. The enums are linked so that the following enum + * continues allocating where the previous one left off, so the + * numbering within each enum always starts with zero. The macros + * take care of the address increment size, so the values entered + * always increase by 1. FAU registers are accessed with byte + * addresses. + */ + +#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) +typedef enum { + CVMX_FAU_REG_64_START = 0, + CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), +} cvmx_fau_reg_64_t; + +#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) +typedef enum { + CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, + CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), +} cvmx_fau_reg_32_t; + +#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) +typedef enum { + CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, + CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), +} cvmx_fau_reg_16_t; + +#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) +typedef enum { + CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, + CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), +} cvmx_fau_reg_8_t; + +/* + * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first + * available FAU address that is not allocated in cvmx-config.h. This + * is 64 bit aligned. + */ +#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) +#define CVMX_FAU_REG_END (2048) + +/********************** scratch memory allocation *************************/ +/* Scratchpad memory allocation. Note that these are byte memory + * addresses. Some uses of scratchpad (IOBDMA for example) require + * the use of 8-byte aligned addresses, so proper alignment needs to + * be taken into account. + */ +/* Generic scratch iobdma area */ +#define CVMX_SCR_SCRATCH (0) +/* First location available after cvmx-config.h allocated region. */ +#define CVMX_SCR_REG_AVAIL_BASE (8) + +/* + * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve + * before the beginning of the packet. If necessary, override the + * default here. See the IPD section of the hardware manual for MBUFF + * SKIP details. + */ +#define CVMX_HELPER_FIRST_MBUFF_SKIP 184 + +/* + * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve + * in each chained packet element. If necessary, override the default + * here. + */ +#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 + +/* + * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is + * enabled for all input ports. This controls if IPD sends + * backpressure to all ports if Octeon's FPA pools don't have enough + * packet or work queue entries. Even when this is off, it is still + * possible to get backpressure from individual hardware ports. When + * configuring backpressure, also check + * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override + * the default here. + */ +#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 + +/* + * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper + * function. Once it is enabled the hardware starts accepting + * packets. You might want to skip the IPD enable if configuration + * changes are need from the default helper setup. If necessary, + * override the default here. + */ +#define CVMX_HELPER_ENABLE_IPD 0 + +/* + * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns + * to incoming packets. + */ +#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED + +#define CVMX_ENABLE_PARAMETER_CHECKING 0 + +/* + * The following select which fields are used by the PIP to generate + * the tag on INPUT + * 0: don't include + * 1: include + */ +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 +#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 + +/* Select skip mode for input ports */ +#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 + +/* + * Force backpressure to be disabled. This overrides all other + * backpressure configuration. + */ +#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 + +#endif /* __CVMX_CONFIG_H__ */ diff --git a/drivers/staging/octeon/cvmx-coremask.h b/drivers/staging/octeon/cvmx-coremask.h new file mode 100644 index 000000000000..a5ad46992250 --- /dev/null +++ b/drivers/staging/octeon/cvmx-coremask.h @@ -0,0 +1,88 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2016 Cavium Inc. (support@cavium.com). + * + */ + +/* + * Module to support operations on bitmap of cores. Coremask can be used to + * select a specific core, a group of cores, or all available cores, for + * initialization and differentiation of roles within a single shared binary + * executable image. + * + * The core numbers used in this file are the same value as what is found in + * the COP0_EBASE register and the rdhwr 0 instruction. + * + * For the CN78XX and other multi-node environments the core numbers are not + * contiguous. The core numbers for the CN78XX are as follows: + * + * Node 0: Cores 0 - 47 + * Node 1: Cores 128 - 175 + * Node 2: Cores 256 - 303 + * Node 3: Cores 384 - 431 + * + */ + +#ifndef __CVMX_COREMASK_H__ +#define __CVMX_COREMASK_H__ + +#define CVMX_MIPS_MAX_CORES 1024 +/* bits per holder */ +#define CVMX_COREMASK_ELTSZ 64 + +/* cvmx_coremask_t's size in u64 */ +#define CVMX_COREMASK_BMPSZ (CVMX_MIPS_MAX_CORES / CVMX_COREMASK_ELTSZ) + +/* cvmx_coremask_t */ +struct cvmx_coremask { + u64 coremask_bitmap[CVMX_COREMASK_BMPSZ]; +}; + +/* + * Is ``core'' set in the coremask? + */ +static inline bool cvmx_coremask_is_core_set(const struct cvmx_coremask *pcm, + int core) +{ + int n, i; + + n = core % CVMX_COREMASK_ELTSZ; + i = core / CVMX_COREMASK_ELTSZ; + + return (pcm->coremask_bitmap[i] & ((u64)1 << n)) != 0; +} + +/* + * Make a copy of a coremask + */ +static inline void cvmx_coremask_copy(struct cvmx_coremask *dest, + const struct cvmx_coremask *src) +{ + memcpy(dest, src, sizeof(*dest)); +} + +/* + * Set the lower 64-bit of the coremask. + */ +static inline void cvmx_coremask_set64(struct cvmx_coremask *pcm, + u64 coremask_64) +{ + pcm->coremask_bitmap[0] = coremask_64; +} + +/* + * Clear ``core'' from the coremask. + */ +static inline void cvmx_coremask_clear_core(struct cvmx_coremask *pcm, int core) +{ + int n, i; + + n = core % CVMX_COREMASK_ELTSZ; + i = core / CVMX_COREMASK_ELTSZ; + pcm->coremask_bitmap[i] &= ~(1ull << n); +} + +#endif /* __CVMX_COREMASK_H__ */ diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/drivers/staging/octeon/cvmx-dbg-defs.h new file mode 100644 index 000000000000..a17caee092bb --- /dev/null +++ b/drivers/staging/octeon/cvmx-dbg-defs.h @@ -0,0 +1,100 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_DBG_DEFS_H__ +#define __CVMX_DBG_DEFS_H__ + +#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) + +union cvmx_dbg_data { + u64 u64; + struct cvmx_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_dbg_data_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 pll_mul:3; + u64 reserved_23_27:5; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 reserved_23_27:5; + u64 pll_mul:3; + u64 reserved_31_63:33; +#endif + } cn30xx; + struct cvmx_dbg_data_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 d_mul:4; + u64 dclk_mul2:1; + u64 cclk_div2:1; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 cclk_div2:1; + u64 dclk_mul2:1; + u64 d_mul:4; + u64 reserved_29_63:35; +#endif + } cn38xx; + struct cvmx_dbg_data_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 rem:6; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 rem:6; + u64 reserved_29_63:35; +#endif + } cn58xx; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-dpi-defs.h b/drivers/staging/octeon/cvmx-dpi-defs.h new file mode 100644 index 000000000000..6d4df58d4d42 --- /dev/null +++ b/drivers/staging/octeon/cvmx-dpi-defs.h @@ -0,0 +1,873 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_DPI_DEFS_H__ +#define __CVMX_DPI_DEFS_H__ + +#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) +#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) +#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) +#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) +#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8) +#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) +#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) +#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) +#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) +#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull)) +#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) +#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) +#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) +#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) +#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) +#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) +#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) +#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) +#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) +static inline u64 CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + + if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8; + } + return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8; +} + +#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) + +union cvmx_dpi_bist_status { + u64 u64; + struct cvmx_dpi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 bist:47; +#else + u64 bist:47; + u64 reserved_47_63:17; +#endif + } s; + struct cvmx_dpi_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 bist:45; +#else + u64 bist:45; + u64 reserved_45_63:19; +#endif + } cn63xx; + struct cvmx_dpi_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 bist:37; +#else + u64 bist:37; + u64 reserved_37_63:27; +#endif + } cn63xxp1; +}; + +union cvmx_dpi_ctl { + u64 u64; + struct cvmx_dpi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 clk:1; + u64 en:1; +#else + u64 en:1; + u64 clk:1; + u64 reserved_2_63:62; +#endif + } s; + struct cvmx_dpi_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 en:1; +#else + u64 en:1; + u64 reserved_1_63:63; +#endif + } cn61xx; +}; + +union cvmx_dpi_dmax_counts { + u64 u64; + struct cvmx_dpi_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 fcnt:7; + u64 dbell:32; +#else + u64 dbell:32; + u64 fcnt:7; + u64 reserved_39_63:25; +#endif + } s; +}; + +union cvmx_dpi_dmax_dbell { + u64 u64; + struct cvmx_dpi_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dbell:16; +#else + u64 dbell:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_dpi_dmax_err_rsp_status { + u64 u64; + struct cvmx_dpi_dmax_err_rsp_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 status:6; +#else + u64 status:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_dpi_dmax_ibuff_saddr { + u64 u64; + struct cvmx_dpi_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 csize:14; + u64 reserved_41_47:7; + u64 idle:1; + u64 saddr:33; + u64 reserved_0_6:7; +#else + u64 reserved_0_6:7; + u64 saddr:33; + u64 idle:1; + u64 reserved_41_47:7; + u64 csize:14; + u64 reserved_62_63:2; +#endif + } s; + struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 csize:14; + u64 reserved_41_47:7; + u64 idle:1; + u64 reserved_36_39:4; + u64 saddr:29; + u64 reserved_0_6:7; +#else + u64 reserved_0_6:7; + u64 saddr:29; + u64 reserved_36_39:4; + u64 idle:1; + u64 reserved_41_47:7; + u64 csize:14; + u64 reserved_62_63:2; +#endif + } cn61xx; +}; + +union cvmx_dpi_dmax_iflight { + u64 u64; + struct cvmx_dpi_dmax_iflight_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 cnt:3; +#else + u64 cnt:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_dpi_dmax_naddr { + u64 u64; + struct cvmx_dpi_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 addr:40; +#else + u64 addr:40; + u64 reserved_40_63:24; +#endif + } s; + struct cvmx_dpi_dmax_naddr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 addr:36; +#else + u64 addr:36; + u64 reserved_36_63:28; +#endif + } cn61xx; +}; + +union cvmx_dpi_dmax_reqbnk0 { + u64 u64; + struct cvmx_dpi_dmax_reqbnk0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 state:64; +#else + u64 state:64; +#endif + } s; +}; + +union cvmx_dpi_dmax_reqbnk1 { + u64 u64; + struct cvmx_dpi_dmax_reqbnk1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 state:64; +#else + u64 state:64; +#endif + } s; +}; + +union cvmx_dpi_dma_control { + u64 u64; + struct cvmx_dpi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 dici_mode:1; + u64 pkt_en1:1; + u64 ffp_dis:1; + u64 commit_mode:1; + u64 pkt_hp:1; + u64 pkt_en:1; + u64 reserved_54_55:2; + u64 dma_enb:6; + u64 reserved_34_47:14; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 reserved_0_13:14; +#else + u64 reserved_0_13:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 reserved_34_47:14; + u64 dma_enb:6; + u64 reserved_54_55:2; + u64 pkt_en:1; + u64 pkt_hp:1; + u64 commit_mode:1; + u64 ffp_dis:1; + u64 pkt_en1:1; + u64 dici_mode:1; + u64 reserved_62_63:2; +#endif + } s; + struct cvmx_dpi_dma_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 pkt_en1:1; + u64 ffp_dis:1; + u64 commit_mode:1; + u64 pkt_hp:1; + u64 pkt_en:1; + u64 reserved_54_55:2; + u64 dma_enb:6; + u64 reserved_34_47:14; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 reserved_0_13:14; +#else + u64 reserved_0_13:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 reserved_34_47:14; + u64 dma_enb:6; + u64 reserved_54_55:2; + u64 pkt_en:1; + u64 pkt_hp:1; + u64 commit_mode:1; + u64 ffp_dis:1; + u64 pkt_en1:1; + u64 reserved_61_63:3; +#endif + } cn63xx; + struct cvmx_dpi_dma_control_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 commit_mode:1; + u64 pkt_hp:1; + u64 pkt_en:1; + u64 reserved_54_55:2; + u64 dma_enb:6; + u64 reserved_34_47:14; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 reserved_0_13:14; +#else + u64 reserved_0_13:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 reserved_34_47:14; + u64 dma_enb:6; + u64 reserved_54_55:2; + u64 pkt_en:1; + u64 pkt_hp:1; + u64 commit_mode:1; + u64 reserved_59_63:5; +#endif + } cn63xxp1; +}; + +union cvmx_dpi_dma_engx_en { + u64 u64; + struct cvmx_dpi_dma_engx_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 qen:8; +#else + u64 qen:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_dma_ppx_cnt { + u64 u64; + struct cvmx_dpi_dma_ppx_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt:16; +#else + u64 cnt:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_dpi_engx_buf { + u64 u64; + struct cvmx_dpi_engx_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 compblks:5; + u64 reserved_9_31:23; + u64 base:5; + u64 blks:4; +#else + u64 blks:4; + u64 base:5; + u64 reserved_9_31:23; + u64 compblks:5; + u64 reserved_37_63:27; +#endif + } s; + struct cvmx_dpi_engx_buf_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 base:4; + u64 blks:4; +#else + u64 blks:4; + u64 base:4; + u64 reserved_8_63:56; +#endif + } cn63xx; +}; + +union cvmx_dpi_info_reg { + u64 u64; + struct cvmx_dpi_info_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ffp:4; + u64 reserved_2_3:2; + u64 ncb:1; + u64 rsl:1; +#else + u64 rsl:1; + u64 ncb:1; + u64 reserved_2_3:2; + u64 ffp:4; + u64 reserved_8_63:56; +#endif + } s; + struct cvmx_dpi_info_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 ncb:1; + u64 rsl:1; +#else + u64 rsl:1; + u64 ncb:1; + u64 reserved_2_63:62; +#endif + } cn63xxp1; +}; + +union cvmx_dpi_int_en { + u64 u64; + struct cvmx_dpi_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 sprt3_rst:1; + u64 sprt2_rst:1; + u64 sprt1_rst:1; + u64 sprt0_rst:1; + u64 reserved_23_23:1; + u64 req_badfil:1; + u64 req_inull:1; + u64 req_anull:1; + u64 req_undflw:1; + u64 req_ovrflw:1; + u64 req_badlen:1; + u64 req_badadr:1; + u64 dmadbo:8; + u64 reserved_2_7:6; + u64 nfovr:1; + u64 nderr:1; +#else + u64 nderr:1; + u64 nfovr:1; + u64 reserved_2_7:6; + u64 dmadbo:8; + u64 req_badadr:1; + u64 req_badlen:1; + u64 req_ovrflw:1; + u64 req_undflw:1; + u64 req_anull:1; + u64 req_inull:1; + u64 req_badfil:1; + u64 reserved_23_23:1; + u64 sprt0_rst:1; + u64 sprt1_rst:1; + u64 sprt2_rst:1; + u64 sprt3_rst:1; + u64 reserved_28_63:36; +#endif + } s; + struct cvmx_dpi_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 sprt1_rst:1; + u64 sprt0_rst:1; + u64 reserved_23_23:1; + u64 req_badfil:1; + u64 req_inull:1; + u64 req_anull:1; + u64 req_undflw:1; + u64 req_ovrflw:1; + u64 req_badlen:1; + u64 req_badadr:1; + u64 dmadbo:8; + u64 reserved_2_7:6; + u64 nfovr:1; + u64 nderr:1; +#else + u64 nderr:1; + u64 nfovr:1; + u64 reserved_2_7:6; + u64 dmadbo:8; + u64 req_badadr:1; + u64 req_badlen:1; + u64 req_ovrflw:1; + u64 req_undflw:1; + u64 req_anull:1; + u64 req_inull:1; + u64 req_badfil:1; + u64 reserved_23_23:1; + u64 sprt0_rst:1; + u64 sprt1_rst:1; + u64 reserved_26_63:38; +#endif + } cn63xx; +}; + +union cvmx_dpi_int_reg { + u64 u64; + struct cvmx_dpi_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 sprt3_rst:1; + u64 sprt2_rst:1; + u64 sprt1_rst:1; + u64 sprt0_rst:1; + u64 reserved_23_23:1; + u64 req_badfil:1; + u64 req_inull:1; + u64 req_anull:1; + u64 req_undflw:1; + u64 req_ovrflw:1; + u64 req_badlen:1; + u64 req_badadr:1; + u64 dmadbo:8; + u64 reserved_2_7:6; + u64 nfovr:1; + u64 nderr:1; +#else + u64 nderr:1; + u64 nfovr:1; + u64 reserved_2_7:6; + u64 dmadbo:8; + u64 req_badadr:1; + u64 req_badlen:1; + u64 req_ovrflw:1; + u64 req_undflw:1; + u64 req_anull:1; + u64 req_inull:1; + u64 req_badfil:1; + u64 reserved_23_23:1; + u64 sprt0_rst:1; + u64 sprt1_rst:1; + u64 sprt2_rst:1; + u64 sprt3_rst:1; + u64 reserved_28_63:36; +#endif + } s; + struct cvmx_dpi_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 sprt1_rst:1; + u64 sprt0_rst:1; + u64 reserved_23_23:1; + u64 req_badfil:1; + u64 req_inull:1; + u64 req_anull:1; + u64 req_undflw:1; + u64 req_ovrflw:1; + u64 req_badlen:1; + u64 req_badadr:1; + u64 dmadbo:8; + u64 reserved_2_7:6; + u64 nfovr:1; + u64 nderr:1; +#else + u64 nderr:1; + u64 nfovr:1; + u64 reserved_2_7:6; + u64 dmadbo:8; + u64 req_badadr:1; + u64 req_badlen:1; + u64 req_ovrflw:1; + u64 req_undflw:1; + u64 req_anull:1; + u64 req_inull:1; + u64 req_badfil:1; + u64 reserved_23_23:1; + u64 sprt0_rst:1; + u64 sprt1_rst:1; + u64 reserved_26_63:38; +#endif + } cn63xx; +}; + +union cvmx_dpi_ncbx_cfg { + u64 u64; + struct cvmx_dpi_ncbx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 molr:6; +#else + u64 molr:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_dpi_pint_info { + u64 u64; + struct cvmx_dpi_pint_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 iinfo:6; + u64 reserved_6_7:2; + u64 sinfo:6; +#else + u64 sinfo:6; + u64 reserved_6_7:2; + u64 iinfo:6; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_dpi_pkt_err_rsp { + u64 u64; + struct cvmx_dpi_pkt_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 pkterr:1; +#else + u64 pkterr:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_dpi_req_err_rsp { + u64 u64; + struct cvmx_dpi_req_err_rsp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 qerr:8; +#else + u64 qerr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_req_err_rsp_en { + u64 u64; + struct cvmx_dpi_req_err_rsp_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 en:8; +#else + u64 en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_req_err_rst { + u64 u64; + struct cvmx_dpi_req_err_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 qerr:8; +#else + u64 qerr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_req_err_rst_en { + u64 u64; + struct cvmx_dpi_req_err_rst_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 en:8; +#else + u64 en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_req_err_skip_comp { + u64 u64; + struct cvmx_dpi_req_err_skip_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 en_rst:8; + u64 reserved_8_15:8; + u64 en_rsp:8; +#else + u64 en_rsp:8; + u64 reserved_8_15:8; + u64 en_rst:8; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_dpi_req_gbl_en { + u64 u64; + struct cvmx_dpi_req_gbl_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 qen:8; +#else + u64 qen:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_dpi_sli_prtx_cfg { + u64 u64; + struct cvmx_dpi_sli_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 halt:1; + u64 qlm_cfg:4; + u64 reserved_17_19:3; + u64 rd_mode:1; + u64 reserved_14_15:2; + u64 molr:6; + u64 mps_lim:1; + u64 reserved_5_6:2; + u64 mps:1; + u64 mrrs_lim:1; + u64 reserved_2_2:1; + u64 mrrs:2; +#else + u64 mrrs:2; + u64 reserved_2_2:1; + u64 mrrs_lim:1; + u64 mps:1; + u64 reserved_5_6:2; + u64 mps_lim:1; + u64 molr:6; + u64 reserved_14_15:2; + u64 rd_mode:1; + u64 reserved_17_19:3; + u64 qlm_cfg:4; + u64 halt:1; + u64 reserved_25_63:39; +#endif + } s; + struct cvmx_dpi_sli_prtx_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 halt:1; + u64 reserved_21_23:3; + u64 qlm_cfg:1; + u64 reserved_17_19:3; + u64 rd_mode:1; + u64 reserved_14_15:2; + u64 molr:6; + u64 mps_lim:1; + u64 reserved_5_6:2; + u64 mps:1; + u64 mrrs_lim:1; + u64 reserved_2_2:1; + u64 mrrs:2; +#else + u64 mrrs:2; + u64 reserved_2_2:1; + u64 mrrs_lim:1; + u64 mps:1; + u64 reserved_5_6:2; + u64 mps_lim:1; + u64 molr:6; + u64 reserved_14_15:2; + u64 rd_mode:1; + u64 reserved_17_19:3; + u64 qlm_cfg:1; + u64 reserved_21_23:3; + u64 halt:1; + u64 reserved_25_63:39; +#endif + } cn63xx; +}; + +union cvmx_dpi_sli_prtx_err { + u64 u64; + struct cvmx_dpi_sli_prtx_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:61; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 addr:61; +#endif + } s; +}; + +union cvmx_dpi_sli_prtx_err_info { + u64 u64; + struct cvmx_dpi_sli_prtx_err_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 lock:1; + u64 reserved_5_7:3; + u64 type:1; + u64 reserved_3_3:1; + u64 reqq:3; +#else + u64 reqq:3; + u64 reserved_3_3:1; + u64 type:1; + u64 reserved_5_7:3; + u64 lock:1; + u64 reserved_9_63:55; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-fau.h b/drivers/staging/octeon/cvmx-fau.h new file mode 100644 index 000000000000..0c36f4af8bd1 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fau.h @@ -0,0 +1,618 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the hardware Fetch and Add Unit. + */ + +#ifndef __CVMX_FAU_H__ +#define __CVMX_FAU_H__ + +/* + * Octeon Fetch and Add Unit (FAU) + */ + +#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) +#define CVMX_FAU_BITS_SCRADDR 63, 56 +#define CVMX_FAU_BITS_LEN 55, 48 +#define CVMX_FAU_BITS_INEVAL 35, 14 +#define CVMX_FAU_BITS_TAGWAIT 13, 13 +#define CVMX_FAU_BITS_NOADD 13, 13 +#define CVMX_FAU_BITS_SIZE 12, 11 +#define CVMX_FAU_BITS_REGISTER 10, 0 + +typedef enum { + CVMX_FAU_OP_SIZE_8 = 0, + CVMX_FAU_OP_SIZE_16 = 1, + CVMX_FAU_OP_SIZE_32 = 2, + CVMX_FAU_OP_SIZE_64 = 3 +} cvmx_fau_op_size_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + u64 error:1; + int64_t value:63; +} cvmx_fau_tagwait64_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + u64 error:1; + int32_t value:31; +} cvmx_fau_tagwait32_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + u64 error:1; + int16_t value:15; +} cvmx_fau_tagwait16_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + u64 error:1; + int8_t value:7; +} cvmx_fau_tagwait8_t; + +/** + * Asynchronous tagwait return definition. If a timeout occurs, + * the error bit will be set. Otherwise the value of the + * register before the update will be returned. + */ +typedef union { + u64 u64; + struct { + u64 invalid:1; + u64 data:63; /* unpredictable if invalid is set */ + } s; +} cvmx_fau_async_tagwait_result_t; + +#ifdef __BIG_ENDIAN_BITFIELD +#define SWIZZLE_8 0 +#define SWIZZLE_16 0 +#define SWIZZLE_32 0 +#else +#define SWIZZLE_8 0x7 +#define SWIZZLE_16 0x6 +#define SWIZZLE_32 0x4 +#endif + +/** + * Builds a store I/O address for writing to the FAU + * + * @noadd: 0 = Store value is atomically added to the current value + * 1 = Store value is atomically written over the current value + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Address to store for atomic update + */ +static inline u64 __cvmx_fau_store_address(u64 noadd, u64 reg) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Builds a I/O address for accessing the FAU + * + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * Returns Address to read from for atomic update + */ +static inline u64 __cvmx_fau_atomic_address(u64 tagwait, u64 reg, + int64_t value) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, + int64_t value) +{ + return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, + int32_t value) +{ + reg ^= SWIZZLE_32; + return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, + int16_t value) +{ + reg ^= SWIZZLE_16; + return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + reg ^= SWIZZLE_8; + return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 64 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait64_t +cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + union { + u64 i64; + cvmx_fau_tagwait64_t t; + } result; + result.i64 = + cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 32 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait32_t +cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + union { + u64 i32; + cvmx_fau_tagwait32_t t; + } result; + reg ^= SWIZZLE_32; + result.i32 = + cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 16 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait16_t +cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + union { + u64 i16; + cvmx_fau_tagwait16_t t; + } result; + reg ^= SWIZZLE_16; + result.i16 = + cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 8 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait8_t +cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + union { + u64 i8; + cvmx_fau_tagwait8_t t; + } result; + reg ^= SWIZZLE_8; + result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Builds I/O data for async operations + * + * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @size: The size of the operation: + * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits + * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits + * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits + * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Data to write using cvmx_send_single + */ +static inline u64 __cvmx_fau_iobdma_data(u64 scraddr, int64_t value, + u64 tagwait, + cvmx_fau_op_size_t size, + u64 reg) +{ + return CVMX_FAU_LOAD_IO_ADDRESS | + cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | + cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an async atomic 64 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add64(u64 scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add32(u64 scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add16(u64 scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add8(u64 scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an async atomic 64 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add64(u64 scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add32(u64 scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add16(u64 scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add8(u64 scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + reg ^= SWIZZLE_32; + cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + reg ^= SWIZZLE_16; + cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + reg ^= SWIZZLE_8; + cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 64 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 32 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) +{ + reg ^= SWIZZLE_32; + cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 16 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) +{ + reg ^= SWIZZLE_16; + cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 8 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) +{ + reg ^= SWIZZLE_8; + cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); +} + +#endif /* __CVMX_FAU_H__ */ diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/drivers/staging/octeon/cvmx-fpa-defs.h new file mode 100644 index 000000000000..cf817cd916ab --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa-defs.h @@ -0,0 +1,1251 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_FPA_DEFS_H__ +#define __CVMX_FPA_DEFS_H__ + +#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) +#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) +#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) +#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) +#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) +#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) +#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) +#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) +#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) +#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) +#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) +#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) +#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) +#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) +#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8 * 1) +#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8 * 1) +#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) +#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) +#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) +#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) +#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) +#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) +#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) +#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) +#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) +#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) +#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) +#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) +#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) +#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) +#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) +#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) +#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) +#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) +#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) +#define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull)) + +union cvmx_fpa_addr_range_error { + u64 u64; + struct cvmx_fpa_addr_range_error_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 pool:5; + u64 addr:33; +#else + u64 addr:33; + u64 pool:5; + u64 reserved_38_63:26; +#endif + } s; +}; + +union cvmx_fpa_bist_status { + u64 u64; + struct cvmx_fpa_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 frd:1; + u64 fpf0:1; + u64 fpf1:1; + u64 ffr:1; + u64 fdr:1; +#else + u64 fdr:1; + u64 ffr:1; + u64 fpf1:1; + u64 fpf0:1; + u64 frd:1; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_fpa_ctl_status { + u64 u64; + struct cvmx_fpa_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 free_en:1; + u64 ret_off:1; + u64 req_off:1; + u64 reset:1; + u64 use_ldt:1; + u64 use_stt:1; + u64 enb:1; + u64 mem1_err:7; + u64 mem0_err:7; +#else + u64 mem0_err:7; + u64 mem1_err:7; + u64 enb:1; + u64 use_stt:1; + u64 use_ldt:1; + u64 reset:1; + u64 req_off:1; + u64 ret_off:1; + u64 free_en:1; + u64 reserved_21_63:43; +#endif + } s; + struct cvmx_fpa_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 reset:1; + u64 use_ldt:1; + u64 use_stt:1; + u64 enb:1; + u64 mem1_err:7; + u64 mem0_err:7; +#else + u64 mem0_err:7; + u64 mem1_err:7; + u64 enb:1; + u64 use_stt:1; + u64 use_ldt:1; + u64 reset:1; + u64 reserved_18_63:46; +#endif + } cn30xx; +}; + +union cvmx_fpa_fpfx_marks { + u64 u64; + struct cvmx_fpa_fpfx_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 fpf_wr:11; + u64 fpf_rd:11; +#else + u64 fpf_rd:11; + u64 fpf_wr:11; + u64 reserved_22_63:42; +#endif + } s; +}; + +union cvmx_fpa_fpfx_size { + u64 u64; + struct cvmx_fpa_fpfx_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 fpf_siz:11; +#else + u64 fpf_siz:11; + u64 reserved_11_63:53; +#endif + } s; +}; + +union cvmx_fpa_fpf0_marks { + u64 u64; + struct cvmx_fpa_fpf0_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 fpf_wr:12; + u64 fpf_rd:12; +#else + u64 fpf_rd:12; + u64 fpf_wr:12; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_fpa_fpf0_size { + u64 u64; + struct cvmx_fpa_fpf0_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 fpf_siz:12; +#else + u64 fpf_siz:12; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_fpa_fpf8_marks { + u64 u64; + struct cvmx_fpa_fpf8_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 fpf_wr:11; + u64 fpf_rd:11; +#else + u64 fpf_rd:11; + u64 fpf_wr:11; + u64 reserved_22_63:42; +#endif + } s; +}; + +union cvmx_fpa_fpf8_size { + u64 u64; + struct cvmx_fpa_fpf8_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 fpf_siz:12; +#else + u64 fpf_siz:12; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_fpa_int_enb { + u64 u64; + struct cvmx_fpa_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_50_63:14; + u64 paddr_e:1; + u64 reserved_44_48:5; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 reserved_44_48:5; + u64 paddr_e:1; + u64 reserved_50_63:14; +#endif + } s; + struct cvmx_fpa_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_enb_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_50_63:14; + u64 paddr_e:1; + u64 res_44:5; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 res_44:5; + u64 paddr_e:1; + u64 reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_enb_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_fpa_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_50_63:14; + u64 paddr_e:1; + u64 pool8th:1; + u64 q8_perr:1; + u64 q8_coff:1; + u64 q8_und:1; + u64 free8:1; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 free8:1; + u64 q8_und:1; + u64 q8_coff:1; + u64 q8_perr:1; + u64 pool8th:1; + u64 paddr_e:1; + u64 reserved_50_63:14; +#endif + } cn68xx; +}; + +union cvmx_fpa_int_sum { + u64 u64; + struct cvmx_fpa_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_50_63:14; + u64 paddr_e:1; + u64 pool8th:1; + u64 q8_perr:1; + u64 q8_coff:1; + u64 q8_und:1; + u64 free8:1; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 free8:1; + u64 q8_und:1; + u64 q8_coff:1; + u64 q8_perr:1; + u64 pool8th:1; + u64 paddr_e:1; + u64 reserved_50_63:14; +#endif + } s; + struct cvmx_fpa_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_fpa_int_sum_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_50_63:14; + u64 paddr_e:1; + u64 reserved_44_48:5; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 reserved_44_48:5; + u64 paddr_e:1; + u64 reserved_50_63:14; +#endif + } cn61xx; + struct cvmx_fpa_int_sum_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 free7:1; + u64 free6:1; + u64 free5:1; + u64 free4:1; + u64 free3:1; + u64 free2:1; + u64 free1:1; + u64 free0:1; + u64 pool7th:1; + u64 pool6th:1; + u64 pool5th:1; + u64 pool4th:1; + u64 pool3th:1; + u64 pool2th:1; + u64 pool1th:1; + u64 pool0th:1; + u64 q7_perr:1; + u64 q7_coff:1; + u64 q7_und:1; + u64 q6_perr:1; + u64 q6_coff:1; + u64 q6_und:1; + u64 q5_perr:1; + u64 q5_coff:1; + u64 q5_und:1; + u64 q4_perr:1; + u64 q4_coff:1; + u64 q4_und:1; + u64 q3_perr:1; + u64 q3_coff:1; + u64 q3_und:1; + u64 q2_perr:1; + u64 q2_coff:1; + u64 q2_und:1; + u64 q1_perr:1; + u64 q1_coff:1; + u64 q1_und:1; + u64 q0_perr:1; + u64 q0_coff:1; + u64 q0_und:1; + u64 fed1_dbe:1; + u64 fed1_sbe:1; + u64 fed0_dbe:1; + u64 fed0_sbe:1; +#else + u64 fed0_sbe:1; + u64 fed0_dbe:1; + u64 fed1_sbe:1; + u64 fed1_dbe:1; + u64 q0_und:1; + u64 q0_coff:1; + u64 q0_perr:1; + u64 q1_und:1; + u64 q1_coff:1; + u64 q1_perr:1; + u64 q2_und:1; + u64 q2_coff:1; + u64 q2_perr:1; + u64 q3_und:1; + u64 q3_coff:1; + u64 q3_perr:1; + u64 q4_und:1; + u64 q4_coff:1; + u64 q4_perr:1; + u64 q5_und:1; + u64 q5_coff:1; + u64 q5_perr:1; + u64 q6_und:1; + u64 q6_coff:1; + u64 q6_perr:1; + u64 q7_und:1; + u64 q7_coff:1; + u64 q7_perr:1; + u64 pool0th:1; + u64 pool1th:1; + u64 pool2th:1; + u64 pool3th:1; + u64 pool4th:1; + u64 pool5th:1; + u64 pool6th:1; + u64 pool7th:1; + u64 free0:1; + u64 free1:1; + u64 free2:1; + u64 free3:1; + u64 free4:1; + u64 free5:1; + u64 free6:1; + u64 free7:1; + u64 reserved_44_63:20; +#endif + } cn63xx; +}; + +union cvmx_fpa_packet_threshold { + u64 u64; + struct cvmx_fpa_packet_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 thresh:32; +#else + u64 thresh:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_fpa_poolx_end_addr { + u64 u64; + struct cvmx_fpa_poolx_end_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 addr:33; +#else + u64 addr:33; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_fpa_poolx_start_addr { + u64 u64; + struct cvmx_fpa_poolx_start_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 addr:33; +#else + u64 addr:33; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_fpa_poolx_threshold { + u64 u64; + struct cvmx_fpa_poolx_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 thresh:32; +#else + u64 thresh:32; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_poolx_threshold_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 thresh:29; +#else + u64 thresh:29; + u64 reserved_29_63:35; +#endif + } cn61xx; +}; + +union cvmx_fpa_quex_available { + u64 u64; + struct cvmx_fpa_quex_available_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 que_siz:32; +#else + u64 que_siz:32; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_fpa_quex_available_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 que_siz:29; +#else + u64 que_siz:29; + u64 reserved_29_63:35; +#endif + } cn30xx; +}; + +union cvmx_fpa_quex_page_index { + u64 u64; + struct cvmx_fpa_quex_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 pg_num:25; +#else + u64 pg_num:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_fpa_que8_page_index { + u64 u64; + struct cvmx_fpa_que8_page_index_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 pg_num:25; +#else + u64 pg_num:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_fpa_que_act { + u64 u64; + struct cvmx_fpa_que_act_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 act_que:3; + u64 act_indx:26; +#else + u64 act_indx:26; + u64 act_que:3; + u64 reserved_29_63:35; +#endif + } s; +}; + +union cvmx_fpa_que_exp { + u64 u64; + struct cvmx_fpa_que_exp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 exp_que:3; + u64 exp_indx:26; +#else + u64 exp_indx:26; + u64 exp_que:3; + u64 reserved_29_63:35; +#endif + } s; +}; + +union cvmx_fpa_wart_ctl { + u64 u64; + struct cvmx_fpa_wart_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 ctl:16; +#else + u64 ctl:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_fpa_wart_status { + u64 u64; + struct cvmx_fpa_wart_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 status:32; +#else + u64 status:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_fpa_wqe_threshold { + u64 u64; + struct cvmx_fpa_wqe_threshold_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 thresh:32; +#else + u64 thresh:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-fpa.h b/drivers/staging/octeon/cvmx-fpa.h new file mode 100644 index 000000000000..8fa98e3a596b --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa.h @@ -0,0 +1,290 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Interface to the hardware Free Pool Allocator. + * + * + */ + +#ifndef __CVMX_FPA_H__ +#define __CVMX_FPA_H__ + +#include + +#include "cvmx-address.h" +#include "cvmx-fpa-defs.h" + +#define CVMX_FPA_NUM_POOLS 8 +#define CVMX_FPA_MIN_BLOCK_SIZE 128 +#define CVMX_FPA_ALIGNMENT 128 + +/** + * Structure describing the data format used for stores to the FPA. + */ +typedef union { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * the (64-bit word) location in scratchpad to write + * to (if len != 0) + */ + u64 scraddr:8; + /* the number of words in the response (0 => no response) */ + u64 len:8; + /* the ID of the device on the non-coherent bus */ + u64 did:8; + /* + * the address that will appear in the first tick on + * the NCB bus. + */ + u64 addr:40; +#else + u64 addr:40; + u64 did:8; + u64 len:8; + u64 scraddr:8; +#endif + } s; +} cvmx_fpa_iobdma_data_t; + +/** + * Structure describing the current state of a FPA pool. + */ +typedef struct { + /* Name it was created under */ + const char *name; + /* Size of each block */ + u64 size; + /* The base memory address of whole block */ + void *base; + /* The number of elements in the pool at creation */ + u64 starting_element_count; +} cvmx_fpa_pool_info_t; + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Return the name of the pool + * + * @pool: Pool to get the name of + * Returns The name + */ +static inline const char *cvmx_fpa_get_name(u64 pool) +{ + return cvmx_fpa_pool_info[pool].name; +} + +/** + * Return the base of the pool + * + * @pool: Pool to get the base of + * Returns The base + */ +static inline void *cvmx_fpa_get_base(u64 pool) +{ + return cvmx_fpa_pool_info[pool].base; +} + +/** + * Check if a pointer belongs to an FPA pool. Return non-zero + * if the supplied pointer is inside the memory controlled by + * an FPA pool. + * + * @pool: Pool to check + * @ptr: Pointer to check + * Returns Non-zero if pointer is in the pool. Zero if not + */ +static inline int cvmx_fpa_is_member(u64 pool, void *ptr) +{ + return ((ptr >= cvmx_fpa_pool_info[pool].base) && + ((char *)ptr < + ((char *)(cvmx_fpa_pool_info[pool].base)) + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count)); +} + +/** + * Enable the FPA for use. Must be performed after any CSR + * configuration but before any other FPA functions. + */ +static inline void cvmx_fpa_enable(void) +{ + union cvmx_fpa_ctl_status status; + + status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); + if (status.s.enb) { + cvmx_dprintf + ("Warning: Enabling FPA when FPA already enabled.\n"); + } + + /* + * Do runtime check as we allow pass1 compiled code to run on + * pass2 chips. + */ + if (cvmx_octeon_is_pass1()) { + union cvmx_fpa_fpfx_marks marks; + int i; + + for (i = 1; i < 8; i++) { + marks.u64 = + cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); + marks.s.fpf_wr = 0xe0; + cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, + marks.u64); + } + + /* Enforce a 10 cycle delay between config and enable */ + __delay(10); + } + + /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */ + status.u64 = 0; + status.s.enb = 1; + cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); +} + +/** + * Get a new block from the FPA + * + * @pool: Pool to get the block from + * Returns Pointer to the block or NULL on failure + */ +static inline void *cvmx_fpa_alloc(u64 pool) +{ + u64 address = + cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); + if (address) + return cvmx_phys_to_ptr(address); + else + return NULL; +} + +/** + * Asynchronously get a new block from the FPA + * + * @scr_addr: Local scratch address to put response in. This is a byte address, + * but must be 8 byte aligned. + * @pool: Pool to get the block from + */ +static inline void cvmx_fpa_async_alloc(u64 scr_addr, u64 pool) +{ + cvmx_fpa_iobdma_data_t data; + + /* + * Hardware only uses 64 bit aligned locations, so convert + * from byte address to 64-bit index + */ + data.s.scraddr = scr_addr >> 3; + data.s.len = 1; + data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool); + data.s.addr = 0; + cvmx_send_single(data.u64); +} + +/** + * Free a block allocated with a FPA pool. Does NOT provide memory + * ordering in cases where the memory block was modified by the core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free_nosync(void *ptr, u64 pool, + u64 num_cache_lines) +{ + cvmx_addr_t newptr; + + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* Prevent GCC from reordering around free */ + barrier(); + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Free a block allocated with a FPA pool. Provides required memory + * ordering in cases where memory block was modified by core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free(void *ptr, u64 pool, + u64 num_cache_lines) +{ + cvmx_addr_t newptr; + + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* + * Make sure that any previous writes to memory go out before + * we free this buffer. This also serves as a barrier to + * prevent GCC from reordering operations to after the + * free. + */ + CVMX_SYNCWS; + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. This should only be + * called by one processor after all hardware has finished + * using the pool. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +u64 cvmx_fpa_shutdown_pool(u64 pool); + +/** + * Get the size of blocks controlled by the pool + * This is resolved to a constant at compile time. + * + * @pool: Pool to access + * Returns Size of the block in bytes + */ +u64 cvmx_fpa_get_block_size(u64 pool); + +#endif /* __CVM_FPA_H__ */ diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/drivers/staging/octeon/cvmx-gmxx-defs.h new file mode 100644 index 000000000000..8e5f552f14f9 --- /dev/null +++ b/drivers/staging/octeon/cvmx-gmxx-defs.h @@ -0,0 +1,2258 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_GMXX_DEFS_H__ +#define __CVMX_GMXX_DEFS_H__ + +static inline u64 CVMX_GMXX_HG2_CONTROL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_INF_MODE(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) + +static inline u64 CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) + +static inline u64 CVMX_GMXX_RX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) +static inline u64 CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048; + } + return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; +} + +static inline u64 CVMX_GMXX_TX_INT_EN(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_TX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_TX_OVR_BP(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; +} + +static inline u64 CVMX_GMXX_TX_PRTS(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; +} + +#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) +static inline u64 CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; +} + +void __cvmx_interrupt_gmxx_enable(int interface); + +union cvmx_gmxx_hg2_control { + u64 u64; + struct cvmx_gmxx_hg2_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 hg2tx_en:1; + u64 hg2rx_en:1; + u64 phys_en:1; + u64 logl_en:16; +#else + u64 logl_en:16; + u64 phys_en:1; + u64 hg2rx_en:1; + u64 hg2tx_en:1; + u64 reserved_19_63:45; +#endif + } s; +}; + +union cvmx_gmxx_inf_mode { + u64 u64; + struct cvmx_gmxx_inf_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 rate:4; + u64 reserved_12_15:4; + u64 speed:4; + u64 reserved_7_7:1; + u64 mode:3; + u64 reserved_3_3:1; + u64 p0mii:1; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 p0mii:1; + u64 reserved_3_3:1; + u64 mode:3; + u64 reserved_7_7:1; + u64 speed:4; + u64 reserved_12_15:4; + u64 rate:4; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_gmxx_inf_mode_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 p0mii:1; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 p0mii:1; + u64 reserved_3_63:61; +#endif + } cn30xx; + struct cvmx_gmxx_inf_mode_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 reserved_2_63:62; +#endif + } cn31xx; + struct cvmx_gmxx_inf_mode_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 speed:2; + u64 reserved_6_7:2; + u64 mode:2; + u64 reserved_2_3:2; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 reserved_2_3:2; + u64 mode:2; + u64 reserved_6_7:2; + u64 speed:2; + u64 reserved_10_63:54; +#endif + } cn52xx; + struct cvmx_gmxx_inf_mode_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 speed:4; + u64 reserved_5_7:3; + u64 mode:1; + u64 reserved_2_3:2; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 reserved_2_3:2; + u64 mode:1; + u64 reserved_5_7:3; + u64 speed:4; + u64 reserved_12_63:52; +#endif + } cn61xx; + struct cvmx_gmxx_inf_mode_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 rate:4; + u64 reserved_12_15:4; + u64 speed:4; + u64 reserved_5_7:3; + u64 mode:1; + u64 reserved_2_3:2; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 reserved_2_3:2; + u64 mode:1; + u64 reserved_5_7:3; + u64 speed:4; + u64 reserved_12_15:4; + u64 rate:4; + u64 reserved_20_63:44; +#endif + } cn66xx; + struct cvmx_gmxx_inf_mode_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 speed:4; + u64 reserved_7_7:1; + u64 mode:3; + u64 reserved_2_3:2; + u64 en:1; + u64 type:1; +#else + u64 type:1; + u64 en:1; + u64 reserved_2_3:2; + u64 mode:3; + u64 reserved_7_7:1; + u64 speed:4; + u64 reserved_12_63:52; +#endif + } cn68xx; +}; + +union cvmx_gmxx_prtx_cfg { + u64 u64; + struct cvmx_gmxx_prtx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 pknd:6; + u64 reserved_14_15:2; + u64 tx_idle:1; + u64 rx_idle:1; + u64 reserved_9_11:3; + u64 speed_msb:1; + u64 reserved_4_7:4; + u64 slottime:1; + u64 duplex:1; + u64 speed:1; + u64 en:1; +#else + u64 en:1; + u64 speed:1; + u64 duplex:1; + u64 slottime:1; + u64 reserved_4_7:4; + u64 speed_msb:1; + u64 reserved_9_11:3; + u64 rx_idle:1; + u64 tx_idle:1; + u64 reserved_14_15:2; + u64 pknd:6; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_gmxx_prtx_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 slottime:1; + u64 duplex:1; + u64 speed:1; + u64 en:1; +#else + u64 en:1; + u64 speed:1; + u64 duplex:1; + u64 slottime:1; + u64 reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_gmxx_prtx_cfg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 tx_idle:1; + u64 rx_idle:1; + u64 reserved_9_11:3; + u64 speed_msb:1; + u64 reserved_4_7:4; + u64 slottime:1; + u64 duplex:1; + u64 speed:1; + u64 en:1; +#else + u64 en:1; + u64 speed:1; + u64 duplex:1; + u64 slottime:1; + u64 reserved_4_7:4; + u64 speed_msb:1; + u64 reserved_9_11:3; + u64 rx_idle:1; + u64 tx_idle:1; + u64 reserved_14_63:50; +#endif + } cn52xx; +}; + +union cvmx_gmxx_rxx_adr_ctl { + u64 u64; + struct cvmx_gmxx_rxx_adr_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 cam_mode:1; + u64 mcst:2; + u64 bcst:1; +#else + u64 bcst:1; + u64 mcst:2; + u64 cam_mode:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_gmxx_rxx_frm_ctl { + u64 u64; + struct cvmx_gmxx_rxx_frm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 ptp_mode:1; + u64 reserved_11_11:1; + u64 null_dis:1; + u64 pre_align:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 pre_align:1; + u64 null_dis:1; + u64 reserved_11_11:1; + u64 ptp_mode:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 pad_len:1; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_gmxx_rxx_frm_ctl_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 reserved_8_63:56; +#endif + } cn31xx; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 null_dis:1; + u64 pre_align:1; + u64 reserved_7_8:2; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 reserved_7_8:2; + u64 pre_align:1; + u64 null_dis:1; + u64 reserved_11_63:53; +#endif + } cn50xx; + struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pre_align:1; + u64 reserved_7_8:2; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 reserved_7_8:2; + u64 pre_align:1; + u64 reserved_10_63:54; +#endif + } cn56xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 null_dis:1; + u64 pre_align:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 pre_align:1; + u64 null_dis:1; + u64 reserved_11_63:53; +#endif + } cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 ptp_mode:1; + u64 reserved_11_11:1; + u64 null_dis:1; + u64 pre_align:1; + u64 reserved_7_8:2; + u64 pre_free:1; + u64 ctl_smac:1; + u64 ctl_mcst:1; + u64 ctl_bck:1; + u64 ctl_drp:1; + u64 pre_strp:1; + u64 pre_chk:1; +#else + u64 pre_chk:1; + u64 pre_strp:1; + u64 ctl_drp:1; + u64 ctl_bck:1; + u64 ctl_mcst:1; + u64 ctl_smac:1; + u64 pre_free:1; + u64 reserved_7_8:2; + u64 pre_align:1; + u64 null_dis:1; + u64 reserved_11_11:1; + u64 ptp_mode:1; + u64 reserved_13_63:51; +#endif + } cn61xx; +}; + +union cvmx_gmxx_rxx_frm_max { + u64 u64; + struct cvmx_gmxx_rxx_frm_max_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 len:16; +#else + u64 len:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_gmxx_rxx_frm_min { + u64 u64; + struct cvmx_gmxx_rxx_frm_min_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 len:16; +#else + u64 len:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_gmxx_rxx_int_en { + u64 u64; + struct cvmx_gmxx_rxx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } s; + struct cvmx_gmxx_rxx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 reserved_19_63:45; +#endif + } cn30xx; + struct cvmx_gmxx_rxx_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_6_6:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 reserved_6_6:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn50xx; + struct cvmx_gmxx_rxx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } cn52xx; + struct cvmx_gmxx_rxx_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 reserved_27_63:37; +#endif + } cn56xxp1; + struct cvmx_gmxx_rxx_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn58xx; + struct cvmx_gmxx_rxx_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } cn61xx; +}; + +union cvmx_gmxx_rxx_int_reg { + u64 u64; + struct cvmx_gmxx_rxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } s; + struct cvmx_gmxx_rxx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 reserved_19_63:45; +#endif + } cn30xx; + struct cvmx_gmxx_rxx_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_6_6:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 reserved_6_6:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn50xx; + struct cvmx_gmxx_rxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } cn52xx; + struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 reserved_27_63:37; +#endif + } cn56xxp1; + struct cvmx_gmxx_rxx_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pause_drp:1; + u64 phy_dupx:1; + u64 phy_spd:1; + u64 phy_link:1; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 niberr:1; + u64 skperr:1; + u64 rcverr:1; + u64 lenerr:1; + u64 alnerr:1; + u64 fcserr:1; + u64 jabber:1; + u64 maxerr:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 maxerr:1; + u64 jabber:1; + u64 fcserr:1; + u64 alnerr:1; + u64 lenerr:1; + u64 rcverr:1; + u64 skperr:1; + u64 niberr:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 phy_link:1; + u64 phy_spd:1; + u64 phy_dupx:1; + u64 pause_drp:1; + u64 reserved_20_63:44; +#endif + } cn58xx; + struct cvmx_gmxx_rxx_int_reg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 hg2cc:1; + u64 hg2fld:1; + u64 undat:1; + u64 uneop:1; + u64 unsop:1; + u64 bad_term:1; + u64 bad_seq:1; + u64 rem_fault:1; + u64 loc_fault:1; + u64 pause_drp:1; + u64 reserved_16_18:3; + u64 ifgerr:1; + u64 coldet:1; + u64 falerr:1; + u64 rsverr:1; + u64 pcterr:1; + u64 ovrerr:1; + u64 reserved_9_9:1; + u64 skperr:1; + u64 rcverr:1; + u64 reserved_5_6:2; + u64 fcserr:1; + u64 jabber:1; + u64 reserved_2_2:1; + u64 carext:1; + u64 minerr:1; +#else + u64 minerr:1; + u64 carext:1; + u64 reserved_2_2:1; + u64 jabber:1; + u64 fcserr:1; + u64 reserved_5_6:2; + u64 rcverr:1; + u64 skperr:1; + u64 reserved_9_9:1; + u64 ovrerr:1; + u64 pcterr:1; + u64 rsverr:1; + u64 falerr:1; + u64 coldet:1; + u64 ifgerr:1; + u64 reserved_16_18:3; + u64 pause_drp:1; + u64 loc_fault:1; + u64 rem_fault:1; + u64 bad_seq:1; + u64 bad_term:1; + u64 unsop:1; + u64 uneop:1; + u64 undat:1; + u64 hg2fld:1; + u64 hg2cc:1; + u64 reserved_29_63:35; +#endif + } cn61xx; +}; + +union cvmx_gmxx_rxx_jabber { + u64 u64; + struct cvmx_gmxx_rxx_jabber_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt:16; +#else + u64 cnt:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_gmxx_rxx_rx_inbnd { + u64 u64; + struct cvmx_gmxx_rxx_rx_inbnd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 duplex:1; + u64 speed:2; + u64 status:1; +#else + u64 status:1; + u64 speed:2; + u64 duplex:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_gmxx_rx_prts { + u64 u64; + struct cvmx_gmxx_rx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 prts:3; +#else + u64 prts:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_gmxx_rx_xaui_ctl { + u64 u64; + struct cvmx_gmxx_rx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 status:2; +#else + u64 status:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_gmxx_txx_thresh { + u64 u64; + struct cvmx_gmxx_txx_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 cnt:10; +#else + u64 cnt:10; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_gmxx_txx_thresh_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 cnt:7; +#else + u64 cnt:7; + u64 reserved_7_63:57; +#endif + } cn30xx; + struct cvmx_gmxx_txx_thresh_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 cnt:9; +#else + u64 cnt:9; + u64 reserved_9_63:55; +#endif + } cn38xx; +}; + +union cvmx_gmxx_tx_int_en { + u64 u64; + struct cvmx_gmxx_tx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } s; + struct cvmx_gmxx_tx_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 late_col:3; + u64 reserved_15_15:1; + u64 xsdef:3; + u64 reserved_11_11:1; + u64 xscol:3; + u64 reserved_5_7:3; + u64 undflw:3; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:3; + u64 reserved_5_7:3; + u64 xscol:3; + u64 reserved_11_11:1; + u64 xsdef:3; + u64 reserved_15_15:1; + u64 late_col:3; + u64 reserved_19_63:45; +#endif + } cn30xx; + struct cvmx_gmxx_tx_int_en_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 xsdef:3; + u64 reserved_11_11:1; + u64 xscol:3; + u64 reserved_5_7:3; + u64 undflw:3; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:3; + u64 reserved_5_7:3; + u64 xscol:3; + u64 reserved_11_11:1; + u64 xsdef:3; + u64 reserved_15_63:49; +#endif + } cn31xx; + struct cvmx_gmxx_tx_int_en_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 ncb_nxa:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 ncb_nxa:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 reserved_20_63:44; +#endif + } cn38xx; + struct cvmx_gmxx_tx_int_en_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 ncb_nxa:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 ncb_nxa:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 reserved_16_63:48; +#endif + } cn38xxp2; + struct cvmx_gmxx_tx_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 reserved_20_63:44; +#endif + } cn52xx; + struct cvmx_gmxx_tx_int_en_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_en_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 pko_nxp:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 pko_nxp:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_en_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 reserved_22_23:2; + u64 ptp_lost:2; + u64 reserved_18_19:2; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_19:2; + u64 ptp_lost:2; + u64 reserved_22_23:2; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } cnf71xx; +}; + +union cvmx_gmxx_tx_int_reg { + u64 u64; + struct cvmx_gmxx_tx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } s; + struct cvmx_gmxx_tx_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 late_col:3; + u64 reserved_15_15:1; + u64 xsdef:3; + u64 reserved_11_11:1; + u64 xscol:3; + u64 reserved_5_7:3; + u64 undflw:3; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:3; + u64 reserved_5_7:3; + u64 xscol:3; + u64 reserved_11_11:1; + u64 xsdef:3; + u64 reserved_15_15:1; + u64 late_col:3; + u64 reserved_19_63:45; +#endif + } cn30xx; + struct cvmx_gmxx_tx_int_reg_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 xsdef:3; + u64 reserved_11_11:1; + u64 xscol:3; + u64 reserved_5_7:3; + u64 undflw:3; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:3; + u64 reserved_5_7:3; + u64 xscol:3; + u64 reserved_11_11:1; + u64 xsdef:3; + u64 reserved_15_63:49; +#endif + } cn31xx; + struct cvmx_gmxx_tx_int_reg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 ncb_nxa:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 ncb_nxa:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 reserved_20_63:44; +#endif + } cn38xx; + struct cvmx_gmxx_tx_int_reg_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 ncb_nxa:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 ncb_nxa:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 reserved_16_63:48; +#endif + } cn38xxp2; + struct cvmx_gmxx_tx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 reserved_20_63:44; +#endif + } cn52xx; + struct cvmx_gmxx_tx_int_reg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_gmxx_tx_int_reg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 ptp_lost:4; + u64 late_col:4; + u64 xsdef:4; + u64 xscol:4; + u64 reserved_6_7:2; + u64 undflw:4; + u64 pko_nxp:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 pko_nxp:1; + u64 undflw:4; + u64 reserved_6_7:2; + u64 xscol:4; + u64 xsdef:4; + u64 late_col:4; + u64 ptp_lost:4; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } cn68xx; + struct cvmx_gmxx_tx_int_reg_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 xchange:1; + u64 reserved_22_23:2; + u64 ptp_lost:2; + u64 reserved_18_19:2; + u64 late_col:2; + u64 reserved_14_15:2; + u64 xsdef:2; + u64 reserved_10_11:2; + u64 xscol:2; + u64 reserved_4_7:4; + u64 undflw:2; + u64 reserved_1_1:1; + u64 pko_nxa:1; +#else + u64 pko_nxa:1; + u64 reserved_1_1:1; + u64 undflw:2; + u64 reserved_4_7:4; + u64 xscol:2; + u64 reserved_10_11:2; + u64 xsdef:2; + u64 reserved_14_15:2; + u64 late_col:2; + u64 reserved_18_19:2; + u64 ptp_lost:2; + u64 reserved_22_23:2; + u64 xchange:1; + u64 reserved_25_63:39; +#endif + } cnf71xx; +}; + +union cvmx_gmxx_tx_ovr_bp { + u64 u64; + struct cvmx_gmxx_tx_ovr_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 tx_prt_bp:16; + u64 reserved_12_31:20; + u64 en:4; + u64 bp:4; + u64 ign_full:4; +#else + u64 ign_full:4; + u64 bp:4; + u64 en:4; + u64 reserved_12_31:20; + u64 tx_prt_bp:16; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_gmxx_tx_ovr_bp_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 en:3; + u64 reserved_7_7:1; + u64 bp:3; + u64 reserved_3_3:1; + u64 ign_full:3; +#else + u64 ign_full:3; + u64 reserved_3_3:1; + u64 bp:3; + u64 reserved_7_7:1; + u64 en:3; + u64 reserved_11_63:53; +#endif + } cn30xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 en:4; + u64 bp:4; + u64 ign_full:4; +#else + u64 ign_full:4; + u64 bp:4; + u64 en:4; + u64 reserved_12_63:52; +#endif + } cn38xx; + struct cvmx_gmxx_tx_ovr_bp_cnf71xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 tx_prt_bp:16; + u64 reserved_10_31:22; + u64 en:2; + u64 reserved_6_7:2; + u64 bp:2; + u64 reserved_2_3:2; + u64 ign_full:2; +#else + u64 ign_full:2; + u64 reserved_2_3:2; + u64 bp:2; + u64 reserved_6_7:2; + u64 en:2; + u64 reserved_10_31:22; + u64 tx_prt_bp:16; + u64 reserved_48_63:16; +#endif + } cnf71xx; +}; + +union cvmx_gmxx_tx_prts { + u64 u64; + struct cvmx_gmxx_tx_prts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 prts:5; +#else + u64 prts:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_gmxx_tx_spi_ctl { + u64 u64; + struct cvmx_gmxx_tx_spi_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 tpa_clr:1; + u64 cont_pkt:1; +#else + u64 cont_pkt:1; + u64 tpa_clr:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_gmxx_tx_spi_max { + u64 u64; + struct cvmx_gmxx_tx_spi_max_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 slice:7; + u64 max2:8; + u64 max1:8; +#else + u64 max1:8; + u64 max2:8; + u64 slice:7; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_gmxx_tx_spi_max_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 max2:8; + u64 max1:8; +#else + u64 max1:8; + u64 max2:8; + u64 reserved_16_63:48; +#endif + } cn38xx; +}; + +union cvmx_gmxx_tx_spi_thresh { + u64 u64; + struct cvmx_gmxx_tx_spi_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 thresh:6; +#else + u64 thresh:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_gmxx_tx_xaui_ctl { + u64 u64; + struct cvmx_gmxx_tx_xaui_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 hg_pause_hgi:2; + u64 hg_en:1; + u64 reserved_7_7:1; + u64 ls_byp:1; + u64 ls:2; + u64 reserved_2_3:2; + u64 uni_en:1; + u64 dic_en:1; +#else + u64 dic_en:1; + u64 uni_en:1; + u64 reserved_2_3:2; + u64 ls:2; + u64 ls_byp:1; + u64 reserved_7_7:1; + u64 hg_en:1; + u64 hg_pause_hgi:2; + u64 reserved_11_63:53; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-gpio-defs.h b/drivers/staging/octeon/cvmx-gpio-defs.h new file mode 100644 index 000000000000..0692ad75a79f --- /dev/null +++ b/drivers/staging/octeon/cvmx-gpio-defs.h @@ -0,0 +1,398 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_GPIO_DEFS_H__ +#define __CVMX_GPIO_DEFS_H__ + +#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) +#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) +#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) +#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) +#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) +#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) +#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) +#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) +#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) +#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) +#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) +#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) +#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8 * 16) + +union cvmx_gpio_bit_cfgx { + u64 u64; + struct cvmx_gpio_bit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:42; + u64 output_sel:5; + u64 synce_sel:2; + u64 clk_gen:1; + u64 clk_sel:2; + u64 fil_sel:4; + u64 fil_cnt:4; + u64 int_type:1; + u64 int_en:1; + u64 rx_xor:1; + u64 tx_oe:1; +#else + u64 tx_oe:1; + u64 rx_xor:1; + u64 int_en:1; + u64 int_type:1; + u64 fil_cnt:4; + u64 fil_sel:4; + u64 clk_sel:2; + u64 clk_gen:1; + u64 synce_sel:2; + u64 output_sel:5; + u64 reserved_21_63:42; +#endif + } s; + struct cvmx_gpio_bit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 fil_sel:4; + u64 fil_cnt:4; + u64 int_type:1; + u64 int_en:1; + u64 rx_xor:1; + u64 tx_oe:1; +#else + u64 tx_oe:1; + u64 rx_xor:1; + u64 int_en:1; + u64 int_type:1; + u64 fil_cnt:4; + u64 fil_sel:4; + u64 reserved_12_63:52; +#endif + } cn30xx; + struct cvmx_gpio_bit_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 clk_gen:1; + u64 clk_sel:2; + u64 fil_sel:4; + u64 fil_cnt:4; + u64 int_type:1; + u64 int_en:1; + u64 rx_xor:1; + u64 tx_oe:1; +#else + u64 tx_oe:1; + u64 rx_xor:1; + u64 int_en:1; + u64 int_type:1; + u64 fil_cnt:4; + u64 fil_sel:4; + u64 clk_sel:2; + u64 clk_gen:1; + u64 reserved_15_63:49; +#endif + } cn52xx; +}; + +union cvmx_gpio_boot_ena { + u64 u64; + struct cvmx_gpio_boot_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 boot_ena:4; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 boot_ena:4; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_gpio_clk_genx { + u64 u64; + struct cvmx_gpio_clk_genx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 n:32; +#else + u64 n:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_gpio_clk_qlmx { + u64 u64; + struct cvmx_gpio_clk_qlmx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 qlm_sel:3; + u64 reserved_3_7:5; + u64 div:1; + u64 lane_sel:2; +#else + u64 lane_sel:2; + u64 div:1; + u64 reserved_3_7:5; + u64 qlm_sel:3; + u64 reserved_11_63:53; +#endif + } s; + struct cvmx_gpio_clk_qlmx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 qlm_sel:2; + u64 reserved_3_7:5; + u64 div:1; + u64 lane_sel:2; +#else + u64 lane_sel:2; + u64 div:1; + u64 reserved_3_7:5; + u64 qlm_sel:2; + u64 reserved_10_63:54; +#endif + } cn61xx; + struct cvmx_gpio_clk_qlmx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 div:1; + u64 lane_sel:2; +#else + u64 lane_sel:2; + u64 div:1; + u64 reserved_3_63:61; +#endif + } cn63xx; +}; + +union cvmx_gpio_dbg_ena { + u64 u64; + struct cvmx_gpio_dbg_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 dbg_ena:21; +#else + u64 dbg_ena:21; + u64 reserved_21_63:43; +#endif + } s; +}; + +union cvmx_gpio_int_clr { + u64 u64; + struct cvmx_gpio_int_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 type:16; +#else + u64 type:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_gpio_multi_cast { + u64 u64; + struct cvmx_gpio_multi_cast_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 en:1; +#else + u64 en:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_gpio_pin_ena { + u64 u64; + struct cvmx_gpio_pin_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 ena19:1; + u64 ena18:1; + u64 reserved_0_17:18; +#else + u64 reserved_0_17:18; + u64 ena18:1; + u64 ena19:1; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_gpio_rx_dat { + u64 u64; + struct cvmx_gpio_rx_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 dat:24; +#else + u64 dat:24; + u64 reserved_24_63:40; +#endif + } s; + struct cvmx_gpio_rx_dat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dat:16; +#else + u64 dat:16; + u64 reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_gpio_rx_dat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 dat:20; +#else + u64 dat:20; + u64 reserved_20_63:44; +#endif + } cn61xx; +}; + +union cvmx_gpio_tim_ctl { + u64 u64; + struct cvmx_gpio_tim_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 sel:4; +#else + u64 sel:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_gpio_tx_clr { + u64 u64; + struct cvmx_gpio_tx_clr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 clr:24; +#else + u64 clr:24; + u64 reserved_24_63:40; +#endif + } s; + struct cvmx_gpio_tx_clr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 clr:16; +#else + u64 clr:16; + u64 reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_gpio_tx_clr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 clr:20; +#else + u64 clr:20; + u64 reserved_20_63:44; +#endif + } cn61xx; +}; + +union cvmx_gpio_tx_set { + u64 u64; + struct cvmx_gpio_tx_set_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 set:24; +#else + u64 set:24; + u64 reserved_24_63:40; +#endif + } s; + struct cvmx_gpio_tx_set_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 set:16; +#else + u64 set:16; + u64 reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_gpio_tx_set_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 set:20; +#else + u64 set:20; + u64 reserved_20_63:44; +#endif + } cn61xx; +}; + +union cvmx_gpio_xbit_cfgx { + u64 u64; + struct cvmx_gpio_xbit_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 synce_sel:2; + u64 clk_gen:1; + u64 clk_sel:2; + u64 fil_sel:4; + u64 fil_cnt:4; + u64 int_type:1; + u64 int_en:1; + u64 rx_xor:1; + u64 tx_oe:1; +#else + u64 tx_oe:1; + u64 rx_xor:1; + u64 int_en:1; + u64 int_type:1; + u64 fil_cnt:4; + u64 fil_sel:4; + u64 clk_sel:2; + u64 clk_gen:1; + u64 synce_sel:2; + u64 reserved_17_63:47; +#endif + } s; + struct cvmx_gpio_xbit_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 fil_sel:4; + u64 fil_cnt:4; + u64 reserved_2_3:2; + u64 rx_xor:1; + u64 tx_oe:1; +#else + u64 tx_oe:1; + u64 rx_xor:1; + u64 reserved_2_3:2; + u64 fil_cnt:4; + u64 fil_sel:4; + u64 reserved_12_63:52; +#endif + } cn30xx; +}; + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c similarity index 61% rename from arch/mips/cavium-octeon/executive/cvmx-helper-board.c rename to drivers/staging/octeon/cvmx-helper-board.c index 0fd9ac76eb74..e64dc23e914d 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +++ b/drivers/staging/octeon/cvmx-helper-board.c @@ -1,65 +1,64 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * - * Helper functions to abstract board specific data about - * network ports from the rest of the cvmx-helper files. - */ + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + */ #include -#include -#include +#include "octeon.h" +#include "cvmx-bootinfo.h" -#include +#include "cvmx-config.h" -#include -#include -#include +#include "cvmx-helper.h" +#include "cvmx-helper-util.h" +#include "cvmx-helper-board.h" -#include -#include +#include "cvmx-gmxx-defs.h" +#include "cvmx-asxx-defs.h" /* - * Return the MII PHY address associated with the given IPD - * port. A result of -1 means there isn't a MII capable PHY - * connected to this port. On chips supporting multiple MII - * busses the bus number is encoded in bits <15:8>. - * - * This function must be modified for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It replies on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: Octeon IPD port to get the MII address for. - * - * Returns MII PHY address and bus number or -1. - */ + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It replies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ int cvmx_helper_board_get_mii_address(int ipd_port) { switch (cvmx_sysinfo_get()->board_type) { @@ -179,7 +178,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port) return 1; else return -1; - } /* Some unknown board. Somebody forgot to update this function... */ @@ -190,29 +188,29 @@ int cvmx_helper_board_get_mii_address(int ipd_port) } /* - * This function is the board specific method of determining an - * ethernet ports link speed. Most Octeon boards have Marvell PHYs - * and are handled by the fall through case. This function must be - * updated for boards that don't have the normal Marvell PHYs. - * - * This function must be modified for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relies on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: IPD input port associated with the port we want to get link - * status for. - * - * Returns The ports link status. If the link isn't fully resolved, this must - * return zero. - */ + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port) { union cvmx_helper_link_info result; WARN_ONCE(!octeon_is_simulation(), - "Using deprecated link status - please update your DT"); + "Using deprecated link status - please update your DT"); /* Unless we fix it later, all links are defaulted to down */ result.u64 = 0; @@ -225,9 +223,9 @@ union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port) return result; } - if (OCTEON_IS_MODEL(OCTEON_CN3XXX) - || OCTEON_IS_MODEL(OCTEON_CN58XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || + OCTEON_IS_MODEL(OCTEON_CN58XX) || + OCTEON_IS_MODEL(OCTEON_CN50XX)) { /* * We don't have a PHY address, so attempt to use * in-band status. It is really important that boards @@ -238,6 +236,7 @@ union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port) union cvmx_gmxx_rxx_rx_inbnd inband_status; int interface = cvmx_helper_get_interface_num(ipd_port); int index = cvmx_helper_get_interface_index_num(ipd_port); + inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); @@ -275,26 +274,26 @@ union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port) } /* - * This function is called by cvmx_helper_interface_probe() after it - * determines the number of ports Octeon can support on a specific - * interface. This function is the per board location to override - * this value. It is called with the number of ports Octeon might - * support and should return the number of actual ports on the - * board. - * - * This function must be modified for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relies on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @interface: Interface to probe - * @supported_ports: - * Number of ports Octeon supports. - * - * Returns Number of ports the actual board supports. Many times this will - * simple be "support_ports". - */ + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ int __cvmx_helper_board_interface_probe(int interface, int supported_ports) { switch (cvmx_sysinfo_get()->board_type) { @@ -321,11 +320,11 @@ int __cvmx_helper_board_interface_probe(int interface, int supported_ports) } /* - * Get the clock type used for the USB block based on board type. - * Used by the USB code for auto configuration of clock type. - * - * Return USB clock type enumeration - */ + * Get the clock type used for the USB block based on board type. + * Used by the USB code for auto configuration of clock type. + * + * Return USB clock type enumeration + */ enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void) { switch (cvmx_sysinfo_get()->board_type) { diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/drivers/staging/octeon/cvmx-helper-board.h new file mode 100644 index 000000000000..ed8df10497c3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-board.h @@ -0,0 +1,123 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + * + */ +#ifndef __CVMX_HELPER_BOARD_H__ +#define __CVMX_HELPER_BOARD_H__ + +#include "cvmx-helper.h" + +enum cvmx_helper_board_usb_clock_types { + USB_CLOCK_TYPE_REF_12, + USB_CLOCK_TYPE_REF_24, + USB_CLOCK_TYPE_REF_48, + USB_CLOCK_TYPE_CRYSTAL_12, +}; + +typedef enum { + set_phy_link_flags_autoneg = 0x1, + set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, + set_phy_link_flags_flow_control_enable = 0x1 << 1, + set_phy_link_flags_flow_control_disable = 0x2 << 1, + set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ +} cvmx_helper_board_set_phy_link_flags_types_t; + +/* + * Fake IPD port, the RGMII/MII interface may use different PHY, use + * this macro to return appropriate MIX address to read the PHY. + */ +#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 + +/** + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ +int cvmx_helper_board_get_mii_address(int ipd_port); + +/** + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ +union cvmx_helper_link_info __cvmx_helper_board_link_get(int ipd_port); + +/** + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ +int __cvmx_helper_board_interface_probe(int interface, + int supported_ports); + +enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void); + +#endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-errata.c b/drivers/staging/octeon/cvmx-helper-errata.c new file mode 100644 index 000000000000..9c72a3ca029b --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-errata.c @@ -0,0 +1,73 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Fixes and workaround for Octeon chip errata. This file + * contains functions called by cvmx-helper to workaround known + * chip errata. For the most part, code doesn't need to call + * these functions directly. + * + */ +#include + +#include "octeon.h" + +#include "cvmx-helper-jtag.h" + +/** + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass + * 1 doesn't work properly. The following code disables 2nd order + * CDR for the specified QLM. + * + * @qlm: QLM to disable 2nd order CDR for. + */ +void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm) +{ + int lane; + + cvmx_helper_qlm_jtag_init(); + /* We need to load all four lanes of the QLM, a total of 1072 bits */ + for (lane = 0; lane < 4; lane++) { + /* + * Each lane has 268 bits. We need to set + * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> = + * 1. All other bits are zero. Bits go in LSB first, + * so start off with the zeros for bits <63:0>. + */ + cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1); + /* cfg_cdr_incx<67:64>=3 */ + cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3); + /* Zeros for bits <76:68> */ + cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1); + /* cfg_cdr_secord<77>=1 */ + cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1); + /* Zeros for bits <267:78> */ + cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1); + } + cvmx_helper_qlm_jtag_update(qlm); +} +EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr); diff --git a/drivers/staging/octeon/cvmx-helper-errata.h b/drivers/staging/octeon/cvmx-helper-errata.h new file mode 100644 index 000000000000..fabfac2bc305 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-errata.h @@ -0,0 +1,32 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_HELPER_ERRATA_H__ +#define __CVMX_HELPER_ERRATA_H__ + +void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-jtag.c b/drivers/staging/octeon/cvmx-helper-jtag.c new file mode 100644 index 000000000000..fe8f2dc744e9 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-jtag.c @@ -0,0 +1,145 @@ + +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Helper utilities for qlm_jtag. + * + */ + +#include "octeon.h" +#include "cvmx-helper-jtag.h" + +/** + * Initialize the internal QLM JTAG logic to allow programming + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions. + * These functions should only be used at the direction of Cavium + * Networks. Programming incorrect values into the JTAG chain + * can cause chip damage. + */ +void cvmx_helper_qlm_jtag_init(void) +{ + union cvmx_ciu_qlm_jtgc jtgc; + u32 clock_div = 0; + u32 divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); + + divisor = (divisor - 1) >> 2; + /* Convert the divisor into a power of 2 shift */ + while (divisor) { + clock_div++; + divisor = divisor >> 1; + } + + /* + * Clock divider for QLM JTAG operations. eclk is divided by + * 2^(CLK_DIV + 2) + */ + jtgc.u64 = 0; + jtgc.s.clk_div = clock_div; + jtgc.s.mux_sel = 0; + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + jtgc.s.bypass = 0x3; + else + jtgc.s.bypass = 0xf; + cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); + cvmx_read_csr(CVMX_CIU_QLM_JTGC); +} + +/** + * Write up to 32bits into the QLM jtag chain. Bits are shifted + * into the MSB and out the LSB, so you should shift in the low + * order bits followed by the high order bits. The JTAG chain is + * 4 * 268 bits long, or 1072. + * + * @qlm: QLM to shift value into + * @bits: Number of bits to shift in (1-32). + * @data: Data to shift in. Bit 0 enters the chain first, followed by + * bit 1, etc. + * + * Returns The low order bits of the JTAG chain that shifted out of the + * circle. + */ +u32 cvmx_helper_qlm_jtag_shift(int qlm, int bits, u32 data) +{ + union cvmx_ciu_qlm_jtgd jtgd; + + jtgd.u64 = 0; + jtgd.s.shift = 1; + jtgd.s.shft_cnt = bits - 1; + jtgd.s.shft_reg = data; + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) + jtgd.s.select = 1 << qlm; + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); + do { + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); + } while (jtgd.s.shift); + return jtgd.s.shft_reg >> (32 - bits); +} + +/** + * Shift long sequences of zeros into the QLM JTAG chain. It is + * common to need to shift more than 32 bits of zeros into the + * chain. This function is a convenience wrapper around + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of + * zeros at a time. + * + * @qlm: QLM to shift zeros into + * @bits: + */ +void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) +{ + while (bits > 0) { + int n = bits; + + if (n > 32) + n = 32; + cvmx_helper_qlm_jtag_shift(qlm, n, 0); + bits -= n; + } +} + +/** + * Program the QLM JTAG chain into all lanes of the QLM. You must + * have already shifted in 268*4, or 1072 bits into the JTAG + * chain. Updating invalid values can possibly cause chip damage. + * + * @qlm: QLM to program + */ +void cvmx_helper_qlm_jtag_update(int qlm) +{ + union cvmx_ciu_qlm_jtgd jtgd; + + /* Update the new data */ + jtgd.u64 = 0; + jtgd.s.update = 1; + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) + jtgd.s.select = 1 << qlm; + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); + do { + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); + } while (jtgd.s.update); +} diff --git a/drivers/staging/octeon/cvmx-helper-jtag.h b/drivers/staging/octeon/cvmx-helper-jtag.h new file mode 100644 index 000000000000..3e55639b960b --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-jtag.h @@ -0,0 +1,42 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper utilities for qlm_jtag. + * + */ + +#ifndef __CVMX_HELPER_JTAG_H__ +#define __CVMX_HELPER_JTAG_H__ + +void cvmx_helper_qlm_jtag_init(void); +u32 cvmx_helper_qlm_jtag_shift(int qlm, int bits, u32 data); +void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits); +void cvmx_helper_qlm_jtag_update(int qlm); + +#endif /* __CVMX_HELPER_JTAG_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/drivers/staging/octeon/cvmx-helper-loop.c new file mode 100644 index 000000000000..a72757221f05 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.c @@ -0,0 +1,85 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for LOOP initialization, configuration, + * and monitoring. + */ +#include "octeon.h" + +#include "cvmx-config.h" + +#include "cvmx-helper.h" +#include "cvmx-pip-defs.h" + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_loop_probe(int interface) +{ + union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; + int num_ports = 4; + int port; + + /* We need to disable length checking so packet < 64 bytes and jumbo + frames don't get errors */ + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = cvmx_helper_get_ipd_port(interface, port); + + port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); + } + + /* Disable FCS stripping for loopback ports */ + ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); + ipd_sub_port_fcs.s.port_bit2 = 0; + cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); + return num_ports; +} + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_loop_enable(int interface) +{ + /* Do nothing. */ + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/drivers/staging/octeon/cvmx-helper-loop.h new file mode 100644 index 000000000000..88e0a83e6d6a --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.h @@ -0,0 +1,59 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as published by + * the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for LOOP initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_LOOP_H__ +#define __CVMX_HELPER_LOOP_H__ + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_loop_probe(int interface); +static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; } + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_loop_enable(int interface); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/drivers/staging/octeon/cvmx-helper-npi.c new file mode 100644 index 000000000000..bd1c70f5f5b2 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.c @@ -0,0 +1,101 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for NPI initialization, configuration, + * and monitoring. + */ +#include "octeon.h" + +#include "cvmx-config.h" + +#include "cvmx-helper.h" + +#include "cvmx-pip-defs.h" + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_npi_probe(int interface) +{ +#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) && + !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) && + !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; +#endif + return 0; +} + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_npi_enable(int interface) +{ + /* + * On CN50XX, CN52XX, and CN56XX we need to disable length + * checking so packet < 64 bytes and jumbo frames don't get + * errors. + */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && + !OCTEON_IS_MODEL(OCTEON_CN58XX)) { + int num_ports = cvmx_helper_ports_on_interface(interface); + int port; + + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = + cvmx_helper_get_ipd_port(interface, port); + port_cfg.u64 = + cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), + port_cfg.u64); + } + } + + /* Enables are controlled by the remote host, so nothing to do here */ + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/drivers/staging/octeon/cvmx-helper-npi.h new file mode 100644 index 000000000000..7a6a78d9f030 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.h @@ -0,0 +1,60 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for NPI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_NPI_H__ +#define __CVMX_HELPER_NPI_H__ + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_npi_probe(int interface); +#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_npi_enable(int interface); + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/drivers/staging/octeon/cvmx-helper-rgmii.c similarity index 75% rename from arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c rename to drivers/staging/octeon/cvmx-helper-rgmii.c index a8c3be4eb6f0..aa22ce389cbb 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c +++ b/drivers/staging/octeon/cvmx-helper-rgmii.c @@ -1,68 +1,67 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (C) 2003-2018 Cavium, Inc. - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Functions for RGMII/GMII/MII initialization, configuration, - * and monitoring. - */ -#include + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + */ +#include "octeon.h" -#include +#include "cvmx-config.h" -#include -#include -#include +#include "cvmx-pko.h" +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" -#include -#include -#include -#include +#include "cvmx-npi-defs.h" +#include "cvmx-gmxx-defs.h" +#include "cvmx-asxx-defs.h" +#include "cvmx-dbg-defs.h" /* - * Probe RGMII ports and determine the number present - * - * @interface: Interface to probe - * - * Returns Number of RGMII/GMII/MII ports (0-4). - */ + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ int __cvmx_helper_rgmii_probe(int interface) { int num_ports = 0; union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); if (mode.s.type) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) { - cvmx_dprintf("ERROR: RGMII initialize called in " - "SPI interface\n"); - } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN58XX)) { + cvmx_dprintf("ERROR: RGMII initialize called in SPI interface\n"); + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || + OCTEON_IS_MODEL(OCTEON_CN30XX) || + OCTEON_IS_MODEL(OCTEON_CN50XX)) { /* * On these chips "type" says we're in * GMII/MII mode. This limits us to 2 ports @@ -73,12 +72,12 @@ int __cvmx_helper_rgmii_probe(int interface) __func__); } } else { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN58XX)) { num_ports = 4; - } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || + OCTEON_IS_MODEL(OCTEON_CN30XX) || + OCTEON_IS_MODEL(OCTEON_CN50XX)) { num_ports = 3; } else { cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", @@ -89,19 +88,20 @@ int __cvmx_helper_rgmii_probe(int interface) } /* - * Put an RGMII interface in loopback mode. Internal packets sent - * out will be received back again on the same port. Externally - * received packets will echo back out. - * - * @port: IPD port number to loop. - */ + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ void cvmx_helper_rgmii_internal_loopback(int port) { int interface = (port >> 4) & 1; int index = port & 0xf; - uint64_t tmp; + u64 tmp; union cvmx_gmxx_prtx_cfg gmx_cfg; + gmx_cfg.u64 = 0; gmx_cfg.s.duplex = 1; gmx_cfg.s.slottime = 1; @@ -121,15 +121,15 @@ void cvmx_helper_rgmii_internal_loopback(int port) } /* - * Workaround ASX setup errata with CN38XX pass1 - * - * @interface: Interface to setup - * @port: Port to setup (0..3) - * @cpu_clock_hz: - * Chip frequency in Hertz - * - * Returns Zero on success, negative on failure - */ + * Workaround ASX setup errata with CN38XX pass1 + * + * @interface: Interface to setup + * @port: Port to setup (0..3) + * @cpu_clock_hz: + * Chip frequency in Hertz + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz) { @@ -143,19 +143,19 @@ static int __cvmx_helper_errata_asx_pass1(int interface, int port, else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000) cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); else - cvmx_dprintf("Illegal clock frequency (%d). " - "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz); + cvmx_dprintf("Illegal clock frequency (%d). CVMX_ASXX_TX_HI_WATERX not set\n", + cpu_clock_hz); return 0; } /* - * Configure all of the ASX, GMX, and PKO registers required - * to get RGMII to function on the supplied interface. - * - * @interface: PKO Interface to configure (0 or 1) - * - * Returns Zero on success - */ + * Configure all of the ASX, GMX, and PKO registers required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ int __cvmx_helper_rgmii_enable(int interface) { int num_ports = cvmx_helper_ports_on_interface(interface); @@ -199,6 +199,7 @@ int __cvmx_helper_rgmii_enable(int interface) * feature. */ union cvmx_gmxx_rxx_frm_ctl frm_ctl; + frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL (port, interface)); @@ -252,15 +253,15 @@ int __cvmx_helper_rgmii_enable(int interface) } /* - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ union cvmx_helper_link_info __cvmx_helper_rgmii_link_get(int ipd_port) { int interface = cvmx_helper_get_interface_num(ipd_port); @@ -271,6 +272,7 @@ union cvmx_helper_link_info __cvmx_helper_rgmii_link_get(int ipd_port) if (asxx_prt_loop.s.int_loop & (1 << index)) { /* Force 1Gbps full duplex on internal loopback */ union cvmx_helper_link_info result; + result.u64 = 0; result.s.full_duplex = 1; result.s.link_up = 1; @@ -281,16 +283,16 @@ union cvmx_helper_link_info __cvmx_helper_rgmii_link_get(int ipd_port) } /* - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_rgmii_link_set(int ipd_port, union cvmx_helper_link_info link_info) { @@ -323,6 +325,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, /* Disable all queues so that TX should become idle */ for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); pko_mem_queue_qos.s.pid = ipd_port; @@ -350,9 +353,9 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_write_csr(CVMX_NPI_DBG_SELECT, interface * 0x800 + index * 0x100 + 0x880); CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, - ==, 0, 10000); + ==, 0, 10000); CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, - ==, 0, 10000); + ==, 0, 10000); /* Disable the port before we make any changes */ new_gmx_cfg.s.en = 0; @@ -399,6 +402,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) { union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); /* @@ -413,8 +417,8 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, */ /* In MII mode, CLK_CNT = 1. */ - if (((index == 0) && (mode.s.p0mii == 1)) - || ((index != 0) && (mode.s.type == 1))) { + if (((index == 0) && (mode.s.p0mii == 1)) || + ((index != 0) && (mode.s.type == 1))) { cvmx_write_csr(CVMX_GMXX_TXX_CLK (index, interface), 1); } @@ -435,6 +439,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port, /* Re-enable the TX path */ for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos_save[i].u64); diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/drivers/staging/octeon/cvmx-helper-rgmii.h new file mode 100644 index 000000000000..feb01ff6cf2a --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-rgmii.h @@ -0,0 +1,92 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_RGMII_H__ +#define __CVMX_HELPER_RGMII_H__ + +/** + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ +int __cvmx_helper_rgmii_probe(int interface); +#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe + +/** + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ +void cvmx_helper_rgmii_internal_loopback(int port); + +/** + * Configure all of the ASX, GMX, and PKO registers required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ +int __cvmx_helper_rgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info __cvmx_helper_rgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_rgmii_link_set(int ipd_port, + union cvmx_helper_link_info link_info); + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/drivers/staging/octeon/cvmx-helper-sgmii.c similarity index 75% rename from arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c rename to drivers/staging/octeon/cvmx-helper-sgmii.c index e07d8f15efba..2dc3a0338d89 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/drivers/staging/octeon/cvmx-helper-sgmii.c @@ -1,57 +1,56 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (C) 2003-2018 Cavium, Inc. - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Functions for SGMII initialization, configuration, - * and monitoring. - */ + * Functions for SGMII initialization, configuration, + * and monitoring. + */ -#include +#include "octeon.h" -#include +#include "cvmx-config.h" -#include -#include +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" -#include -#include -#include +#include "cvmx-gmxx-defs.h" +#include "cvmx-pcsx-defs.h" +#include "cvmx-pcsxx-defs.h" /** - * Perform initialization required only once for an SGMII port. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * - * Returns Zero on success, negative on failure - */ + * Perform initialization required only once for an SGMII port. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) { - const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; + const u64 clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg; union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; @@ -94,6 +93,7 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) if (pcs_misc_ctl_reg.s.mode) { /* 1000BASE-X */ union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg; + pcsx_anx_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); pcsx_anx_adv_reg.s.rem_flt = 0; @@ -104,11 +104,13 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) pcsx_anx_adv_reg.u64); } else { union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); if (pcsx_miscx_ctl_reg.s.mac_phy) { /* PHY Mode */ union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg; + pcsx_sgmx_an_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG (index, interface)); @@ -126,14 +128,14 @@ static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) } /** - * Initialize the SERTES link for the first time or after a loss - * of link. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * - * Returns Zero on success, negative on failure - */ + * Initialize the SERTES link for the first time or after a loss + * of link. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) { union cvmx_pcsx_mrx_control_reg control_reg; @@ -155,9 +157,8 @@ static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) if (CVMX_WAIT_FOR_FIELD64 (CVMX_PCSX_MRX_CONTROL_REG(index, interface), union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { - cvmx_dprintf("SGMII%d: Timeout waiting for port %d " - "to finish reset\n", - interface, index); + cvmx_dprintf("SGMII%d: Timeout waiting for port %d to finish reset\n", + interface, index); return -1; } } @@ -189,15 +190,15 @@ static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) } /** - * Configure an SGMII link to the specified speed after the SERTES - * link is up. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * @link_info: Link state to configure - * - * Returns Zero on success, negative on failure - */ + * Configure an SGMII link to the specified speed after the SERTES + * link is up. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * @link_info: Link state to configure + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index, union cvmx_helper_link_info @@ -216,9 +217,9 @@ static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, /* Wait for GMX to be idle */ if (CVMX_WAIT_FOR_FIELD64 (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg, - rx_idle, ==, 1, 10000) - || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), - union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, + rx_idle, ==, 1, 10000) || + CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), + union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, 10000)) { cvmx_dprintf ("SGMII%d: Timeout waiting for port %d to be idle\n", @@ -295,15 +296,15 @@ static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, } /** - * Bring up the SGMII interface to be ready for packet I/O but - * leave I/O disabled using the GMX override. This function - * follows the bringup documented in 10.6.3 of the manual. - * - * @interface: Interface to bringup - * @num_ports: Number of ports on the interface - * - * Returns Zero on success, negative on failure - */ + * Bring up the SGMII interface to be ready for packet I/O but + * leave I/O disabled using the GMX override. This function + * follows the bringup documented in 10.6.3 of the manual. + * + * @interface: Interface to bringup + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) { int index; @@ -312,6 +313,7 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) for (index = 0; index < num_ports; index++) { int ipd_port = cvmx_helper_get_ipd_port(interface, index); + __cvmx_helper_sgmii_hardware_init_one_time(interface, index); /* Linux kernel driver will call ....link_set with the * proper link state. In the simulator there is no @@ -320,7 +322,7 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) */ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) __cvmx_helper_sgmii_link_set(ipd_port, - __cvmx_helper_sgmii_link_get(ipd_port)); + __cvmx_helper_sgmii_link_get(ipd_port)); } return 0; @@ -330,15 +332,16 @@ int __cvmx_helper_sgmii_enumerate(int interface) { return 4; } + /** - * Probe a SGMII interface and determine the number of ports - * connected to it. The SGMII interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ int __cvmx_helper_sgmii_probe(int interface) { union cvmx_gmxx_inf_mode mode; @@ -355,14 +358,14 @@ int __cvmx_helper_sgmii_probe(int interface) } /** - * Bringup and enable a SGMII interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_sgmii_enable(int interface) { int num_ports = cvmx_helper_ports_on_interface(interface); @@ -372,6 +375,7 @@ int __cvmx_helper_sgmii_enable(int interface) for (index = 0; index < num_ports; index++) { union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); gmxx_prtx_cfg.s.en = 1; @@ -385,15 +389,15 @@ int __cvmx_helper_sgmii_enable(int interface) } /** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port) { union cvmx_helper_link_info result; @@ -429,6 +433,7 @@ union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port) /* FIXME */ } else { union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); if (pcsx_miscx_ctl_reg.s.mac_phy) { @@ -494,21 +499,22 @@ union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port) } /** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_sgmii_link_set(int ipd_port, union cvmx_helper_link_info link_info) { int interface = cvmx_helper_get_interface_num(ipd_port); int index = cvmx_helper_get_interface_index_num(ipd_port); + __cvmx_helper_sgmii_hardware_init_link(interface, index); return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, link_info); diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/drivers/staging/octeon/cvmx-helper-sgmii.h new file mode 100644 index 000000000000..17e09e58ed24 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-sgmii.h @@ -0,0 +1,86 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for SGMII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_SGMII_H__ +#define __CVMX_HELPER_SGMII_H__ + +/** + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_sgmii_probe(int interface); +int __cvmx_helper_sgmii_enumerate(int interface); + +/** + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info __cvmx_helper_sgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_link_set(int ipd_port, + union cvmx_helper_link_info link_info); + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/drivers/staging/octeon/cvmx-helper-spi.c similarity index 56% rename from arch/mips/cavium-octeon/executive/cvmx-helper-spi.c rename to drivers/staging/octeon/cvmx-helper-spi.c index 525914e9b22d..8735be78a9ba 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/drivers/staging/octeon/cvmx-helper-spi.c @@ -1,50 +1,49 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (C) 2003-2018 Cavium, Inc. - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Functions for SPI initialization, configuration, - * and monitoring. - */ -#include + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#include "octeon.h" -#include -#include -#include +#include "cvmx-config.h" +#include "cvmx-spi.h" +#include "cvmx-helper.h" -#include -#include -#include -#include +#include "cvmx-pip-defs.h" +#include "cvmx-pko-defs.h" +#include "cvmx-spxx-defs.h" +#include "cvmx-stxx-defs.h" /* - * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI - * initialization routines wait for SPI training. You can override the - * value using executive-config.h if necessary. - */ + * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI + * initialization routines wait for SPI training. You can override the + * value using executive-config.h if necessary. + */ #ifndef CVMX_HELPER_SPI_TIMEOUT #define CVMX_HELPER_SPI_TIMEOUT 10 #endif @@ -60,14 +59,14 @@ int __cvmx_helper_spi_enumerate(int interface) } /** - * Probe a SPI interface and determine the number of ports - * connected to it. The SPI interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ int __cvmx_helper_spi_probe(int interface) { int num_ports = 0; @@ -77,6 +76,7 @@ int __cvmx_helper_spi_probe(int interface) num_ports = 10; } else { union cvmx_pko_reg_crc_enable enable; + num_ports = 16; /* * Unlike the SPI4000, most SPI devices don't @@ -93,14 +93,14 @@ int __cvmx_helper_spi_probe(int interface) } /** - * Bringup and enable a SPI interface. After this call packet I/O - * should be fully functional. This is called with IPD enabled but - * PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_spi_enable(int interface) { /* @@ -110,9 +110,11 @@ int __cvmx_helper_spi_enable(int interface) */ int num_ports = cvmx_helper_ports_on_interface(interface); int ipd_port; + for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; ipd_port++) { union cvmx_pip_prt_cfgx port_config; + port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); port_config.s.crc_en = 1; cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); @@ -131,20 +133,21 @@ int __cvmx_helper_spi_enable(int interface) } /** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ union cvmx_helper_link_info __cvmx_helper_spi_link_get(int ipd_port) { union cvmx_helper_link_info result; int interface = cvmx_helper_get_interface_num(ipd_port); int index = cvmx_helper_get_interface_index_num(ipd_port); + result.u64 = 0; if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { @@ -183,16 +186,16 @@ union cvmx_helper_link_info __cvmx_helper_spi_link_get(int ipd_port) } /** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_spi_link_set(int ipd_port, union cvmx_helper_link_info link_info) { /* Nothing to do. If we have a SPI4000 then the setup was already performed diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/drivers/staging/octeon/cvmx-helper-spi.h new file mode 100644 index 000000000000..7ee449ab29a0 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-spi.h @@ -0,0 +1,83 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#ifndef __CVMX_HELPER_SPI_H__ +#define __CVMX_HELPER_SPI_H__ + +/** + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_spi_probe(int interface); +int __cvmx_helper_spi_enumerate(int interface); + +/** + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info __cvmx_helper_spi_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_link_set(int ipd_port, + union cvmx_helper_link_info link_info); + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c similarity index 64% rename from arch/mips/cavium-octeon/executive/cvmx-helper-util.c rename to drivers/staging/octeon/cvmx-helper-util.c index 53b912745dbd..dd36afdf32ff 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c +++ b/drivers/staging/octeon/cvmx-helper-util.c @@ -1,57 +1,56 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Small helper utilities. - */ + * Small helper utilities. + */ #include -#include +#include "octeon.h" -#include +#include "cvmx-config.h" -#include -#include -#include -#include -#include +#include "cvmx-fpa.h" +#include "cvmx-pip.h" +#include "cvmx-pko.h" +#include "cvmx-ipd.h" +#include "cvmx-spi.h" -#include -#include +#include "cvmx-helper.h" +#include "cvmx-helper-util.h" -#include +#include "cvmx-ipd-defs.h" /** - * Convert a interface mode into a human readable string - * - * @mode: Mode to convert - * - * Returns String - */ + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode) { @@ -81,17 +80,17 @@ const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t } /** - * Setup Random Early Drop on a specific input queue - * - * @queue: Input queue to setup RED on (0-7) - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incoming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ + * Setup Random Early Drop on a specific input queue + * + * @queue: Input queue to setup RED on (0-7) + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ static int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) { @@ -118,16 +117,16 @@ static int cvmx_helper_setup_red_queue(int queue, int pass_thresh, } /** - * Setup Random Early Drop to automatically begin dropping packets. - * - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incoming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) { union cvmx_ipd_portx_bp_page_cnt page_cnt; @@ -168,15 +167,15 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) EXPORT_SYMBOL_GPL(cvmx_helper_setup_red); /** - * Setup the common GMX settings that determine the number of - * ports. These setting apply to almost all configurations of all - * chips. - * - * @interface: Interface to configure - * @num_ports: Number of ports on the interface - * - * Returns Zero on success, negative on failure - */ + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ int __cvmx_helper_setup_gmx(int interface, int num_ports) { union cvmx_gmxx_tx_prts gmx_tx_prts; @@ -193,16 +192,15 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports) /* Tell GMX the number of RX ports on this interface. This only ** applies to *GMII and XAUI ports */ if (cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_RGMII - || cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_SGMII - || cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_GMII - || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_RGMII || + cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_SGMII || + cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_GMII || + cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_XAUI) { if (num_ports > 4) { - cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal " - "num_ports\n"); + cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal num_ports\n"); return -1; } @@ -212,8 +210,8 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports) } /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ - if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) - && !OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && + !OCTEON_IS_MODEL(OCTEON_CN50XX)) { /* Tell PKO the number of ports on this interface */ pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); if (interface == 0) { @@ -250,8 +248,8 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports) * memory load. */ gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); - if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || + OCTEON_IS_MODEL(OCTEON_CN50XX)) { /* These chips have a fixed max threshold of 0x40 */ gmx_tx_thresh.s.cnt = 0x40; } else { @@ -277,14 +275,14 @@ int __cvmx_helper_setup_gmx(int interface, int num_ports) } /** - * Returns the IPD/PKO port number for a port on the given - * interface. - * - * @interface: Interface to use - * @port: Port on the interface - * - * Returns IPD/PKO port number - */ + * Returns the IPD/PKO port number for a port on the given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ int cvmx_helper_get_ipd_port(int interface, int port) { switch (interface) { @@ -306,12 +304,12 @@ int cvmx_helper_get_ipd_port(int interface, int port) EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port); /** - * Returns the interface number for an IPD/PKO port number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface number - */ + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ int cvmx_helper_get_interface_num(int ipd_port) { if (ipd_port < 16) @@ -327,21 +325,20 @@ int cvmx_helper_get_interface_num(int ipd_port) else if (ipd_port < 48) return 5; else - cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD " - "port number\n"); + cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n"); return -1; } EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num); /** - * Returns the interface index number for an IPD/PKO port - * number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface index number - */ + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ int cvmx_helper_get_interface_index_num(int ipd_port) { if (ipd_port < 32) @@ -355,8 +352,7 @@ int cvmx_helper_get_interface_index_num(int ipd_port) else if (ipd_port < 48) return ipd_port & 3; else - cvmx_dprintf("cvmx_helper_get_interface_index_num: " - "Illegal IPD port number\n"); + cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n"); return -1; } diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/drivers/staging/octeon/cvmx-helper-util.h new file mode 100644 index 000000000000..84fa116ceb8e --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-util.h @@ -0,0 +1,191 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Small helper utilities. + * + */ + +#ifndef __CVMX_HELPER_UTIL_H__ +#define __CVMX_HELPER_UTIL_H__ + +/** + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ +extern const char + *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode); + +/** + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incoming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); + +/** + * Get the version of the CVMX libraries. + * + * Returns Version string. Note this buffer is allocated statically + * and will be shared by all callers. + */ +const char *cvmx_helper_get_version(void); + +/** + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_setup_gmx(int interface, int num_ports); + +/** + * Returns the IPD/PKO port number for a port on the given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ +int cvmx_helper_get_ipd_port(int interface, int port); + +/** + * Returns the IPD/PKO port number for the first port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_first_ipd_port(int interface) +{ + return cvmx_helper_get_ipd_port(interface, 0); +} + +/** + * Returns the IPD/PKO port number for the last port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_last_ipd_port(int interface) +{ + int cvmx_helper_ports_on_interface(int interface); + + return cvmx_helper_get_first_ipd_port(interface) + + cvmx_helper_ports_on_interface(interface) - 1; +} + +/** + * Free the packet buffers contained in a work queue entry. + * The work queue entry is not freed. + * + * @work: Work queue entry with packet to free + */ +static inline void cvmx_helper_free_packet_data(struct cvmx_wqe *work) +{ + u64 number_buffers; + union cvmx_buf_ptr buffer_ptr; + union cvmx_buf_ptr next_buffer_ptr; + u64 start_of_buffer; + + number_buffers = work->word2.s.bufs; + if (number_buffers == 0) + return; + buffer_ptr = work->packet_ptr; + + /* + * Since the number of buffers is not zero, we know this is + * not a dynamic short packet. We need to check if it is a + * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is + * true, we need to free all buffers except for the first + * one. The caller doesn't expect their WQE pointer to be + * freed + */ + start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + if (cvmx_ptr_to_phys(work) == start_of_buffer) { + next_buffer_ptr = + *(union cvmx_buf_ptr *)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + buffer_ptr = next_buffer_ptr; + number_buffers--; + } + + while (number_buffers--) { + /* + * Remember the back pointer is in cache lines, not + * 64bit words + */ + start_of_buffer = + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + /* + * Read pointer to next buffer before we free the + * current buffer. + */ + next_buffer_ptr = + *(union cvmx_buf_ptr *)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), + buffer_ptr.s.pool, 0); + buffer_ptr = next_buffer_ptr; + } +} + +/** + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ +int cvmx_helper_get_interface_num(int ipd_port); + +/** + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ +int cvmx_helper_get_interface_index_num(int ipd_port); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/drivers/staging/octeon/cvmx-helper-xaui.c new file mode 100644 index 000000000000..66062f645b3d --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.c @@ -0,0 +1,322 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ + +#include "octeon.h" + +#include "cvmx-config.h" + +#include "cvmx-helper.h" + +#include "cvmx-pko-defs.h" +#include "cvmx-gmxx-defs.h" +#include "cvmx-pcsx-defs.h" +#include "cvmx-pcsxx-defs.h" + +int __cvmx_helper_xaui_enumerate(int interface) +{ + union cvmx_gmxx_hg2_control gmx_hg2_control; + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + +/* + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_xaui_probe(int interface) +{ + int i; + union cvmx_gmxx_inf_mode mode; + + /* + * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the + * interface needs to be enabled before IPD otherwise per port + * backpressure may not work properly. + */ + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + mode.s.en = 1; + cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); + + __cvmx_helper_setup_gmx(interface, 1); + + /* + * Setup PKO to support 16 ports for HiGig2 virtual + * ports. We're pointing all of the PKO packet ports for this + * interface to the XAUI. This allows us to use HiGig2 + * backpressure per port. + */ + for (i = 0; i < 16; i++) { + union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs; + + pko_mem_port_ptrs.u64 = 0; + /* + * We set each PKO port to have equal priority in a + * round robin fashion. + */ + pko_mem_port_ptrs.s.static_p = 0; + pko_mem_port_ptrs.s.qos_mask = 0xff; + /* All PKO ports map to the same XAUI hardware port */ + pko_mem_port_ptrs.s.eid = interface * 4; + pko_mem_port_ptrs.s.pid = interface * 16 + i; + cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); + } + return __cvmx_helper_xaui_enumerate(interface); +} + +/* + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_enable(int interface) +{ + union cvmx_gmxx_prtx_cfg gmx_cfg; + union cvmx_pcsxx_control1_reg xauiCtl; + union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl; + union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl; + union cvmx_gmxx_rxx_int_en gmx_rx_int_en; + union cvmx_gmxx_tx_int_en gmx_tx_int_en; + union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; + + /* Setup PKND */ + if (octeon_has_feature(OCTEON_FEATURE_PKND)) { + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + } + + /* (1) Interface has already been enabled. */ + + /* (2) Disable GMX. */ + xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); + xauiMiscCtl.s.gmxeno = 1; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + /* (3) Disable GMX and PCSX interrupts. */ + gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + + /* (4) Bring up the PCSX and GMX reconciliation layer. */ + /* (4)a Set polarity and lane swapping. */ + /* (4)b */ + gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + /* Enable better IFG packing and improves performance */ + gmxXauiTxCtl.s.dic_en = 1; + gmxXauiTxCtl.s.uni_en = 0; + cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); + + /* (4)c Aply reset sequence */ + xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); + xauiCtl.s.lo_pwr = 0; + + /* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */ + if (!OCTEON_IS_MODEL(OCTEON_CN66XX) && + !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) && + !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)) + xauiCtl.s.reset = 1; + + cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); + + /* Wait for PCS to come out of reset */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg, + reset, ==, 0, 10000)) + return -1; + /* Wait for PCS to be aligned */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_10GBX_STATUS_REG(interface), + union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000)) + return -1; + /* Wait for RX to be ready */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl, + status, ==, 0, 10000)) + return -1; + + /* (6) Configure GMX */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* Wait for GMX RX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + rx_idle, ==, 1, 10000)) + return -1; + /* Wait for GMX TX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + tx_idle, ==, 1, 10000)) + return -1; + + /* GMX configure */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.speed = 1; + gmx_cfg.s.speed_msb = 0; + gmx_cfg.s.slottime = 1; + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* (7) Clear out any error state */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), + cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); + cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), + cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); + cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), + cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); + + /* Wait for receive link */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg, + rcv_lnk, ==, 1, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + xmtflt, ==, 0, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + rcvflt, ==, 0, 10000)) + return -1; + + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); + + /* (8) Enable packet reception */ + xauiMiscCtl.s.gmxeno = 0; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface); + __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + + return 0; +} + +/* + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info __cvmx_helper_xaui_link_get(int ipd_port) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + union cvmx_pcsxx_status1_reg pcsxx_status1_reg; + union cvmx_helper_link_info result; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + pcsxx_status1_reg.u64 = + cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); + result.u64 = 0; + + /* Only return a link if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) && + (pcsxx_status1_reg.s.rcv_lnk == 1)) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } else { + /* Disable GMX and PCSX interrupts. */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + } + return result; +} + +/* + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_link_set(int ipd_port, union cvmx_helper_link_info link_info) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + + /* If the link shouldn't be up, then just return */ + if (!link_info.s.link_up) + return 0; + + /* Do nothing if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0)) + return 0; + + /* Bring the link up */ + return __cvmx_helper_xaui_enable(interface); +} diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/drivers/staging/octeon/cvmx-helper-xaui.h new file mode 100644 index 000000000000..ffc987082ba9 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.h @@ -0,0 +1,86 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_XAUI_H__ +#define __CVMX_HELPER_XAUI_H__ + +/** + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_xaui_probe(int interface); +int __cvmx_helper_xaui_enumerate(int interface); + +/** + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info __cvmx_helper_xaui_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_link_set(int ipd_port, + union cvmx_helper_link_info link_info); + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/drivers/staging/octeon/cvmx-helper.c similarity index 78% rename from arch/mips/cavium-octeon/executive/cvmx-helper.c rename to drivers/staging/octeon/cvmx-helper.c index 9abfc4bf9bd8..51fda38bd616 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/drivers/staging/octeon/cvmx-helper.c @@ -1,62 +1,61 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * - * Helper functions for common, but complicated tasks. - * - */ + * + * Helper functions for common, but complicated tasks. + * + */ #include -#include +#include "octeon.h" -#include +#include "cvmx-config.h" -#include -#include -#include -#include -#include -#include -#include +#include "cvmx-fpa.h" +#include "cvmx-pip.h" +#include "cvmx-pko.h" +#include "cvmx-ipd.h" +#include "cvmx-spi.h" +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" -#include -#include +#include "cvmx-pip-defs.h" +#include "cvmx-asxx-defs.h" /* Port count per interface */ static int interface_port_count[9]; /** - * Return the number of interfaces the chip has. Each interface - * may have multiple ports. Most chips support two interfaces, - * but the CNX0XX and CNX1XX are exceptions. These only support - * one interface. - * - * Returns Number of interfaces on chip - */ + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ int cvmx_helper_get_number_of_interfaces(void) { if (OCTEON_IS_MODEL(OCTEON_CN68XX)) @@ -77,14 +76,14 @@ int cvmx_helper_get_number_of_interfaces(void) EXPORT_SYMBOL_GPL(cvmx_helper_get_number_of_interfaces); /** - * Return the number of ports on an interface. Depending on the - * chip and configuration, this can be 1-16. A value of 0 - * specifies that the interface doesn't exist or isn't usable. - * - * @interface: Interface to get the port count for - * - * Returns Number of ports on interface. Can be Zero. - */ + * Return the number of ports on an interface. Depending on the + * chip and configuration, this can be 1-16. A value of 0 + * specifies that the interface doesn't exist or isn't usable. + * + * @interface: Interface to get the port count for + * + * Returns Number of ports on interface. Can be Zero. + */ int cvmx_helper_ports_on_interface(int interface) { return interface_port_count[interface]; @@ -92,12 +91,13 @@ int cvmx_helper_ports_on_interface(int interface) EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface); /** - * @INTERNAL - * Return interface mode for CN68xx. - */ + * @INTERNAL + * Return interface mode for CN68xx. + */ static cvmx_helper_interface_mode_t __cvmx_get_mode_cn68xx(int interface) { union cvmx_mio_qlmx_cfg qlm_cfg; + switch (interface) { case 0: qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); @@ -144,9 +144,9 @@ static cvmx_helper_interface_mode_t __cvmx_get_mode_cn68xx(int interface) } /** - * @INTERNAL - * Return interface mode for an Octeon II - */ + * @INTERNAL + * Return interface mode for an Octeon II + */ static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface) { union cvmx_gmxx_inf_mode mode; @@ -211,6 +211,7 @@ static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface) } else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) { if (interface == 0) { union cvmx_mio_qlmx_cfg qlm_cfg; + qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); if (qlm_cfg.s.qlm_cfg == 2) return CVMX_HELPER_INTERFACE_MODE_SGMII; @@ -244,9 +245,9 @@ static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface) } /** - * @INTERNAL - * Return interface mode for CN7XXX. - */ + * @INTERNAL + * Return interface mode for CN7XXX. + */ static cvmx_helper_interface_mode_t __cvmx_get_mode_cn7xxx(int interface) { union cvmx_gmxx_inf_mode mode; @@ -280,15 +281,15 @@ static cvmx_helper_interface_mode_t __cvmx_get_mode_cn7xxx(int interface) } /** - * Get the operating mode of an interface. Depending on the Octeon - * chip and configuration, this function returns an enumeration - * of the type of packet I/O supported by an interface. - * - * @interface: Interface to probe - * - * Returns Mode of the interface. Unknown or unsupported interfaces return - * DISABLED. - */ + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) { union cvmx_gmxx_inf_mode mode; @@ -316,18 +317,18 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) return CVMX_HELPER_INTERFACE_MODE_NPI; if (interface == 3) { - if (OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || + OCTEON_IS_MODEL(OCTEON_CN52XX)) return CVMX_HELPER_INTERFACE_MODE_LOOP; else return CVMX_HELPER_INTERFACE_MODE_DISABLED; } /* Interface 1 is always disabled on CN31XX and CN30XX */ - if ((interface == 1) - && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX))) + if ((interface == 1) && + (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || + OCTEON_IS_MODEL(OCTEON_CN50XX) || + OCTEON_IS_MODEL(OCTEON_CN52XX))) return CVMX_HELPER_INTERFACE_MODE_DISABLED; mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); @@ -350,8 +351,8 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) return CVMX_HELPER_INTERFACE_MODE_DISABLED; if (mode.s.type) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN58XX)) return CVMX_HELPER_INTERFACE_MODE_SPI; else return CVMX_HELPER_INTERFACE_MODE_GMII; @@ -362,16 +363,16 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) EXPORT_SYMBOL_GPL(cvmx_helper_interface_get_mode); /** - * Configure the IPD/PIP tagging and QoS options for a specific - * port. This function determines the POW work queue entry - * contents for a port. The setup performed here is controlled by - * the defines in executive-config.h. - * - * @ipd_port: Port to configure. This follows the IPD numbering, not the - * per interface numbering - * - * Returns Zero on success, negative on failure - */ + * Configure the IPD/PIP tagging and QoS options for a specific + * port. This function determines the POW work queue entry + * contents for a port. The setup performed here is controlled by + * the defines in executive-config.h. + * + * @ipd_port: Port to configure. This follows the IPD numbering, not the + * per interface numbering + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_port_setup_ipd(int ipd_port) { union cvmx_pip_prt_cfgx port_config; @@ -411,14 +412,14 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port) } /** - * This function sets the interface_port_count[interface] correctly, - * without modifying any hardware configuration. Hardware setup of - * the ports will be performed later. - * - * @interface: Interface to probe - * - * Returns Zero on success, negative on failure - */ + * This function sets the interface_port_count[interface] correctly, + * without modifying any hardware configuration. Hardware setup of + * the ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ int cvmx_helper_interface_enumerate(int interface) { switch (cvmx_helper_interface_get_mode(interface)) { @@ -485,16 +486,16 @@ int cvmx_helper_interface_enumerate(int interface) } /** - * This function probes an interface to determine the actual - * number of hardware ports connected to it. It doesn't setup the - * ports or enable them. The main goal here is to set the global - * interface_port_count[interface] correctly. Hardware setup of the - * ports will be performed later. - * - * @interface: Interface to probe - * - * Returns Zero on success, negative on failure - */ + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ int cvmx_helper_interface_probe(int interface) { cvmx_helper_interface_enumerate(interface); @@ -553,15 +554,15 @@ int cvmx_helper_interface_probe(int interface) } /** - * Setup the IPD/PIP for the ports on an interface. Packet - * classification and tagging are set for every port on the - * interface. The number of ports on the interface must already - * have been probed. - * - * @interface: Interface to setup IPD/PIP for - * - * Returns Zero on success, negative on failure - */ + * Setup the IPD/PIP for the ports on an interface. Packet + * classification and tagging are set for every port on the + * interface. The number of ports on the interface must already + * have been probed. + * + * @interface: Interface to setup IPD/PIP for + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_interface_setup_ipd(int interface) { int ipd_port = cvmx_helper_get_ipd_port(interface, 0); @@ -575,11 +576,11 @@ static int __cvmx_helper_interface_setup_ipd(int interface) } /** - * Setup global setting for IPD/PIP not related to a specific - * interface or port. This must be called before IPD is enabled. - * - * Returns Zero on success, negative on failure. - */ + * Setup global setting for IPD/PIP not related to a specific + * interface or port. This must be called before IPD is enabled. + * + * Returns Zero on success, negative on failure. + */ static int __cvmx_helper_global_setup_ipd(void) { /* Setup the global packet input options */ @@ -597,14 +598,14 @@ static int __cvmx_helper_global_setup_ipd(void) } /** - * Setup the PKO for the ports on an interface. The number of - * queues per port and the priority of each PKO output queue - * is set here. PKO must be disabled when this function is called. - * - * @interface: Interface to setup PKO for - * - * Returns Zero on success, negative on failure - */ + * Setup the PKO for the ports on an interface. The number of + * queues per port and the priority of each PKO output queue + * is set here. PKO must be disabled when this function is called. + * + * @interface: Interface to setup PKO for + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_interface_setup_pko(int interface) { /* @@ -619,8 +620,8 @@ static int __cvmx_helper_interface_setup_pko(int interface) * the second half. With per-core PKO queues (PKO lockless * operation) all queues have the same priority. */ - uint64_t priorities[16] = - { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; + u64 priorities[16] = { + 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; /* * Setup the IPD/PIP and PKO for the ports discovered @@ -629,6 +630,7 @@ static int __cvmx_helper_interface_setup_pko(int interface) */ int ipd_port = cvmx_helper_get_ipd_port(interface, 0); int num_ports = interface_port_count[interface]; + while (num_ports--) { cvmx_pko_config_port(ipd_port, cvmx_pko_get_base_queue_per_core(ipd_port, @@ -641,11 +643,11 @@ static int __cvmx_helper_interface_setup_pko(int interface) } /** - * Setup global setting for PKO not related to a specific - * interface or port. This must be called before PKO is enabled. - * - * Returns Zero on success, negative on failure. - */ + * Setup global setting for PKO not related to a specific + * interface or port. This must be called before PKO is enabled. + * + * Returns Zero on success, negative on failure. + */ static int __cvmx_helper_global_setup_pko(void) { /* @@ -653,6 +655,7 @@ static int __cvmx_helper_global_setup_pko(void) * anyone might start packet output using tags. */ union cvmx_iob_fau_timeout fau_to; + fau_to.u64 = 0; fau_to.s.tout_val = 0xfff; fau_to.s.tout_enb = 0; @@ -676,10 +679,10 @@ static int __cvmx_helper_global_setup_pko(void) } /** - * Setup global backpressure setting. - * - * Returns Zero on success, negative on failure - */ + * Setup global backpressure setting. + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_global_setup_backpressure(void) { #if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE @@ -687,6 +690,7 @@ static int __cvmx_helper_global_setup_backpressure(void) /* Disable backpressure (pause frame) generation */ int num_interfaces = cvmx_helper_get_number_of_interfaces(); int interface; + for (interface = 0; interface < num_interfaces; interface++) { switch (cvmx_helper_interface_get_mode(interface)) { case CVMX_HELPER_INTERFACE_MODE_DISABLED: @@ -710,19 +714,20 @@ static int __cvmx_helper_global_setup_backpressure(void) } /** - * Enable packet input/output from the hardware. This function is - * called after all internal setup is complete and IPD is enabled. - * After this function completes, packets will be accepted from the - * hardware ports. PKO should still be disabled to make sure packets - * aren't sent out partially setup hardware. - * - * @interface: Interface to enable - * - * Returns Zero on success, negative on failure - */ + * Enable packet input/output from the hardware. This function is + * called after all internal setup is complete and IPD is enabled. + * After this function completes, packets will be accepted from the + * hardware ports. PKO should still be disabled to make sure packets + * aren't sent out partially setup hardware. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ static int __cvmx_helper_packet_hardware_enable(int interface) { int result = 0; + switch (cvmx_helper_interface_get_mode(interface)) { /* These types don't support ports to IPD/PKO */ case CVMX_HELPER_INTERFACE_MODE_DISABLED: @@ -772,22 +777,22 @@ static int __cvmx_helper_packet_hardware_enable(int interface) } /** - * Function to adjust internal IPD pointer alignments - * - * Returns 0 on success - * !0 on failure - */ + * Function to adjust internal IPD pointer alignments + * + * Returns 0 on success + * !0 on failure + */ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) { #define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \ - (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP) + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_FIRST_MBUFF_SKIP) #define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \ - (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) #define FIX_IPD_OUTPORT 0 /* Ports 0-15 are interface 0, 16-31 are interface 1 */ #define INTERFACE(port) (port >> 4) #define INDEX(port) (port & 0xf) - uint64_t *p64; + u64 *p64; union cvmx_pko_command_word0 pko_command; union cvmx_buf_ptr g_buffer, pkt_buffer; struct cvmx_wqe *work; @@ -798,17 +803,17 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) int i; /* Save values for restore at end */ - uint64_t prtx_cfg = + u64 prtx_cfg = cvmx_read_csr(CVMX_GMXX_PRTX_CFG (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); - uint64_t tx_ptr_en = + u64 tx_ptr_en = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); - uint64_t rx_ptr_en = + u64 rx_ptr_en = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); - uint64_t rxx_jabber = + u64 rxx_jabber = cvmx_read_csr(CVMX_GMXX_RXX_JABBER (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); - uint64_t frame_max = + u64 frame_max = cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); @@ -849,8 +854,7 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) g_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL)); if (g_buffer.s.addr == 0) { - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "buffer allocation failure.\n"); + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n"); goto fix_ipd_exit; } @@ -861,18 +865,17 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) pkt_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL)); if (pkt_buffer.s.addr == 0) { - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "buffer allocation failure.\n"); + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n"); goto fix_ipd_exit; } pkt_buffer.s.i = 1; pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL; pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES; - p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr); + p64 = (u64 *)cvmx_phys_to_ptr(pkt_buffer.s.addr); p64[0] = 0xffffffffffff0000ull; p64[1] = 0x08004510ull; - p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull; + p64[2] = ((u64)(size - 14) << 48) | 0x5ae740004000ull; p64[3] = 0x3a5fc0a81073c0a8ull; for (i = 0; i < num_segs; i++) { @@ -883,7 +886,7 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) if (i == (num_segs - 1)) pkt_buffer.s.i = 0; - *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr + + *(u64 *)cvmx_phys_to_ptr(g_buffer.s.addr + 8 * i) = pkt_buffer.u64; } @@ -928,11 +931,10 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) do { work = cvmx_pow_work_request_sync(CVMX_POW_WAIT); retry_cnt--; - } while ((work == NULL) && (retry_cnt > 0)); + } while ((!work) && (retry_cnt > 0)); if (!retry_cnt) - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "get_work() timeout occurred.\n"); + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred.\n"); /* Free packet */ if (work) @@ -962,15 +964,14 @@ static int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n"); return !!num_segs; - } /** - * Called after all internal packet IO paths are setup. This - * function enables IPD/PIP and begins packet input and output. - * - * Returns Zero on success, negative on failure - */ + * Called after all internal packet IO paths are setup. This + * function enables IPD/PIP and begins packet input and output. + * + * Returns Zero on success, negative on failure + */ int cvmx_helper_ipd_and_packet_input_enable(void) { int num_interfaces; @@ -993,23 +994,23 @@ int cvmx_helper_ipd_and_packet_input_enable(void) /* Finally enable PKO now that the entire path is up and running */ cvmx_pko_enable(); - if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) - || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) - && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) + if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) || + OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) && + (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) __cvmx_helper_errata_fix_ipd_ptr_alignment(); return 0; } EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable); /** - * Initialize the PIP, IPD, and PKO hardware to support - * simple priority based queues for the ethernet ports. Each - * port is configured with a number of priority queues based - * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower - * priority than the previous. - * - * Returns Zero on success, non-zero on failure - */ + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ int cvmx_helper_initialize_packet_io_global(void) { int result = 0; @@ -1062,15 +1063,15 @@ int cvmx_helper_initialize_packet_io_global(void) EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global); /** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port) { union cvmx_helper_link_info result; @@ -1122,16 +1123,16 @@ union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port) EXPORT_SYMBOL_GPL(cvmx_helper_link_get); /** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ int cvmx_helper_link_set(int ipd_port, union cvmx_helper_link_info link_info) { int result = -1; diff --git a/drivers/staging/octeon/cvmx-helper.h b/drivers/staging/octeon/cvmx-helper.h new file mode 100644 index 000000000000..1d5d5df6dbda --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper.h @@ -0,0 +1,170 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions for common, but complicated tasks. + * + */ + +#ifndef __CVMX_HELPER_H__ +#define __CVMX_HELPER_H__ + +#include "cvmx-config.h" +#include "cvmx-fpa.h" +#include "cvmx-wqe.h" + +typedef enum { + CVMX_HELPER_INTERFACE_MODE_DISABLED, + CVMX_HELPER_INTERFACE_MODE_RGMII, + CVMX_HELPER_INTERFACE_MODE_GMII, + CVMX_HELPER_INTERFACE_MODE_SPI, + CVMX_HELPER_INTERFACE_MODE_PCIE, + CVMX_HELPER_INTERFACE_MODE_XAUI, + CVMX_HELPER_INTERFACE_MODE_SGMII, + CVMX_HELPER_INTERFACE_MODE_PICMG, + CVMX_HELPER_INTERFACE_MODE_NPI, + CVMX_HELPER_INTERFACE_MODE_LOOP, +} cvmx_helper_interface_mode_t; + +union cvmx_helper_link_info { + u64 u64; + struct { + u64 reserved_20_63:44; + u64 link_up:1; /**< Is the physical link up? */ + u64 full_duplex:1; /**< 1 if the link is full duplex */ + u64 speed:18; /**< Speed of the link in Mbps */ + } s; +}; + +#include "cvmx-helper-errata.h" +#include "cvmx-helper-loop.h" +#include "cvmx-helper-npi.h" +#include "cvmx-helper-rgmii.h" +#include "cvmx-helper-sgmii.h" +#include "cvmx-helper-spi.h" +#include "cvmx-helper-util.h" +#include "cvmx-helper-xaui.h" + +/** + * This function enables the IPD and also enables the packet interfaces. + * The packet interfaces (RGMII and SPI) must be enabled after the + * IPD. This should be called by the user program after any additional + * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD + * is not set in the executive-config.h file. + * + * Returns 0 on success + * -1 on failure + */ +int cvmx_helper_ipd_and_packet_input_enable(void); + +/** + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ +int cvmx_helper_initialize_packet_io_global(void); + +/** + * Returns the number of ports on the given interface. + * The interface must be initialized before the port count + * can be returned. + * + * @interface: Which interface to return port count for. + * + * Returns Port count for interface + * -1 for uninitialized interface + */ +int cvmx_helper_ports_on_interface(int interface); + +/** + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ +int cvmx_helper_get_number_of_interfaces(void); + +/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ +cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int + interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_link_set(int ipd_port, + union cvmx_helper_link_info link_info); + +/** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_probe(int interface); +int cvmx_helper_interface_enumerate(int interface); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-iob-defs.h b/drivers/staging/octeon/cvmx-iob-defs.h new file mode 100644 index 000000000000..1c22aed692fe --- /dev/null +++ b/drivers/staging/octeon/cvmx-iob-defs.h @@ -0,0 +1,902 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_IOB_DEFS_H__ +#define __CVMX_IOB_DEFS_H__ + +#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull)) +#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull)) +#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull)) +#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull)) +#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull)) +#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull)) +#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull)) +#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull)) +#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull)) +#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull)) +#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull)) +#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull)) +#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull)) +#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull)) +#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull)) +#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull)) +#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull)) +#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull)) +#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull)) +#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull)) +#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull)) +#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull)) +#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull)) +#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull)) +#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull)) +#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull)) +#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull)) +#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull)) +#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull)) +#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull)) +#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull)) +#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull)) +#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull)) +#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull)) + +union cvmx_iob_bist_status { + u64 u64; + struct cvmx_iob_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 ibd:1; + u64 icd:1; +#else + u64 icd:1; + u64 ibd:1; + u64 reserved_2_63:62; +#endif + } s; + struct cvmx_iob_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 icnrcb:1; + u64 icr0:1; + u64 icr1:1; + u64 icnr1:1; + u64 icnr0:1; + u64 ibdr0:1; + u64 ibdr1:1; + u64 ibr0:1; + u64 ibr1:1; + u64 icnrt:1; + u64 ibrq0:1; + u64 ibrq1:1; + u64 icrn0:1; + u64 icrn1:1; + u64 icrp0:1; + u64 icrp1:1; + u64 ibd:1; + u64 icd:1; +#else + u64 icd:1; + u64 ibd:1; + u64 icrp1:1; + u64 icrp0:1; + u64 icrn1:1; + u64 icrn0:1; + u64 ibrq1:1; + u64 ibrq0:1; + u64 icnrt:1; + u64 ibr1:1; + u64 ibr0:1; + u64 ibdr1:1; + u64 ibdr0:1; + u64 icnr0:1; + u64 icnr1:1; + u64 icr1:1; + u64 icr0:1; + u64 icnrcb:1; + u64 reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_iob_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 xmdfif:1; + u64 xmcfif:1; + u64 iorfif:1; + u64 rsdfif:1; + u64 iocfif:1; + u64 icnrcb:1; + u64 icr0:1; + u64 icr1:1; + u64 icnr1:1; + u64 icnr0:1; + u64 ibdr0:1; + u64 ibdr1:1; + u64 ibr0:1; + u64 ibr1:1; + u64 icnrt:1; + u64 ibrq0:1; + u64 ibrq1:1; + u64 icrn0:1; + u64 icrn1:1; + u64 icrp0:1; + u64 icrp1:1; + u64 ibd:1; + u64 icd:1; +#else + u64 icd:1; + u64 ibd:1; + u64 icrp1:1; + u64 icrp0:1; + u64 icrn1:1; + u64 icrn0:1; + u64 ibrq1:1; + u64 ibrq0:1; + u64 icnrt:1; + u64 ibr1:1; + u64 ibr0:1; + u64 ibdr1:1; + u64 ibdr0:1; + u64 icnr0:1; + u64 icnr1:1; + u64 icr1:1; + u64 icr0:1; + u64 icnrcb:1; + u64 iocfif:1; + u64 rsdfif:1; + u64 iorfif:1; + u64 xmcfif:1; + u64 xmdfif:1; + u64 reserved_23_63:41; +#endif + } cn61xx; + struct cvmx_iob_bist_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 xmdfif:1; + u64 xmcfif:1; + u64 iorfif:1; + u64 rsdfif:1; + u64 iocfif:1; + u64 icnrcb:1; + u64 icr0:1; + u64 icr1:1; + u64 icnr0:1; + u64 ibr0:1; + u64 ibr1:1; + u64 icnrt:1; + u64 ibrq0:1; + u64 ibrq1:1; + u64 icrn0:1; + u64 icrn1:1; + u64 ibd:1; + u64 icd:1; +#else + u64 icd:1; + u64 ibd:1; + u64 icrn1:1; + u64 icrn0:1; + u64 ibrq1:1; + u64 ibrq0:1; + u64 icnrt:1; + u64 ibr1:1; + u64 ibr0:1; + u64 icnr0:1; + u64 icr1:1; + u64 icr0:1; + u64 icnrcb:1; + u64 iocfif:1; + u64 rsdfif:1; + u64 iorfif:1; + u64 xmcfif:1; + u64 xmdfif:1; + u64 reserved_18_63:46; +#endif + } cn68xx; +}; + +union cvmx_iob_ctl_status { + u64 u64; + struct cvmx_iob_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 fif_dly:1; + u64 xmc_per:4; + u64 reserved_5_5:1; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 reserved_5_5:1; + u64 xmc_per:4; + u64 fif_dly:1; + u64 reserved_11_63:53; +#endif + } s; + struct cvmx_iob_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 reserved_5_63:59; +#endif + } cn30xx; + struct cvmx_iob_ctl_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 rr_mode:1; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 rr_mode:1; + u64 reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_iob_ctl_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 fif_dly:1; + u64 xmc_per:4; + u64 rr_mode:1; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 rr_mode:1; + u64 xmc_per:4; + u64 fif_dly:1; + u64 reserved_11_63:53; +#endif + } cn61xx; + struct cvmx_iob_ctl_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 xmc_per:4; + u64 rr_mode:1; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 rr_mode:1; + u64 xmc_per:4; + u64 reserved_10_63:54; +#endif + } cn63xx; + struct cvmx_iob_ctl_status_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 fif_dly:1; + u64 xmc_per:4; + u64 rsvr5:1; + u64 outb_mat:1; + u64 inb_mat:1; + u64 pko_enb:1; + u64 dwb_enb:1; + u64 fau_end:1; +#else + u64 fau_end:1; + u64 dwb_enb:1; + u64 pko_enb:1; + u64 inb_mat:1; + u64 outb_mat:1; + u64 rsvr5:1; + u64 xmc_per:4; + u64 fif_dly:1; + u64 reserved_11_63:53; +#endif + } cn68xx; +}; + +union cvmx_iob_dwb_pri_cnt { + u64 u64; + struct cvmx_iob_dwb_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_fau_timeout { + u64 u64; + struct cvmx_iob_fau_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 tout_enb:1; + u64 tout_val:12; +#else + u64 tout_val:12; + u64 tout_enb:1; + u64 reserved_13_63:51; +#endif + } s; +}; + +union cvmx_iob_i2c_pri_cnt { + u64 u64; + struct cvmx_iob_i2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_inb_control_match { + u64 u64; + struct cvmx_iob_inb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 mask:8; + u64 opc:4; + u64 dst:9; + u64 src:8; +#else + u64 src:8; + u64 dst:9; + u64 opc:4; + u64 mask:8; + u64 reserved_29_63:35; +#endif + } s; +}; + +union cvmx_iob_inb_control_match_enb { + u64 u64; + struct cvmx_iob_inb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 mask:8; + u64 opc:4; + u64 dst:9; + u64 src:8; +#else + u64 src:8; + u64 dst:9; + u64 opc:4; + u64 mask:8; + u64 reserved_29_63:35; +#endif + } s; +}; + +union cvmx_iob_inb_data_match { + u64 u64; + struct cvmx_iob_inb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_iob_inb_data_match_enb { + u64 u64; + struct cvmx_iob_inb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_iob_int_enb { + u64 u64; + struct cvmx_iob_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 p_dat:1; + u64 np_dat:1; + u64 p_eop:1; + u64 p_sop:1; + u64 np_eop:1; + u64 np_sop:1; +#else + u64 np_sop:1; + u64 np_eop:1; + u64 p_sop:1; + u64 p_eop:1; + u64 np_dat:1; + u64 p_dat:1; + u64 reserved_6_63:58; +#endif + } s; + struct cvmx_iob_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 p_eop:1; + u64 p_sop:1; + u64 np_eop:1; + u64 np_sop:1; +#else + u64 np_sop:1; + u64 np_eop:1; + u64 p_sop:1; + u64 p_eop:1; + u64 reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_iob_int_enb_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } cn68xx; +}; + +union cvmx_iob_int_sum { + u64 u64; + struct cvmx_iob_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 p_dat:1; + u64 np_dat:1; + u64 p_eop:1; + u64 p_sop:1; + u64 np_eop:1; + u64 np_sop:1; +#else + u64 np_sop:1; + u64 np_eop:1; + u64 p_sop:1; + u64 p_eop:1; + u64 np_dat:1; + u64 p_dat:1; + u64 reserved_6_63:58; +#endif + } s; + struct cvmx_iob_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 p_eop:1; + u64 p_sop:1; + u64 np_eop:1; + u64 np_sop:1; +#else + u64 np_sop:1; + u64 np_eop:1; + u64 p_sop:1; + u64 p_eop:1; + u64 reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_iob_int_sum_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } cn68xx; +}; + +union cvmx_iob_n2c_l2c_pri_cnt { + u64 u64; + struct cvmx_iob_n2c_l2c_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_n2c_rsp_pri_cnt { + u64 u64; + struct cvmx_iob_n2c_rsp_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_outb_com_pri_cnt { + u64 u64; + struct cvmx_iob_outb_com_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_outb_control_match { + u64 u64; + struct cvmx_iob_outb_control_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 mask:8; + u64 eot:1; + u64 dst:8; + u64 src:9; +#else + u64 src:9; + u64 dst:8; + u64 eot:1; + u64 mask:8; + u64 reserved_26_63:38; +#endif + } s; +}; + +union cvmx_iob_outb_control_match_enb { + u64 u64; + struct cvmx_iob_outb_control_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 mask:8; + u64 eot:1; + u64 dst:8; + u64 src:9; +#else + u64 src:9; + u64 dst:8; + u64 eot:1; + u64 mask:8; + u64 reserved_26_63:38; +#endif + } s; +}; + +union cvmx_iob_outb_data_match { + u64 u64; + struct cvmx_iob_outb_data_match_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_iob_outb_data_match_enb { + u64 u64; + struct cvmx_iob_outb_data_match_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_iob_outb_fpa_pri_cnt { + u64 u64; + struct cvmx_iob_outb_fpa_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_outb_req_pri_cnt { + u64 u64; + struct cvmx_iob_outb_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_p2c_req_pri_cnt { + u64 u64; + struct cvmx_iob_p2c_req_pri_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 cnt_enb:1; + u64 cnt_val:15; +#else + u64 cnt_val:15; + u64 cnt_enb:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_iob_pkt_err { + u64 u64; + struct cvmx_iob_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 vport:6; + u64 port:6; +#else + u64 port:6; + u64 vport:6; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_iob_pkt_err_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 port:6; +#else + u64 port:6; + u64 reserved_6_63:58; +#endif + } cn30xx; +}; + +union cvmx_iob_to_cmb_credits { + u64 u64; + struct cvmx_iob_to_cmb_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 ncb_rd:3; + u64 ncb_wr:3; +#else + u64 ncb_wr:3; + u64 ncb_rd:3; + u64 reserved_6_63:58; +#endif + } s; + struct cvmx_iob_to_cmb_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 pko_rd:3; + u64 ncb_rd:3; + u64 ncb_wr:3; +#else + u64 ncb_wr:3; + u64 ncb_rd:3; + u64 pko_rd:3; + u64 reserved_9_63:55; +#endif + } cn52xx; + struct cvmx_iob_to_cmb_credits_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 dwb:3; + u64 ncb_rd:3; + u64 ncb_wr:3; +#else + u64 ncb_wr:3; + u64 ncb_rd:3; + u64 dwb:3; + u64 reserved_9_63:55; +#endif + } cn68xx; +}; + +union cvmx_iob_to_ncb_did_00_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_00_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_111_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_111_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_223_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_223_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_24_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_24_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_32_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_32_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_40_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_40_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_55_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_55_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_64_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_64_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_79_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_79_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_96_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_96_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_iob_to_ncb_did_98_credits { + u64 u64; + struct cvmx_iob_to_ncb_did_98_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 crd:7; +#else + u64 crd:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-ipd-defs.h b/drivers/staging/octeon/cvmx-ipd-defs.h new file mode 100644 index 000000000000..977e4008df7d --- /dev/null +++ b/drivers/staging/octeon/cvmx-ipd-defs.h @@ -0,0 +1,1471 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_IPD_DEFS_H__ +#define __CVMX_IPD_DEFS_H__ + +#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) +#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) +#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) +#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) +#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) +#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) +#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) +#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) +#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) +#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) +#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) +#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) +#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) +#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) +#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) +#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) +#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) +#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) +#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) +#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) +#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) +#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) +#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8 * 36) +#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8 * 40) +#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8 * 36) +#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8 * 40) +#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8 * 44) +#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) +#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) +#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) +#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) +#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) +#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) +#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) +#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) +#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) +#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) +#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) +#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) +#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) +#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) +#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) +#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) +#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) +#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) +#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) +#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) +#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) +#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) +#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) +#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) +#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) +#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) +#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) +#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) +#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) +#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) +#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) +#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) +#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) +#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) +#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) +#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) +#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) + +union cvmx_ipd_1st_mbuff_skip { + u64 u64; + struct cvmx_ipd_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 skip_sz:6; +#else + u64 skip_sz:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_1st_next_ptr_back { + u64 u64; + struct cvmx_ipd_1st_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 back:4; +#else + u64 back:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_ipd_2nd_next_ptr_back { + u64 u64; + struct cvmx_ipd_2nd_next_ptr_back_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 back:4; +#else + u64 back:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_ipd_bist_status { + u64 u64; + struct cvmx_ipd_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 iiwo1:1; + u64 iiwo0:1; + u64 iio1:1; + u64 iio0:1; + u64 pbm4:1; + u64 csr_mem:1; + u64 csr_ncmd:1; + u64 pwq_wqed:1; + u64 pwq_wp1:1; + u64 pwq_pow:1; + u64 ipq_pbe1:1; + u64 ipq_pbe0:1; + u64 pbm3:1; + u64 pbm2:1; + u64 pbm1:1; + u64 pbm0:1; + u64 pbm_word:1; + u64 pwq1:1; + u64 pwq0:1; + u64 prc_off:1; + u64 ipd_old:1; + u64 ipd_new:1; + u64 pwp:1; +#else + u64 pwp:1; + u64 ipd_new:1; + u64 ipd_old:1; + u64 prc_off:1; + u64 pwq0:1; + u64 pwq1:1; + u64 pbm_word:1; + u64 pbm0:1; + u64 pbm1:1; + u64 pbm2:1; + u64 pbm3:1; + u64 ipq_pbe0:1; + u64 ipq_pbe1:1; + u64 pwq_pow:1; + u64 pwq_wp1:1; + u64 pwq_wqed:1; + u64 csr_ncmd:1; + u64 csr_mem:1; + u64 pbm4:1; + u64 iio0:1; + u64 iio1:1; + u64 iiwo0:1; + u64 iiwo1:1; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 pwq_wqed:1; + u64 pwq_wp1:1; + u64 pwq_pow:1; + u64 ipq_pbe1:1; + u64 ipq_pbe0:1; + u64 pbm3:1; + u64 pbm2:1; + u64 pbm1:1; + u64 pbm0:1; + u64 pbm_word:1; + u64 pwq1:1; + u64 pwq0:1; + u64 prc_off:1; + u64 ipd_old:1; + u64 ipd_new:1; + u64 pwp:1; +#else + u64 pwp:1; + u64 ipd_new:1; + u64 ipd_old:1; + u64 prc_off:1; + u64 pwq0:1; + u64 pwq1:1; + u64 pbm_word:1; + u64 pbm0:1; + u64 pbm1:1; + u64 pbm2:1; + u64 pbm3:1; + u64 ipq_pbe0:1; + u64 ipq_pbe1:1; + u64 pwq_pow:1; + u64 pwq_wp1:1; + u64 pwq_wqed:1; + u64 reserved_16_63:48; +#endif + } cn30xx; + struct cvmx_ipd_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 csr_mem:1; + u64 csr_ncmd:1; + u64 pwq_wqed:1; + u64 pwq_wp1:1; + u64 pwq_pow:1; + u64 ipq_pbe1:1; + u64 ipq_pbe0:1; + u64 pbm3:1; + u64 pbm2:1; + u64 pbm1:1; + u64 pbm0:1; + u64 pbm_word:1; + u64 pwq1:1; + u64 pwq0:1; + u64 prc_off:1; + u64 ipd_old:1; + u64 ipd_new:1; + u64 pwp:1; +#else + u64 pwp:1; + u64 ipd_new:1; + u64 ipd_old:1; + u64 prc_off:1; + u64 pwq0:1; + u64 pwq1:1; + u64 pbm_word:1; + u64 pbm0:1; + u64 pbm1:1; + u64 pbm2:1; + u64 pbm3:1; + u64 ipq_pbe0:1; + u64 ipq_pbe1:1; + u64 pwq_pow:1; + u64 pwq_wp1:1; + u64 pwq_wqed:1; + u64 csr_ncmd:1; + u64 csr_mem:1; + u64 reserved_18_63:46; +#endif + } cn52xx; +}; + +union cvmx_ipd_bp_prt_red_end { + u64 u64; + struct cvmx_ipd_bp_prt_red_end_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 prt_enb:48; +#else + u64 prt_enb:48; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_ipd_bp_prt_red_end_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 prt_enb:36; +#else + u64 prt_enb:36; + u64 reserved_36_63:28; +#endif + } cn30xx; + struct cvmx_ipd_bp_prt_red_end_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 prt_enb:40; +#else + u64 prt_enb:40; + u64 reserved_40_63:24; +#endif + } cn52xx; + struct cvmx_ipd_bp_prt_red_end_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 prt_enb:44; +#else + u64 prt_enb:44; + u64 reserved_44_63:20; +#endif + } cn63xx; +}; + +union cvmx_ipd_bpidx_mbuf_th { + u64 u64; + struct cvmx_ipd_bpidx_mbuf_th_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 bp_enb:1; + u64 page_cnt:17; +#else + u64 page_cnt:17; + u64 bp_enb:1; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_bpid_bp_counterx { + u64 u64; + struct cvmx_ipd_bpid_bp_counterx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 cnt_val:25; +#else + u64 cnt_val:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_clk_count { + u64 u64; + struct cvmx_ipd_clk_count_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 clk_cnt:64; +#else + u64 clk_cnt:64; +#endif + } s; +}; + +union cvmx_ipd_credits { + u64 u64; + struct cvmx_ipd_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 iob_wrc:8; + u64 iob_wr:8; +#else + u64 iob_wr:8; + u64 iob_wrc:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_ipd_ctl_status { + u64 u64; + struct cvmx_ipd_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 use_sop:1; + u64 rst_done:1; + u64 clken:1; + u64 no_wptr:1; + u64 pq_apkt:1; + u64 pq_nabuf:1; + u64 ipd_full:1; + u64 pkt_off:1; + u64 len_m8:1; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 len_m8:1; + u64 pkt_off:1; + u64 ipd_full:1; + u64 pq_nabuf:1; + u64 pq_apkt:1; + u64 no_wptr:1; + u64 clken:1; + u64 rst_done:1; + u64 use_sop:1; + u64 reserved_18_63:46; +#endif + } s; + struct cvmx_ipd_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 len_m8:1; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 len_m8:1; + u64 reserved_10_63:54; +#endif + } cn30xx; + struct cvmx_ipd_ctl_status_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 reserved_9_63:55; +#endif + } cn38xxp2; + struct cvmx_ipd_ctl_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 no_wptr:1; + u64 pq_apkt:1; + u64 pq_nabuf:1; + u64 ipd_full:1; + u64 pkt_off:1; + u64 len_m8:1; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 len_m8:1; + u64 pkt_off:1; + u64 ipd_full:1; + u64 pq_nabuf:1; + u64 pq_apkt:1; + u64 no_wptr:1; + u64 reserved_15_63:49; +#endif + } cn50xx; + struct cvmx_ipd_ctl_status_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 ipd_full:1; + u64 pkt_off:1; + u64 len_m8:1; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 len_m8:1; + u64 pkt_off:1; + u64 ipd_full:1; + u64 reserved_12_63:52; +#endif + } cn58xx; + struct cvmx_ipd_ctl_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 clken:1; + u64 no_wptr:1; + u64 pq_apkt:1; + u64 pq_nabuf:1; + u64 ipd_full:1; + u64 pkt_off:1; + u64 len_m8:1; + u64 reset:1; + u64 addpkt:1; + u64 naddbuf:1; + u64 pkt_lend:1; + u64 wqe_lend:1; + u64 pbp_en:1; + u64 opc_mode:2; + u64 ipd_en:1; +#else + u64 ipd_en:1; + u64 opc_mode:2; + u64 pbp_en:1; + u64 wqe_lend:1; + u64 pkt_lend:1; + u64 naddbuf:1; + u64 addpkt:1; + u64 reset:1; + u64 len_m8:1; + u64 pkt_off:1; + u64 ipd_full:1; + u64 pq_nabuf:1; + u64 pq_apkt:1; + u64 no_wptr:1; + u64 clken:1; + u64 reserved_16_63:48; +#endif + } cn63xxp1; +}; + +union cvmx_ipd_ecc_ctl { + u64 u64; + struct cvmx_ipd_ecc_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 pm3_syn:2; + u64 pm2_syn:2; + u64 pm1_syn:2; + u64 pm0_syn:2; +#else + u64 pm0_syn:2; + u64 pm1_syn:2; + u64 pm2_syn:2; + u64 pm3_syn:2; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_ipd_free_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_free_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 max_cnts:7; + u64 wraddr:8; + u64 praddr:8; + u64 cena:1; + u64 raddr:8; +#else + u64 raddr:8; + u64 cena:1; + u64 praddr:8; + u64 wraddr:8; + u64 max_cnts:7; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_ipd_free_ptr_value { + u64 u64; + struct cvmx_ipd_free_ptr_value_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 ptr:33; +#else + u64 ptr:33; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_hold_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_43_63:21; + u64 ptr:33; + u64 max_pkt:3; + u64 praddr:3; + u64 cena:1; + u64 raddr:3; +#else + u64 raddr:3; + u64 cena:1; + u64 praddr:3; + u64 max_pkt:3; + u64 ptr:33; + u64 reserved_43_63:21; +#endif + } s; +}; + +union cvmx_ipd_int_enb { + u64 u64; + struct cvmx_ipd_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 pw3_dbe:1; + u64 pw3_sbe:1; + u64 pw2_dbe:1; + u64 pw2_sbe:1; + u64 pw1_dbe:1; + u64 pw1_sbe:1; + u64 pw0_dbe:1; + u64 pw0_sbe:1; + u64 dat:1; + u64 eop:1; + u64 sop:1; + u64 pq_sub:1; + u64 pq_add:1; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 pq_add:1; + u64 pq_sub:1; + u64 sop:1; + u64 eop:1; + u64 dat:1; + u64 pw0_sbe:1; + u64 pw0_dbe:1; + u64 pw1_sbe:1; + u64 pw1_dbe:1; + u64 pw2_sbe:1; + u64 pw2_dbe:1; + u64 pw3_sbe:1; + u64 pw3_dbe:1; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 reserved_5_63:59; +#endif + } cn30xx; + struct cvmx_ipd_int_enb_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 reserved_10_63:54; +#endif + } cn38xx; + struct cvmx_ipd_int_enb_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 pq_sub:1; + u64 pq_add:1; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 pq_add:1; + u64 pq_sub:1; + u64 reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_ipd_int_sum { + u64 u64; + struct cvmx_ipd_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 pw3_dbe:1; + u64 pw3_sbe:1; + u64 pw2_dbe:1; + u64 pw2_sbe:1; + u64 pw1_dbe:1; + u64 pw1_sbe:1; + u64 pw0_dbe:1; + u64 pw0_sbe:1; + u64 dat:1; + u64 eop:1; + u64 sop:1; + u64 pq_sub:1; + u64 pq_add:1; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 pq_add:1; + u64 pq_sub:1; + u64 sop:1; + u64 eop:1; + u64 dat:1; + u64 pw0_sbe:1; + u64 pw0_dbe:1; + u64 pw1_sbe:1; + u64 pw1_dbe:1; + u64 pw2_sbe:1; + u64 pw2_dbe:1; + u64 pw3_sbe:1; + u64 pw3_dbe:1; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_ipd_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 reserved_5_63:59; +#endif + } cn30xx; + struct cvmx_ipd_int_sum_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 reserved_10_63:54; +#endif + } cn38xx; + struct cvmx_ipd_int_sum_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 pq_sub:1; + u64 pq_add:1; + u64 bc_ovr:1; + u64 d_coll:1; + u64 c_coll:1; + u64 cc_ovr:1; + u64 dc_ovr:1; + u64 bp_sub:1; + u64 prc_par3:1; + u64 prc_par2:1; + u64 prc_par1:1; + u64 prc_par0:1; +#else + u64 prc_par0:1; + u64 prc_par1:1; + u64 prc_par2:1; + u64 prc_par3:1; + u64 bp_sub:1; + u64 dc_ovr:1; + u64 cc_ovr:1; + u64 c_coll:1; + u64 d_coll:1; + u64 bc_ovr:1; + u64 pq_add:1; + u64 pq_sub:1; + u64 reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_ipd_next_pkt_ptr { + u64 u64; + struct cvmx_ipd_next_pkt_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 ptr:33; +#else + u64 ptr:33; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_next_wqe_ptr { + u64 u64; + struct cvmx_ipd_next_wqe_ptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 ptr:33; +#else + u64 ptr:33; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_ipd_not_1st_mbuff_skip { + u64 u64; + struct cvmx_ipd_not_1st_mbuff_skip_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 skip_sz:6; +#else + u64 skip_sz:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_on_bp_drop_pktx { + u64 u64; + struct cvmx_ipd_on_bp_drop_pktx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 prt_enb:64; +#else + u64 prt_enb:64; +#endif + } s; +}; + +union cvmx_ipd_packet_mbuff_size { + u64 u64; + struct cvmx_ipd_packet_mbuff_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 mb_size:12; +#else + u64 mb_size:12; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_ipd_pkt_err { + u64 u64; + struct cvmx_ipd_pkt_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 reasm:6; +#else + u64 reasm:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_ipd_pkt_ptr_valid { + u64 u64; + struct cvmx_ipd_pkt_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 ptr:29; +#else + u64 ptr:29; + u64 reserved_29_63:35; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt { + u64 u64; + struct cvmx_ipd_portx_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 bp_enb:1; + u64 page_cnt:17; +#else + u64 page_cnt:17; + u64 bp_enb:1; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt2 { + u64 u64; + struct cvmx_ipd_portx_bp_page_cnt2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 bp_enb:1; + u64 page_cnt:17; +#else + u64 page_cnt:17; + u64 bp_enb:1; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_portx_bp_page_cnt3 { + u64 u64; + struct cvmx_ipd_portx_bp_page_cnt3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 bp_enb:1; + u64 page_cnt:17; +#else + u64 page_cnt:17; + u64 bp_enb:1; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters2_pairx { + u64 u64; + struct cvmx_ipd_port_bp_counters2_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 cnt_val:25; +#else + u64 cnt_val:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters3_pairx { + u64 u64; + struct cvmx_ipd_port_bp_counters3_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 cnt_val:25; +#else + u64 cnt_val:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters4_pairx { + u64 u64; + struct cvmx_ipd_port_bp_counters4_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 cnt_val:25; +#else + u64 cnt_val:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_bp_counters_pairx { + u64 u64; + struct cvmx_ipd_port_bp_counters_pairx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 cnt_val:25; +#else + u64 cnt_val:25; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_ipd_port_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 ptr:33; + u64 max_pkt:7; + u64 cena:1; + u64 raddr:7; +#else + u64 raddr:7; + u64 cena:1; + u64 max_pkt:7; + u64 ptr:33; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_ipd_port_qos_x_cnt { + u64 u64; + struct cvmx_ipd_port_qos_x_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wmark:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 wmark:32; +#endif + } s; +}; + +union cvmx_ipd_port_qos_intx { + u64 u64; + struct cvmx_ipd_port_qos_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 intr:64; +#else + u64 intr:64; +#endif + } s; +}; + +union cvmx_ipd_port_qos_int_enbx { + u64 u64; + struct cvmx_ipd_port_qos_int_enbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 enb:64; +#else + u64 enb:64; +#endif + } s; +}; + +union cvmx_ipd_port_sopx { + u64 u64; + struct cvmx_ipd_port_sopx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 sop:64; +#else + u64 sop:64; +#endif + } s; +}; + +union cvmx_ipd_prc_hold_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 max_pkt:3; + u64 praddr:3; + u64 ptr:29; + u64 cena:1; + u64 raddr:3; +#else + u64 raddr:3; + u64 cena:1; + u64 ptr:29; + u64 praddr:3; + u64 max_pkt:3; + u64 reserved_39_63:25; +#endif + } s; +}; + +union cvmx_ipd_prc_port_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 max_pkt:7; + u64 ptr:29; + u64 cena:1; + u64 raddr:7; +#else + u64 raddr:7; + u64 cena:1; + u64 ptr:29; + u64 max_pkt:7; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_ipd_ptr_count { + u64 u64; + struct cvmx_ipd_ptr_count_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 pktv_cnt:1; + u64 wqev_cnt:1; + u64 pfif_cnt:3; + u64 pkt_pcnt:7; + u64 wqe_pcnt:7; +#else + u64 wqe_pcnt:7; + u64 pkt_pcnt:7; + u64 pfif_cnt:3; + u64 wqev_cnt:1; + u64 pktv_cnt:1; + u64 reserved_19_63:45; +#endif + } s; +}; + +union cvmx_ipd_pwp_ptr_fifo_ctl { + u64 u64; + struct cvmx_ipd_pwp_ptr_fifo_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 max_cnts:7; + u64 wraddr:8; + u64 praddr:8; + u64 ptr:29; + u64 cena:1; + u64 raddr:8; +#else + u64 raddr:8; + u64 cena:1; + u64 ptr:29; + u64 praddr:8; + u64 wraddr:8; + u64 max_cnts:7; + u64 reserved_61_63:3; +#endif + } s; +}; + +union cvmx_ipd_qosx_red_marks { + u64 u64; + struct cvmx_ipd_qosx_red_marks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 drop:32; + u64 pass:32; +#else + u64 pass:32; + u64 drop:32; +#endif + } s; +}; + +union cvmx_ipd_que0_free_page_cnt { + u64 u64; + struct cvmx_ipd_que0_free_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 q0_pcnt:32; +#else + u64 q0_pcnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_ipd_red_bpid_enablex { + u64 u64; + struct cvmx_ipd_red_bpid_enablex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 prt_enb:64; +#else + u64 prt_enb:64; +#endif + } s; +}; + +union cvmx_ipd_red_delay { + u64 u64; + struct cvmx_ipd_red_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 prb_dly:14; + u64 avg_dly:14; +#else + u64 avg_dly:14; + u64 prb_dly:14; + u64 reserved_28_63:36; +#endif + } s; +}; + +union cvmx_ipd_red_port_enable { + u64 u64; + struct cvmx_ipd_red_port_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 prb_dly:14; + u64 avg_dly:14; + u64 prt_enb:36; +#else + u64 prt_enb:36; + u64 avg_dly:14; + u64 prb_dly:14; +#endif + } s; +}; + +union cvmx_ipd_red_port_enable2 { + u64 u64; + struct cvmx_ipd_red_port_enable2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 prt_enb:12; +#else + u64 prt_enb:12; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_ipd_red_port_enable2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 prt_enb:4; +#else + u64 prt_enb:4; + u64 reserved_4_63:60; +#endif + } cn52xx; + struct cvmx_ipd_red_port_enable2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 prt_enb:8; +#else + u64 prt_enb:8; + u64 reserved_8_63:56; +#endif + } cn63xx; +}; + +union cvmx_ipd_red_quex_param { + u64 u64; + struct cvmx_ipd_red_quex_param_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 use_pcnt:1; + u64 new_con:8; + u64 avg_con:8; + u64 prb_con:32; +#else + u64 prb_con:32; + u64 avg_con:8; + u64 new_con:8; + u64 use_pcnt:1; + u64 reserved_49_63:15; +#endif + } s; +}; + +union cvmx_ipd_req_wgt { + u64 u64; + struct cvmx_ipd_req_wgt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wgt7:8; + u64 wgt6:8; + u64 wgt5:8; + u64 wgt4:8; + u64 wgt3:8; + u64 wgt2:8; + u64 wgt1:8; + u64 wgt0:8; +#else + u64 wgt0:8; + u64 wgt1:8; + u64 wgt2:8; + u64 wgt3:8; + u64 wgt4:8; + u64 wgt5:8; + u64 wgt6:8; + u64 wgt7:8; +#endif + } s; +}; + +union cvmx_ipd_sub_port_bp_page_cnt { + u64 u64; + struct cvmx_ipd_sub_port_bp_page_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 port:6; + u64 page_cnt:25; +#else + u64 page_cnt:25; + u64 port:6; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_ipd_sub_port_fcs { + u64 u64; + struct cvmx_ipd_sub_port_fcs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 port_bit2:4; + u64 reserved_32_35:4; + u64 port_bit:32; +#else + u64 port_bit:32; + u64 reserved_32_35:4; + u64 port_bit2:4; + u64 reserved_40_63:24; +#endif + } s; + struct cvmx_ipd_sub_port_fcs_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 port_bit:3; +#else + u64 port_bit:3; + u64 reserved_3_63:61; +#endif + } cn30xx; + struct cvmx_ipd_sub_port_fcs_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 port_bit:32; +#else + u64 port_bit:32; + u64 reserved_32_63:32; +#endif + } cn38xx; +}; + +union cvmx_ipd_sub_port_qos_cnt { + u64 u64; + struct cvmx_ipd_sub_port_qos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_41_63:23; + u64 port_qos:9; + u64 cnt:32; +#else + u64 cnt:32; + u64 port_qos:9; + u64 reserved_41_63:23; +#endif + } s; +}; + +union cvmx_ipd_wqe_fpa_queue { + u64 u64; + struct cvmx_ipd_wqe_fpa_queue_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 wqe_pool:3; +#else + u64 wqe_pool:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_ipd_wqe_ptr_valid { + u64 u64; + struct cvmx_ipd_wqe_ptr_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 ptr:29; +#else + u64 ptr:29; + u64 reserved_29_63:35; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-ipd.h b/drivers/staging/octeon/cvmx-ipd.h new file mode 100644 index 000000000000..740671f4da34 --- /dev/null +++ b/drivers/staging/octeon/cvmx-ipd.h @@ -0,0 +1,348 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Interface to the hardware Input Packet Data unit. + */ + +#ifndef __CVMX_IPD_H__ +#define __CVMX_IPD_H__ + +#include "octeon-feature.h" + +#include "cvmx-ipd-defs.h" +#include "cvmx-pip-defs.h" + +enum cvmx_ipd_mode { + CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ + CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */ + CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ + CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ +}; + +#ifndef CVMX_ENABLE_LEN_M8_FIX +#define CVMX_ENABLE_LEN_M8_FIX 0 +#endif + +/* CSR typedefs have been moved to cvmx-csr-*.h */ +typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t; +typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t; + +typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t; +typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; + +/** + * Configure IPD + * + * @mbuff_size: Packets buffer size in 8 byte words + * @first_mbuff_skip: + * Number of 8 byte words to skip in the first buffer + * @not_first_mbuff_skip: + * Number of 8 byte words to skip in each following buffer + * @first_back: Must be same as first_mbuff_skip / 128 + * @second_back: + * Must be same as not_first_mbuff_skip / 128 + * @wqe_fpa_pool: + * FPA pool to get work entries from + * @cache_mode: + * @back_pres_enable_flag: + * Enable or disable port back pressure + */ +static inline void cvmx_ipd_config(u64 mbuff_size, + u64 first_mbuff_skip, + u64 not_first_mbuff_skip, + u64 first_back, + u64 second_back, + u64 wqe_fpa_pool, + enum cvmx_ipd_mode cache_mode, + u64 back_pres_enable_flag) +{ + cvmx_ipd_mbuff_first_skip_t first_skip; + cvmx_ipd_mbuff_not_first_skip_t not_first_skip; + union cvmx_ipd_packet_mbuff_size size; + cvmx_ipd_first_next_ptr_back_t first_back_struct; + cvmx_ipd_second_next_ptr_back_t second_back_struct; + union cvmx_ipd_wqe_fpa_queue wqe_pool; + union cvmx_ipd_ctl_status ipd_ctl_reg; + + first_skip.u64 = 0; + first_skip.s.skip_sz = first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); + + not_first_skip.u64 = 0; + not_first_skip.s.skip_sz = not_first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); + + size.u64 = 0; + size.s.mb_size = mbuff_size; + cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); + + first_back_struct.u64 = 0; + first_back_struct.s.back = first_back; + cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); + + second_back_struct.u64 = 0; + second_back_struct.s.back = second_back; + cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); + + wqe_pool.u64 = 0; + wqe_pool.s.wqe_pool = wqe_fpa_pool; + cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); + + ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_reg.s.opc_mode = cache_mode; + ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); + + /* Note: the example RED code that used to be here has been moved to + cvmx_helper_setup_red */ +} + +/** + * Enable IPD + */ +static inline void cvmx_ipd_enable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_reg.s.ipd_en) { + cvmx_dprintf + ("Warning: Enabling IPD when IPD already enabled.\n"); + } + ipd_reg.s.ipd_en = 1; +#if CVMX_ENABLE_LEN_M8_FIX + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) + ipd_reg.s.len_m8 = TRUE; +#endif + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Disable IPD + */ +static inline void cvmx_ipd_disable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_reg.s.ipd_en = 0; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Supportive function for cvmx_fpa_shutdown_pool. + */ +static inline void cvmx_ipd_free_ptr(void) +{ + /* Only CN38XXp{1,2} cannot read pointer out of the IPD */ + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) && + !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { + int no_wptr = 0; + union cvmx_ipd_ptr_count ipd_ptr_count; + + ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); + + /* Handle Work Queue Entry in cn56xx and cn52xx */ + if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) { + union cvmx_ipd_ctl_status ipd_ctl_status; + + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_ctl_status.s.no_wptr) + no_wptr = 1; + } + + /* Free the prefetched WQE */ + if (ipd_ptr_count.s.wqev_cnt) { + union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid; + + ipd_wqe_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64)ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64)ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_WQE_POOL, 0); + } + + /* Free all WQE in the fifo */ + if (ipd_ptr_count.s.wqe_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + ipd_pwp_ptr_fifo_ctl.s.max_cnts + + (ipd_pwp_ptr_fifo_ctl.s.wraddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_WQE_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Free the prefetched packet */ + if (ipd_ptr_count.s.pktv_cnt) { + union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid; + + ipd_pkt_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); + cvmx_fpa_free(cvmx_phys_to_ptr + (ipd_pkt_ptr_valid.s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + + /* Free the per port prefetched packets */ + if (1) { + int i; + union cvmx_ipd_prc_port_ptr_fifo_ctl + ipd_prc_port_ptr_fifo_ctl; + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + + for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + i++) { + ipd_prc_port_ptr_fifo_ctl.s.cena = 0; + ipd_prc_port_ptr_fifo_ctl.s.raddr = + i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64) + ipd_prc_port_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_port_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + } + + /* Free all packets in the holding fifo */ + if (ipd_ptr_count.s.pfif_cnt) { + int i; + union cvmx_ipd_prc_hold_ptr_fifo_ctl + ipd_prc_hold_ptr_fifo_ctl; + + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) { + ipd_prc_hold_ptr_fifo_ctl.s.cena = 0; + ipd_prc_hold_ptr_fifo_ctl.s.raddr = + (ipd_prc_hold_ptr_fifo_ctl.s.praddr + + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64) + ipd_prc_hold_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_hold_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + } + + /* Free all packets in the fifo */ + if (ipd_ptr_count.s.pkt_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + (ipd_pwp_ptr_fifo_ctl.s.praddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((u64)ipd_pwp_ptr_fifo_ctl. + s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Reset the IPD to get all buffers out of it */ + { + union cvmx_ipd_ctl_status ipd_ctl_status; + + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_status.s.reset = 1; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); + } + + /* Reset the PIP */ + { + union cvmx_pip_sft_rst pip_sft_rst; + + pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); + pip_sft_rst.s.rst = 1; + cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); + } + } +} + +#endif /* __CVMX_IPD_H__ */ diff --git a/drivers/staging/octeon/cvmx-l2c-defs.h b/drivers/staging/octeon/cvmx-l2c-defs.h new file mode 100644 index 000000000000..9dfe96e43983 --- /dev/null +++ b/drivers/staging/octeon/cvmx-l2c-defs.h @@ -0,0 +1,237 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_L2C_DEFS_H__ +#define __CVMX_L2C_DEFS_H__ + +#include + +#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull)) +#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull)) +#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull)) +#define CVMX_L2C_ERR_TDTX(block_id) \ + (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_ERR_TTGX(block_id) \ + (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull)) +#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull)) +#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull)) +#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + \ + ((offset) & 3) * 8) +#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0) +#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1) +#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2) +#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3) +#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull)) +#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull)) +#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull)) +#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull)) +#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull)) +#define CVMX_L2C_TADX_PFCX(offset, block_id) \ + (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + (((offset) & 3) + \ + ((block_id) & 7) * 0x8000ull) * 8) +#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \ + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \ + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + \ + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + \ + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_TADX_PRF(offset) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + \ + ((offset) & 7) * 0x40000ull) +#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + \ + ((block_id) & 3) * 0x40000ull) +#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + \ + ((offset) & 1) * 8) +#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \ + ((offset) & 31) * 8) + +union cvmx_l2c_err_tdtx { + u64 u64; + struct cvmx_l2c_err_tdtx_s { + __BITFIELD_FIELD(u64 dbe:1, + __BITFIELD_FIELD(u64 sbe:1, + __BITFIELD_FIELD(u64 vdbe:1, + __BITFIELD_FIELD(u64 vsbe:1, + __BITFIELD_FIELD(u64 syn:10, + __BITFIELD_FIELD(u64 reserved_22_49:28, + __BITFIELD_FIELD(u64 wayidx:18, + __BITFIELD_FIELD(u64 reserved_2_3:2, + __BITFIELD_FIELD(u64 type:2, + ;))))))))) + } s; +}; + +union cvmx_l2c_err_ttgx { + u64 u64; + struct cvmx_l2c_err_ttgx_s { + __BITFIELD_FIELD(u64 dbe:1, + __BITFIELD_FIELD(u64 sbe:1, + __BITFIELD_FIELD(u64 noway:1, + __BITFIELD_FIELD(u64 reserved_56_60:5, + __BITFIELD_FIELD(u64 syn:6, + __BITFIELD_FIELD(u64 reserved_22_49:28, + __BITFIELD_FIELD(u64 wayidx:15, + __BITFIELD_FIELD(u64 reserved_2_6:5, + __BITFIELD_FIELD(u64 type:2, + ;))))))))) + } s; +}; + +union cvmx_l2c_cfg { + u64 u64; + struct cvmx_l2c_cfg_s { + __BITFIELD_FIELD(u64 reserved_20_63:44, + __BITFIELD_FIELD(u64 bstrun:1, + __BITFIELD_FIELD(u64 lbist:1, + __BITFIELD_FIELD(u64 xor_bank:1, + __BITFIELD_FIELD(u64 dpres1:1, + __BITFIELD_FIELD(u64 dpres0:1, + __BITFIELD_FIELD(u64 dfill_dis:1, + __BITFIELD_FIELD(u64 fpexp:4, + __BITFIELD_FIELD(u64 fpempty:1, + __BITFIELD_FIELD(u64 fpen:1, + __BITFIELD_FIELD(u64 idxalias:1, + __BITFIELD_FIELD(u64 mwf_crd:4, + __BITFIELD_FIELD(u64 rsp_arb_mode:1, + __BITFIELD_FIELD(u64 rfb_arb_mode:1, + __BITFIELD_FIELD(u64 lrf_arb_mode:1, + ;))))))))))))))) + } s; +}; + +union cvmx_l2c_ctl { + u64 u64; + struct cvmx_l2c_ctl_s { + __BITFIELD_FIELD(u64 reserved_30_63:34, + __BITFIELD_FIELD(u64 sepcmt:1, + __BITFIELD_FIELD(u64 rdf_fast:1, + __BITFIELD_FIELD(u64 disstgl2i:1, + __BITFIELD_FIELD(u64 l2dfsbe:1, + __BITFIELD_FIELD(u64 l2dfdbe:1, + __BITFIELD_FIELD(u64 discclk:1, + __BITFIELD_FIELD(u64 maxvab:4, + __BITFIELD_FIELD(u64 maxlfb:4, + __BITFIELD_FIELD(u64 rsp_arb_mode:1, + __BITFIELD_FIELD(u64 xmc_arb_mode:1, + __BITFIELD_FIELD(u64 ef_ena:1, + __BITFIELD_FIELD(u64 ef_cnt:7, + __BITFIELD_FIELD(u64 vab_thresh:4, + __BITFIELD_FIELD(u64 disecc:1, + __BITFIELD_FIELD(u64 disidxalias:1, + ;)))))))))))))))) + } s; +}; + +union cvmx_l2c_dbg { + u64 u64; + struct cvmx_l2c_dbg_s { + __BITFIELD_FIELD(u64 reserved_15_63:49, + __BITFIELD_FIELD(u64 lfb_enum:4, + __BITFIELD_FIELD(u64 lfb_dmp:1, + __BITFIELD_FIELD(u64 ppnum:4, + __BITFIELD_FIELD(u64 set:3, + __BITFIELD_FIELD(u64 finv:1, + __BITFIELD_FIELD(u64 l2d:1, + __BITFIELD_FIELD(u64 l2t:1, + ;)))))))) + } s; +}; + +union cvmx_l2c_pfctl { + u64 u64; + struct cvmx_l2c_pfctl_s { + __BITFIELD_FIELD(u64 reserved_36_63:28, + __BITFIELD_FIELD(u64 cnt3rdclr:1, + __BITFIELD_FIELD(u64 cnt2rdclr:1, + __BITFIELD_FIELD(u64 cnt1rdclr:1, + __BITFIELD_FIELD(u64 cnt0rdclr:1, + __BITFIELD_FIELD(u64 cnt3ena:1, + __BITFIELD_FIELD(u64 cnt3clr:1, + __BITFIELD_FIELD(u64 cnt3sel:6, + __BITFIELD_FIELD(u64 cnt2ena:1, + __BITFIELD_FIELD(u64 cnt2clr:1, + __BITFIELD_FIELD(u64 cnt2sel:6, + __BITFIELD_FIELD(u64 cnt1ena:1, + __BITFIELD_FIELD(u64 cnt1clr:1, + __BITFIELD_FIELD(u64 cnt1sel:6, + __BITFIELD_FIELD(u64 cnt0ena:1, + __BITFIELD_FIELD(u64 cnt0clr:1, + __BITFIELD_FIELD(u64 cnt0sel:6, + ;))))))))))))))))) + } s; +}; + +union cvmx_l2c_tadx_prf { + u64 u64; + struct cvmx_l2c_tadx_prf_s { + __BITFIELD_FIELD(u64 reserved_32_63:32, + __BITFIELD_FIELD(u64 cnt3sel:8, + __BITFIELD_FIELD(u64 cnt2sel:8, + __BITFIELD_FIELD(u64 cnt1sel:8, + __BITFIELD_FIELD(u64 cnt0sel:8, + ;))))) + } s; +}; + +union cvmx_l2c_tadx_tag { + u64 u64; + struct cvmx_l2c_tadx_tag_s { + __BITFIELD_FIELD(u64 reserved_46_63:18, + __BITFIELD_FIELD(u64 ecc:6, + __BITFIELD_FIELD(u64 reserved_36_39:4, + __BITFIELD_FIELD(u64 tag:19, + __BITFIELD_FIELD(u64 reserved_4_16:13, + __BITFIELD_FIELD(u64 use:1, + __BITFIELD_FIELD(u64 valid:1, + __BITFIELD_FIELD(u64 dirty:1, + __BITFIELD_FIELD(u64 lock:1, + ;))))))))) + } s; +}; + +union cvmx_l2c_lckbase { + u64 u64; + struct cvmx_l2c_lckbase_s { + __BITFIELD_FIELD(u64 reserved_31_63:33, + __BITFIELD_FIELD(u64 lck_base:27, + __BITFIELD_FIELD(u64 reserved_1_3:3, + __BITFIELD_FIELD(u64 lck_ena:1, + ;)))) + } s; +}; + +union cvmx_l2c_lckoff { + u64 u64; + struct cvmx_l2c_lckoff_s { + __BITFIELD_FIELD(u64 reserved_10_63:54, + __BITFIELD_FIELD(u64 lck_offset:10, + ;)) + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-l2c.h b/drivers/staging/octeon/cvmx-l2c.h new file mode 100644 index 000000000000..f4f2d34b7cbf --- /dev/null +++ b/drivers/staging/octeon/cvmx-l2c.h @@ -0,0 +1,361 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the Level 2 Cache (L2C) control, measurement, and debugging + * facilities. + */ + +#ifndef __CVMX_L2C_H__ +#define __CVMX_L2C_H__ + +#include + +#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro */ +#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro */ +#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro */ + +/* Based on 128 byte cache line size */ +#define CVMX_L2C_IDX_ADDR_SHIFT 7 +#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) + +/* Defines for index aliasing computations */ +#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + \ + cvmx_l2c_get_set_bits()) +#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) +#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 + +/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ +#define CVMX_L2C_TADS 1 + +union cvmx_l2c_tag { + u64 u64; + struct { + __BITFIELD_FIELD(u64 reserved:28, + __BITFIELD_FIELD(u64 V:1, + __BITFIELD_FIELD(u64 D:1, + __BITFIELD_FIELD(u64 L:1, + __BITFIELD_FIELD(u64 U:1, + __BITFIELD_FIELD(u64 addr:32, + ;)))))) + } s; +}; + +/* L2C Performance Counter events. */ +enum cvmx_l2c_event { + CVMX_L2C_EVENT_CYCLES = 0, + CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, + CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, + CVMX_L2C_EVENT_DATA_MISS = 3, + CVMX_L2C_EVENT_DATA_HIT = 4, + CVMX_L2C_EVENT_MISS = 5, + CVMX_L2C_EVENT_HIT = 6, + CVMX_L2C_EVENT_VICTIM_HIT = 7, + CVMX_L2C_EVENT_INDEX_CONFLICT = 8, + CVMX_L2C_EVENT_TAG_PROBE = 9, + CVMX_L2C_EVENT_TAG_UPDATE = 10, + CVMX_L2C_EVENT_TAG_COMPLETE = 11, + CVMX_L2C_EVENT_TAG_DIRTY = 12, + CVMX_L2C_EVENT_DATA_STORE_NOP = 13, + CVMX_L2C_EVENT_DATA_STORE_READ = 14, + CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, + CVMX_L2C_EVENT_FILL_DATA_VALID = 16, + CVMX_L2C_EVENT_WRITE_REQUEST = 17, + CVMX_L2C_EVENT_READ_REQUEST = 18, + CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, + CVMX_L2C_EVENT_XMC_NOP = 20, + CVMX_L2C_EVENT_XMC_LDT = 21, + CVMX_L2C_EVENT_XMC_LDI = 22, + CVMX_L2C_EVENT_XMC_LDD = 23, + CVMX_L2C_EVENT_XMC_STF = 24, + CVMX_L2C_EVENT_XMC_STT = 25, + CVMX_L2C_EVENT_XMC_STP = 26, + CVMX_L2C_EVENT_XMC_STC = 27, + CVMX_L2C_EVENT_XMC_DWB = 28, + CVMX_L2C_EVENT_XMC_PL2 = 29, + CVMX_L2C_EVENT_XMC_PSL1 = 30, + CVMX_L2C_EVENT_XMC_IOBLD = 31, + CVMX_L2C_EVENT_XMC_IOBST = 32, + CVMX_L2C_EVENT_XMC_IOBDMA = 33, + CVMX_L2C_EVENT_XMC_IOBRSP = 34, + CVMX_L2C_EVENT_XMC_BUS_VALID = 35, + CVMX_L2C_EVENT_XMC_MEM_DATA = 36, + CVMX_L2C_EVENT_XMC_REFL_DATA = 37, + CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, + CVMX_L2C_EVENT_RSC_NOP = 39, + CVMX_L2C_EVENT_RSC_STDN = 40, + CVMX_L2C_EVENT_RSC_FILL = 41, + CVMX_L2C_EVENT_RSC_REFL = 42, + CVMX_L2C_EVENT_RSC_STIN = 43, + CVMX_L2C_EVENT_RSC_SCIN = 44, + CVMX_L2C_EVENT_RSC_SCFL = 45, + CVMX_L2C_EVENT_RSC_SCDN = 46, + CVMX_L2C_EVENT_RSC_DATA_VALID = 47, + CVMX_L2C_EVENT_RSC_VALID_FILL = 48, + CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, + CVMX_L2C_EVENT_RSC_VALID_REFL = 50, + CVMX_L2C_EVENT_LRF_REQ = 51, + CVMX_L2C_EVENT_DT_RD_ALLOC = 52, + CVMX_L2C_EVENT_DT_WR_INVAL = 53, + CVMX_L2C_EVENT_MAX +}; + +/* L2C Performance Counter events for Octeon2. */ +enum cvmx_l2c_tad_event { + CVMX_L2C_TAD_EVENT_NONE = 0, + CVMX_L2C_TAD_EVENT_TAG_HIT = 1, + CVMX_L2C_TAD_EVENT_TAG_MISS = 2, + CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, + CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, + CVMX_L2C_TAD_EVENT_SC_FAIL = 5, + CVMX_L2C_TAD_EVENT_SC_PASS = 6, + CVMX_L2C_TAD_EVENT_LFB_VALID = 7, + CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, + CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, + CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, + CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, + CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, + CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, + CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, + CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, + CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, + CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, + CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, + CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, + CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, + CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, + CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, + CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, + CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, + CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, + CVMX_L2C_TAD_EVENT_MAX +}; + +/** + * Configure one of the four L2 Cache performance counters to capture event + * occurrences. + * + * @counter: The counter to configure. Range 0..3. + * @event: The type of L2 Cache event occurrence to count. + * @clear_on_read: When asserted, any read of the performance counter + * clears the counter. + * + * @note The routine does not clear the counter. + */ +void cvmx_l2c_config_perf(u32 counter, enum cvmx_l2c_event event, + u32 clear_on_read); + +/** + * Read the given L2 Cache performance counter. The counter must be configured + * before reading, but this routine does not enforce this requirement. + * + * @counter: The counter to configure. Range 0..3. + * + * Returns The current counter value. + */ +u64 cvmx_l2c_read_perf(u32 counter); + +/** + * Return the L2 Cache way partitioning for a given core. + * + * @core: The core processor of interest. + * + * Returns The mask specifying the partitioning. 0 bits in mask indicates + * the cache 'ways' that a core can evict from. + * -1 on error + */ +int cvmx_l2c_get_core_way_partition(u32 core); + +/** + * Partitions the L2 cache for a core + * + * @core: The core that the partitioning applies to. + * @mask: The partitioning of the ways expressed as a binary + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. + * + + * @note If any ways are blocked for all cores and the HW blocks, then + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. + */ +int cvmx_l2c_set_core_way_partition(u32 core, u32 mask); + +/** + * Return the L2 Cache way partitioning for the hw blocks. + * + * Returns The mask specifying the reserved way. 0 bits in mask indicates + * the cache 'ways' that a core can evict from. + * -1 on error + */ +int cvmx_l2c_get_hw_way_partition(void); + +/** + * Partitions the L2 cache for the hardware blocks. + * + * @mask: The partitioning of the ways expressed as a binary + * mask. A 0 bit allows the core to evict cache lines from + * a way, while a 1 bit blocks the core from evicting any + * lines from that way. There must be at least one allowed + * way (0 bit) in the mask. + * + + * @note If any ways are blocked for all cores and the HW blocks, then + * those ways will never have any cache lines evicted from them. + * All cores and the hardware blocks are free to read from all + * ways regardless of the partitioning. + */ +int cvmx_l2c_set_hw_way_partition(u32 mask); + +/** + * Locks a line in the L2 cache at the specified physical address + * + * @addr: physical address of line to lock + * + * Returns 0 on success, + * 1 if line not locked. + */ +int cvmx_l2c_lock_line(u64 addr); + +/** + * Locks a specified memory region in the L2 cache. + * + * Note that if not all lines can be locked, that means that all + * but one of the ways (associations) available to the locking + * core are locked. Having only 1 association available for + * normal caching may have a significant adverse affect on performance. + * Care should be taken to ensure that enough of the L2 cache is left + * unlocked to allow for normal caching of DRAM. + * + * @start: Physical address of the start of the region to lock + * @len: Length (in bytes) of region to lock + * + * Returns Number of requested lines that where not locked. + * 0 on success (all locked) + */ +int cvmx_l2c_lock_mem_region(u64 start, u64 len); + +/** + * Unlock and flush a cache line from the L2 cache. + * IMPORTANT: Must only be run by one core at a time due to use + * of L2C debug features. + * Note that this function will flush a matching but unlocked cache line. + * (If address is not in L2, no lines are flushed.) + * + * @address: Physical address to unlock + * + * Returns 0: line not unlocked + * 1: line unlocked + */ +int cvmx_l2c_unlock_line(u64 address); + +/** + * Unlocks a region of memory that is locked in the L2 cache + * + * @start: start physical address + * @len: length (in bytes) to unlock + * + * Returns Number of locked lines that the call unlocked + */ +int cvmx_l2c_unlock_mem_region(u64 start, u64 len); + +/** + * Read the L2 controller tag for a given location in L2 + * + * @association: + * Which association to read line from + * @index: Which way to read from. + * + * Returns l2c tag structure for line requested. + */ +union cvmx_l2c_tag cvmx_l2c_get_tag(u32 association, u32 index); + +/* Wrapper providing a deprecated old function name */ +static inline union cvmx_l2c_tag cvmx_get_l2c_tag(u32 association, + u32 index) + __attribute__((deprecated)); +static inline union cvmx_l2c_tag cvmx_get_l2c_tag(u32 association, + u32 index) +{ + return cvmx_l2c_get_tag(association, index); +} + +/** + * Returns the cache index for a given physical address + * + * @addr: physical address + * + * Returns L2 cache index + */ +u32 cvmx_l2c_address_to_index(u64 addr); + +/** + * Flushes (and unlocks) the entire L2 cache. + * IMPORTANT: Must only be run by one core at a time due to use + * of L2C debug features. + */ +void cvmx_l2c_flush(void); + +/** + * + * Returns the size of the L2 cache in bytes, + * -1 on error (unrecognized model) + */ +int cvmx_l2c_get_cache_size_bytes(void); + +/** + * Return the number of sets in the L2 Cache + * + * Returns + */ +int cvmx_l2c_get_num_sets(void); + +/** + * Return log base 2 of the number of sets in the L2 cache + * Returns + */ +int cvmx_l2c_get_set_bits(void); +/** + * Return the number of associations in the L2 Cache + * + * Returns + */ +int cvmx_l2c_get_num_assoc(void); + +/** + * Flush a line from the L2 cache + * This should only be called from one core at a time, as this routine + * sets the core to the 'debug' core in order to flush the line. + * + * @assoc: Association (or way) to flush + * @index: Index to flush + */ +void cvmx_l2c_flush_line(u32 assoc, u32 index); + +#endif /* __CVMX_L2C_H__ */ diff --git a/drivers/staging/octeon/cvmx-l2d-defs.h b/drivers/staging/octeon/cvmx-l2d-defs.h new file mode 100644 index 000000000000..d4fc46dd3566 --- /dev/null +++ b/drivers/staging/octeon/cvmx-l2d-defs.h @@ -0,0 +1,58 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_L2D_DEFS_H__ +#define __CVMX_L2D_DEFS_H__ + +#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull)) +#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull)) + +union cvmx_l2d_err { + u64 u64; + struct cvmx_l2d_err_s { + __BITFIELD_FIELD(u64 reserved_6_63:58, + __BITFIELD_FIELD(u64 bmhclsel:1, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;))))))) + } s; +}; + +union cvmx_l2d_fus3 { + u64 u64; + struct cvmx_l2d_fus3_s { + __BITFIELD_FIELD(u64 reserved_40_63:24, + __BITFIELD_FIELD(u64 ema_ctl:3, + __BITFIELD_FIELD(u64 reserved_34_36:3, + __BITFIELD_FIELD(u64 q3fus:34, + ;)))) + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-l2t-defs.h b/drivers/staging/octeon/cvmx-l2t-defs.h new file mode 100644 index 000000000000..4771e6b73c9e --- /dev/null +++ b/drivers/staging/octeon/cvmx-l2t-defs.h @@ -0,0 +1,141 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_L2T_DEFS_H__ +#define __CVMX_L2T_DEFS_H__ + +#include + +#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) + +union cvmx_l2t_err { + u64 u64; + struct cvmx_l2t_err_s { + __BITFIELD_FIELD(u64 reserved_29_63:35, + __BITFIELD_FIELD(u64 fadru:1, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 fset:3, + __BITFIELD_FIELD(u64 fadr:10, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;)))))))))))))) + } s; + struct cvmx_l2t_err_cn30xx { + __BITFIELD_FIELD(u64 reserved_28_63:36, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 reserved_23_23:1, + __BITFIELD_FIELD(u64 fset:2, + __BITFIELD_FIELD(u64 reserved_19_20:2, + __BITFIELD_FIELD(u64 fadr:8, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;))))))))))))))) + } cn30xx; + struct cvmx_l2t_err_cn31xx { + __BITFIELD_FIELD(u64 reserved_28_63:36, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 reserved_23_23:1, + __BITFIELD_FIELD(u64 fset:2, + __BITFIELD_FIELD(u64 reserved_20_20:1, + __BITFIELD_FIELD(u64 fadr:9, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;))))))))))))))) + } cn31xx; + struct cvmx_l2t_err_cn38xx { + __BITFIELD_FIELD(u64 reserved_28_63:36, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 fset:3, + __BITFIELD_FIELD(u64 fadr:10, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;))))))))))))) + } cn38xx; + struct cvmx_l2t_err_cn50xx { + __BITFIELD_FIELD(u64 reserved_28_63:36, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 fset:3, + __BITFIELD_FIELD(u64 reserved_18_20:3, + __BITFIELD_FIELD(u64 fadr:7, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;)))))))))))))) + } cn50xx; + struct cvmx_l2t_err_cn52xx { + __BITFIELD_FIELD(u64 reserved_28_63:36, + __BITFIELD_FIELD(u64 lck_intena2:1, + __BITFIELD_FIELD(u64 lckerr2:1, + __BITFIELD_FIELD(u64 lck_intena:1, + __BITFIELD_FIELD(u64 lckerr:1, + __BITFIELD_FIELD(u64 fset:3, + __BITFIELD_FIELD(u64 reserved_20_20:1, + __BITFIELD_FIELD(u64 fadr:9, + __BITFIELD_FIELD(u64 fsyn:6, + __BITFIELD_FIELD(u64 ded_err:1, + __BITFIELD_FIELD(u64 sec_err:1, + __BITFIELD_FIELD(u64 ded_intena:1, + __BITFIELD_FIELD(u64 sec_intena:1, + __BITFIELD_FIELD(u64 ecc_ena:1, + ;)))))))))))))) + } cn52xx; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-led-defs.h b/drivers/staging/octeon/cvmx-led-defs.h new file mode 100644 index 000000000000..0532be1f43e3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-led-defs.h @@ -0,0 +1,213 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_LED_DEFS_H__ +#define __CVMX_LED_DEFS_H__ + +#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull)) +#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull)) +#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull)) +#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull)) +#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull)) +#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull)) +#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull)) +#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull)) +#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8) +#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8) +#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8) +#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16) +#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16) + +union cvmx_led_blink { + u64 u64; + struct cvmx_led_blink_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rate:8; +#else + u64 rate:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_led_clk_phase { + u64 u64; + struct cvmx_led_clk_phase_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 phase:7; +#else + u64 phase:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_led_cylon { + u64 u64; + struct cvmx_led_cylon_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 rate:16; +#else + u64 rate:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_led_dbg { + u64 u64; + struct cvmx_led_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 dbg_en:1; +#else + u64 dbg_en:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_led_en { + u64 u64; + struct cvmx_led_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 en:1; +#else + u64 en:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_led_polarity { + u64 u64; + struct cvmx_led_polarity_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 polarity:1; +#else + u64 polarity:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_led_prt { + u64 u64; + struct cvmx_led_prt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 prt_en:8; +#else + u64 prt_en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_led_prt_fmt { + u64 u64; + struct cvmx_led_prt_fmt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 format:4; +#else + u64 format:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_led_prt_statusx { + u64 u64; + struct cvmx_led_prt_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 status:6; +#else + u64 status:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_led_udd_cntx { + u64 u64; + struct cvmx_led_udd_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 cnt:6; +#else + u64 cnt:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_led_udd_datx { + u64 u64; + struct cvmx_led_udd_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 dat:32; +#else + u64 dat:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_led_udd_dat_clrx { + u64 u64; + struct cvmx_led_udd_dat_clrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 clr:32; +#else + u64 clr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_led_udd_dat_setx { + u64 u64; + struct cvmx_led_udd_dat_setx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 set:32; +#else + u64 set:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-lmcx-defs.h b/drivers/staging/octeon/cvmx-lmcx-defs.h new file mode 100644 index 000000000000..9a7691a3167d --- /dev/null +++ b/drivers/staging/octeon/cvmx-lmcx-defs.h @@ -0,0 +1,2942 @@ +/***********************license start*************** + * Author: Cavium Inc. + * + * Contact: support@cavium.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Inc. for more information + ***********************license end**************************************/ + +#ifndef __CVMX_LMCX_DEFS_H__ +#define __CVMX_LMCX_DEFS_H__ + +#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull) +static inline u64 CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; +} + +static inline u64 CVMX_LMCX_ECC_SYND(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; +} + +static inline u64 CVMX_LMCX_FADR(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN30XX & OCTEON_FAMILY_MASK: + case OCTEON_CN50XX & OCTEON_FAMILY_MASK: + case OCTEON_CN38XX & OCTEON_FAMILY_MASK: + case OCTEON_CN31XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; +} + +#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull) +static inline u64 CVMX_LMCX_NXM(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN58XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; +} + +#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull)) +#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8) +#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull)) +#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull)) +#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull)) +#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull) +#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull) + +union cvmx_lmcx_bist_ctl { + u64 u64; + struct cvmx_lmcx_bist_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 start:1; +#else + u64 start:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_lmcx_bist_result { + u64 u64; + struct cvmx_lmcx_bist_result_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 csrd2e:1; + u64 csre2d:1; + u64 mwf:1; + u64 mwd:3; + u64 mwc:1; + u64 mrf:1; + u64 mrd:3; +#else + u64 mrd:3; + u64 mrf:1; + u64 mwc:1; + u64 mwd:3; + u64 mwf:1; + u64 csre2d:1; + u64 csrd2e:1; + u64 reserved_11_63:53; +#endif + } s; + struct cvmx_lmcx_bist_result_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 mwf:1; + u64 mwd:3; + u64 mwc:1; + u64 mrf:1; + u64 mrd:3; +#else + u64 mrd:3; + u64 mrf:1; + u64 mwc:1; + u64 mwd:3; + u64 mwf:1; + u64 reserved_9_63:55; +#endif + } cn50xx; +}; + +union cvmx_lmcx_char_ctl { + u64 u64; + struct cvmx_lmcx_char_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 dr:1; + u64 skew_on:1; + u64 en:1; + u64 sel:1; + u64 prog:8; + u64 prbs:32; +#else + u64 prbs:32; + u64 prog:8; + u64 sel:1; + u64 en:1; + u64 skew_on:1; + u64 dr:1; + u64 reserved_44_63:20; +#endif + } s; + struct cvmx_lmcx_char_ctl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 en:1; + u64 sel:1; + u64 prog:8; + u64 prbs:32; +#else + u64 prbs:32; + u64 prog:8; + u64 sel:1; + u64 en:1; + u64 reserved_42_63:22; +#endif + } cn63xx; +}; + +union cvmx_lmcx_char_mask0 { + u64 u64; + struct cvmx_lmcx_char_mask0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mask:64; +#else + u64 mask:64; +#endif + } s; +}; + +union cvmx_lmcx_char_mask1 { + u64 u64; + struct cvmx_lmcx_char_mask1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 mask:8; +#else + u64 mask:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_lmcx_char_mask2 { + u64 u64; + struct cvmx_lmcx_char_mask2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mask:64; +#else + u64 mask:64; +#endif + } s; +}; + +union cvmx_lmcx_char_mask3 { + u64 u64; + struct cvmx_lmcx_char_mask3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 mask:8; +#else + u64 mask:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_lmcx_char_mask4 { + u64 u64; + struct cvmx_lmcx_char_mask4_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 reset_n_mask:1; + u64 a_mask:16; + u64 ba_mask:3; + u64 we_n_mask:1; + u64 cas_n_mask:1; + u64 ras_n_mask:1; + u64 odt1_mask:2; + u64 odt0_mask:2; + u64 cs1_n_mask:2; + u64 cs0_n_mask:2; + u64 cke_mask:2; +#else + u64 cke_mask:2; + u64 cs0_n_mask:2; + u64 cs1_n_mask:2; + u64 odt0_mask:2; + u64 odt1_mask:2; + u64 ras_n_mask:1; + u64 cas_n_mask:1; + u64 we_n_mask:1; + u64 ba_mask:3; + u64 a_mask:16; + u64 reset_n_mask:1; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_lmcx_comp_ctl { + u64 u64; + struct cvmx_lmcx_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nctl_csr:4; + u64 nctl_clk:4; + u64 nctl_cmd:4; + u64 nctl_dat:4; + u64 pctl_csr:4; + u64 pctl_clk:4; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 pctl_clk:4; + u64 pctl_csr:4; + u64 nctl_dat:4; + u64 nctl_cmd:4; + u64 nctl_clk:4; + u64 nctl_csr:4; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_comp_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nctl_csr:4; + u64 nctl_clk:4; + u64 nctl_cmd:4; + u64 nctl_dat:4; + u64 pctl_csr:4; + u64 pctl_clk:4; + u64 pctl_cmd:4; + u64 pctl_dat:4; +#else + u64 pctl_dat:4; + u64 pctl_cmd:4; + u64 pctl_clk:4; + u64 pctl_csr:4; + u64 nctl_dat:4; + u64 nctl_cmd:4; + u64 nctl_clk:4; + u64 nctl_csr:4; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_comp_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nctl_csr:4; + u64 reserved_20_27:8; + u64 nctl_dat:4; + u64 pctl_csr:4; + u64 reserved_5_11:7; + u64 pctl_dat:5; +#else + u64 pctl_dat:5; + u64 reserved_5_11:7; + u64 pctl_csr:4; + u64 nctl_dat:4; + u64 reserved_20_27:8; + u64 nctl_csr:4; + u64 reserved_32_63:32; +#endif + } cn50xx; + struct cvmx_lmcx_comp_ctl_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nctl_csr:4; + u64 reserved_20_27:8; + u64 nctl_dat:4; + u64 pctl_csr:4; + u64 reserved_4_11:8; + u64 pctl_dat:4; +#else + u64 pctl_dat:4; + u64 reserved_4_11:8; + u64 pctl_csr:4; + u64 nctl_dat:4; + u64 reserved_20_27:8; + u64 nctl_csr:4; + u64 reserved_32_63:32; +#endif + } cn58xxp1; +}; + +union cvmx_lmcx_comp_ctl2 { + u64 u64; + struct cvmx_lmcx_comp_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ddr__ptune:4; + u64 ddr__ntune:4; + u64 m180:1; + u64 byp:1; + u64 ptune:4; + u64 ntune:4; + u64 rodt_ctl:4; + u64 cmd_ctl:4; + u64 ck_ctl:4; + u64 dqx_ctl:4; +#else + u64 dqx_ctl:4; + u64 ck_ctl:4; + u64 cmd_ctl:4; + u64 rodt_ctl:4; + u64 ntune:4; + u64 ptune:4; + u64 byp:1; + u64 m180:1; + u64 ddr__ntune:4; + u64 ddr__ptune:4; + u64 reserved_34_63:30; +#endif + } s; +}; + +union cvmx_lmcx_config { + u64 u64; + struct cvmx_lmcx_config_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 mode32b:1; + u64 scrz:1; + u64 early_unload_d1_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d0_r0:1; + u64 init_status:4; + u64 mirrmask:4; + u64 rankmask:4; + u64 rank_ena:1; + u64 sref_with_dll:1; + u64 early_dqx:1; + u64 sequence:3; + u64 ref_zqcs_int:19; + u64 reset:1; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 pbank_lsb:4; + u64 row_lsb:3; + u64 ecc_ena:1; + u64 init_start:1; +#else + u64 init_start:1; + u64 ecc_ena:1; + u64 row_lsb:3; + u64 pbank_lsb:4; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reset:1; + u64 ref_zqcs_int:19; + u64 sequence:3; + u64 early_dqx:1; + u64 sref_with_dll:1; + u64 rank_ena:1; + u64 rankmask:4; + u64 mirrmask:4; + u64 init_status:4; + u64 early_unload_d0_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d1_r1:1; + u64 scrz:1; + u64 mode32b:1; + u64 reserved_61_63:3; +#endif + } s; + struct cvmx_lmcx_config_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 early_unload_d1_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d0_r0:1; + u64 init_status:4; + u64 mirrmask:4; + u64 rankmask:4; + u64 rank_ena:1; + u64 sref_with_dll:1; + u64 early_dqx:1; + u64 sequence:3; + u64 ref_zqcs_int:19; + u64 reset:1; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 pbank_lsb:4; + u64 row_lsb:3; + u64 ecc_ena:1; + u64 init_start:1; +#else + u64 init_start:1; + u64 ecc_ena:1; + u64 row_lsb:3; + u64 pbank_lsb:4; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reset:1; + u64 ref_zqcs_int:19; + u64 sequence:3; + u64 early_dqx:1; + u64 sref_with_dll:1; + u64 rank_ena:1; + u64 rankmask:4; + u64 mirrmask:4; + u64 init_status:4; + u64 early_unload_d0_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d1_r1:1; + u64 reserved_59_63:5; +#endif + } cn63xx; + struct cvmx_lmcx_config_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_55_63:9; + u64 init_status:4; + u64 mirrmask:4; + u64 rankmask:4; + u64 rank_ena:1; + u64 sref_with_dll:1; + u64 early_dqx:1; + u64 sequence:3; + u64 ref_zqcs_int:19; + u64 reset:1; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 pbank_lsb:4; + u64 row_lsb:3; + u64 ecc_ena:1; + u64 init_start:1; +#else + u64 init_start:1; + u64 ecc_ena:1; + u64 row_lsb:3; + u64 pbank_lsb:4; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reset:1; + u64 ref_zqcs_int:19; + u64 sequence:3; + u64 early_dqx:1; + u64 sref_with_dll:1; + u64 rank_ena:1; + u64 rankmask:4; + u64 mirrmask:4; + u64 init_status:4; + u64 reserved_55_63:9; +#endif + } cn63xxp1; + struct cvmx_lmcx_config_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 scrz:1; + u64 early_unload_d1_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d0_r0:1; + u64 init_status:4; + u64 mirrmask:4; + u64 rankmask:4; + u64 rank_ena:1; + u64 sref_with_dll:1; + u64 early_dqx:1; + u64 sequence:3; + u64 ref_zqcs_int:19; + u64 reset:1; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 pbank_lsb:4; + u64 row_lsb:3; + u64 ecc_ena:1; + u64 init_start:1; +#else + u64 init_start:1; + u64 ecc_ena:1; + u64 row_lsb:3; + u64 pbank_lsb:4; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reset:1; + u64 ref_zqcs_int:19; + u64 sequence:3; + u64 early_dqx:1; + u64 sref_with_dll:1; + u64 rank_ena:1; + u64 rankmask:4; + u64 mirrmask:4; + u64 init_status:4; + u64 early_unload_d0_r0:1; + u64 early_unload_d0_r1:1; + u64 early_unload_d1_r0:1; + u64 early_unload_d1_r1:1; + u64 scrz:1; + u64 reserved_60_63:4; +#endif + } cn66xx; +}; + +union cvmx_lmcx_control { + u64 u64; + struct cvmx_lmcx_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 scramble_ena:1; + u64 thrcnt:12; + u64 persub:8; + u64 thrmax:4; + u64 crm_cnt:5; + u64 crm_thr:5; + u64 crm_max:5; + u64 rodt_bprch:1; + u64 wodt_bprch:1; + u64 bprch:2; + u64 ext_zqcs_dis:1; + u64 int_zqcs_dis:1; + u64 auto_dclkdis:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 nxm_write_en:1; + u64 elev_prio_dis:1; + u64 inorder_wr:1; + u64 inorder_rd:1; + u64 throttle_wr:1; + u64 throttle_rd:1; + u64 fprch2:2; + u64 pocas:1; + u64 ddr2t:1; + u64 bwcnt:1; + u64 rdimm_ena:1; +#else + u64 rdimm_ena:1; + u64 bwcnt:1; + u64 ddr2t:1; + u64 pocas:1; + u64 fprch2:2; + u64 throttle_rd:1; + u64 throttle_wr:1; + u64 inorder_rd:1; + u64 inorder_wr:1; + u64 elev_prio_dis:1; + u64 nxm_write_en:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 auto_dclkdis:1; + u64 int_zqcs_dis:1; + u64 ext_zqcs_dis:1; + u64 bprch:2; + u64 wodt_bprch:1; + u64 rodt_bprch:1; + u64 crm_max:5; + u64 crm_thr:5; + u64 crm_cnt:5; + u64 thrmax:4; + u64 persub:8; + u64 thrcnt:12; + u64 scramble_ena:1; +#endif + } s; + struct cvmx_lmcx_control_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 rodt_bprch:1; + u64 wodt_bprch:1; + u64 bprch:2; + u64 ext_zqcs_dis:1; + u64 int_zqcs_dis:1; + u64 auto_dclkdis:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 nxm_write_en:1; + u64 elev_prio_dis:1; + u64 inorder_wr:1; + u64 inorder_rd:1; + u64 throttle_wr:1; + u64 throttle_rd:1; + u64 fprch2:2; + u64 pocas:1; + u64 ddr2t:1; + u64 bwcnt:1; + u64 rdimm_ena:1; +#else + u64 rdimm_ena:1; + u64 bwcnt:1; + u64 ddr2t:1; + u64 pocas:1; + u64 fprch2:2; + u64 throttle_rd:1; + u64 throttle_wr:1; + u64 inorder_rd:1; + u64 inorder_wr:1; + u64 elev_prio_dis:1; + u64 nxm_write_en:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 auto_dclkdis:1; + u64 int_zqcs_dis:1; + u64 ext_zqcs_dis:1; + u64 bprch:2; + u64 wodt_bprch:1; + u64 rodt_bprch:1; + u64 reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_lmcx_control_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 scramble_ena:1; + u64 reserved_24_62:39; + u64 rodt_bprch:1; + u64 wodt_bprch:1; + u64 bprch:2; + u64 ext_zqcs_dis:1; + u64 int_zqcs_dis:1; + u64 auto_dclkdis:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 nxm_write_en:1; + u64 elev_prio_dis:1; + u64 inorder_wr:1; + u64 inorder_rd:1; + u64 throttle_wr:1; + u64 throttle_rd:1; + u64 fprch2:2; + u64 pocas:1; + u64 ddr2t:1; + u64 bwcnt:1; + u64 rdimm_ena:1; +#else + u64 rdimm_ena:1; + u64 bwcnt:1; + u64 ddr2t:1; + u64 pocas:1; + u64 fprch2:2; + u64 throttle_rd:1; + u64 throttle_wr:1; + u64 inorder_rd:1; + u64 inorder_wr:1; + u64 elev_prio_dis:1; + u64 nxm_write_en:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 auto_dclkdis:1; + u64 int_zqcs_dis:1; + u64 ext_zqcs_dis:1; + u64 bprch:2; + u64 wodt_bprch:1; + u64 rodt_bprch:1; + u64 reserved_24_62:39; + u64 scramble_ena:1; +#endif + } cn66xx; + struct cvmx_lmcx_control_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 thrcnt:12; + u64 persub:8; + u64 thrmax:4; + u64 crm_cnt:5; + u64 crm_thr:5; + u64 crm_max:5; + u64 rodt_bprch:1; + u64 wodt_bprch:1; + u64 bprch:2; + u64 ext_zqcs_dis:1; + u64 int_zqcs_dis:1; + u64 auto_dclkdis:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 nxm_write_en:1; + u64 elev_prio_dis:1; + u64 inorder_wr:1; + u64 inorder_rd:1; + u64 throttle_wr:1; + u64 throttle_rd:1; + u64 fprch2:2; + u64 pocas:1; + u64 ddr2t:1; + u64 bwcnt:1; + u64 rdimm_ena:1; +#else + u64 rdimm_ena:1; + u64 bwcnt:1; + u64 ddr2t:1; + u64 pocas:1; + u64 fprch2:2; + u64 throttle_rd:1; + u64 throttle_wr:1; + u64 inorder_rd:1; + u64 inorder_wr:1; + u64 elev_prio_dis:1; + u64 nxm_write_en:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 auto_dclkdis:1; + u64 int_zqcs_dis:1; + u64 ext_zqcs_dis:1; + u64 bprch:2; + u64 wodt_bprch:1; + u64 rodt_bprch:1; + u64 crm_max:5; + u64 crm_thr:5; + u64 crm_cnt:5; + u64 thrmax:4; + u64 persub:8; + u64 thrcnt:12; + u64 reserved_63_63:1; +#endif + } cn68xx; +}; + +union cvmx_lmcx_ctl { + u64 u64; + struct cvmx_lmcx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 pll_div2:1; + u64 pll_bypass:1; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 reserved_10_11:2; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 reserved_10_11:2; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 pll_bypass:1; + u64 pll_div2:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 pll_div2:1; + u64 pll_bypass:1; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 dreset:1; + u64 mode32b:1; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 mode32b:1; + u64 dreset:1; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 pll_bypass:1; + u64 pll_div2:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_ctl_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 reserved_16_17:2; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 set_zero:1; + u64 mode128b:1; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 mode128b:1; + u64 set_zero:1; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 reserved_16_17:2; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_lmcx_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 reserved_17_17:1; + u64 pll_bypass:1; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 dreset:1; + u64 mode32b:1; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 mode32b:1; + u64 dreset:1; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 pll_bypass:1; + u64 reserved_17_17:1; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } cn50xx; + struct cvmx_lmcx_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 reserved_16_17:2; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 dreset:1; + u64 mode32b:1; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 mode32b:1; + u64 dreset:1; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 reserved_16_17:2; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } cn52xx; + struct cvmx_lmcx_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:4; + u64 ddr__pctl:4; + u64 slow_scf:1; + u64 xor_bank:1; + u64 max_write_batch:4; + u64 reserved_16_17:2; + u64 rdimm_ena:1; + u64 r2r_slot:1; + u64 inorder_mwf:1; + u64 inorder_mrf:1; + u64 dreset:1; + u64 mode128b:1; + u64 fprch2:1; + u64 bprch:1; + u64 sil_lat:2; + u64 tskw:2; + u64 qs_dic:2; + u64 dic:2; +#else + u64 dic:2; + u64 qs_dic:2; + u64 tskw:2; + u64 sil_lat:2; + u64 bprch:1; + u64 fprch2:1; + u64 mode128b:1; + u64 dreset:1; + u64 inorder_mrf:1; + u64 inorder_mwf:1; + u64 r2r_slot:1; + u64 rdimm_ena:1; + u64 reserved_16_17:2; + u64 max_write_batch:4; + u64 xor_bank:1; + u64 slow_scf:1; + u64 ddr__pctl:4; + u64 ddr__nctl:4; + u64 reserved_32_63:32; +#endif + } cn58xx; +}; + +union cvmx_lmcx_ctl1 { + u64 u64; + struct cvmx_lmcx_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 sequence:3; + u64 sil_mode:1; + u64 dcc_enable:1; + u64 reserved_2_7:6; + u64 data_layout:2; +#else + u64 data_layout:2; + u64 reserved_2_7:6; + u64 dcc_enable:1; + u64 sil_mode:1; + u64 sequence:3; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reserved_21_63:43; +#endif + } s; + struct cvmx_lmcx_ctl1_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 data_layout:2; +#else + u64 data_layout:2; + u64 reserved_2_63:62; +#endif + } cn30xx; + struct cvmx_lmcx_ctl1_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 sil_mode:1; + u64 dcc_enable:1; + u64 reserved_2_7:6; + u64 data_layout:2; +#else + u64 data_layout:2; + u64 reserved_2_7:6; + u64 dcc_enable:1; + u64 sil_mode:1; + u64 reserved_10_63:54; +#endif + } cn50xx; + struct cvmx_lmcx_ctl1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 ecc_adr:1; + u64 forcewrite:4; + u64 idlepower:3; + u64 sequence:3; + u64 sil_mode:1; + u64 dcc_enable:1; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 dcc_enable:1; + u64 sil_mode:1; + u64 sequence:3; + u64 idlepower:3; + u64 forcewrite:4; + u64 ecc_adr:1; + u64 reserved_21_63:43; +#endif + } cn52xx; + struct cvmx_lmcx_ctl1_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 sil_mode:1; + u64 dcc_enable:1; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 dcc_enable:1; + u64 sil_mode:1; + u64 reserved_10_63:54; +#endif + } cn58xx; +}; + +union cvmx_lmcx_dclk_cnt { + u64 u64; + struct cvmx_lmcx_dclk_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dclkcnt:64; +#else + u64 dclkcnt:64; +#endif + } s; +}; + +union cvmx_lmcx_dclk_cnt_hi { + u64 u64; + struct cvmx_lmcx_dclk_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 dclkcnt_hi:32; +#else + u64 dclkcnt_hi:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_dclk_cnt_lo { + u64 u64; + struct cvmx_lmcx_dclk_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 dclkcnt_lo:32; +#else + u64 dclkcnt_lo:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_dclk_ctl { + u64 u64; + struct cvmx_lmcx_dclk_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 off90_ena:1; + u64 dclk90_byp:1; + u64 dclk90_ld:1; + u64 dclk90_vlu:5; +#else + u64 dclk90_vlu:5; + u64 dclk90_ld:1; + u64 dclk90_byp:1; + u64 off90_ena:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_lmcx_ddr2_ctl { + u64 u64; + struct cvmx_lmcx_ddr2_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bank8:1; + u64 burst8:1; + u64 addlat:3; + u64 pocas:1; + u64 bwcnt:1; + u64 twr:3; + u64 silo_hc:1; + u64 ddr_eof:4; + u64 tfaw:5; + u64 crip_mode:1; + u64 ddr2t:1; + u64 odt_ena:1; + u64 qdll_ena:1; + u64 dll90_vlu:5; + u64 dll90_byp:1; + u64 rdqs:1; + u64 ddr2:1; +#else + u64 ddr2:1; + u64 rdqs:1; + u64 dll90_byp:1; + u64 dll90_vlu:5; + u64 qdll_ena:1; + u64 odt_ena:1; + u64 ddr2t:1; + u64 crip_mode:1; + u64 tfaw:5; + u64 ddr_eof:4; + u64 silo_hc:1; + u64 twr:3; + u64 bwcnt:1; + u64 pocas:1; + u64 addlat:3; + u64 burst8:1; + u64 bank8:1; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_ddr2_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bank8:1; + u64 burst8:1; + u64 addlat:3; + u64 pocas:1; + u64 bwcnt:1; + u64 twr:3; + u64 silo_hc:1; + u64 ddr_eof:4; + u64 tfaw:5; + u64 crip_mode:1; + u64 ddr2t:1; + u64 odt_ena:1; + u64 qdll_ena:1; + u64 dll90_vlu:5; + u64 dll90_byp:1; + u64 reserved_1_1:1; + u64 ddr2:1; +#else + u64 ddr2:1; + u64 reserved_1_1:1; + u64 dll90_byp:1; + u64 dll90_vlu:5; + u64 qdll_ena:1; + u64 odt_ena:1; + u64 ddr2t:1; + u64 crip_mode:1; + u64 tfaw:5; + u64 ddr_eof:4; + u64 silo_hc:1; + u64 twr:3; + u64 bwcnt:1; + u64 pocas:1; + u64 addlat:3; + u64 burst8:1; + u64 bank8:1; + u64 reserved_32_63:32; +#endif + } cn30xx; +}; + +union cvmx_lmcx_ddr_pll_ctl { + u64 u64; + struct cvmx_lmcx_ddr_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 jtg_test_mode:1; + u64 dfm_div_reset:1; + u64 dfm_ps_en:3; + u64 ddr_div_reset:1; + u64 ddr_ps_en:3; + u64 diffamp:4; + u64 cps:3; + u64 cpb:3; + u64 reset_n:1; + u64 clkf:7; +#else + u64 clkf:7; + u64 reset_n:1; + u64 cpb:3; + u64 cps:3; + u64 diffamp:4; + u64 ddr_ps_en:3; + u64 ddr_div_reset:1; + u64 dfm_ps_en:3; + u64 dfm_div_reset:1; + u64 jtg_test_mode:1; + u64 reserved_27_63:37; +#endif + } s; +}; + +union cvmx_lmcx_delay_cfg { + u64 u64; + struct cvmx_lmcx_delay_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 dq:5; + u64 cmd:5; + u64 clk:5; +#else + u64 clk:5; + u64 cmd:5; + u64 dq:5; + u64 reserved_15_63:49; +#endif + } s; + struct cvmx_lmcx_delay_cfg_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 dq:4; + u64 reserved_9_9:1; + u64 cmd:4; + u64 reserved_4_4:1; + u64 clk:4; +#else + u64 clk:4; + u64 reserved_4_4:1; + u64 cmd:4; + u64 reserved_9_9:1; + u64 dq:4; + u64 reserved_14_63:50; +#endif + } cn38xx; +}; + +union cvmx_lmcx_dimmx_params { + u64 u64; + struct cvmx_lmcx_dimmx_params_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rc15:4; + u64 rc14:4; + u64 rc13:4; + u64 rc12:4; + u64 rc11:4; + u64 rc10:4; + u64 rc9:4; + u64 rc8:4; + u64 rc7:4; + u64 rc6:4; + u64 rc5:4; + u64 rc4:4; + u64 rc3:4; + u64 rc2:4; + u64 rc1:4; + u64 rc0:4; +#else + u64 rc0:4; + u64 rc1:4; + u64 rc2:4; + u64 rc3:4; + u64 rc4:4; + u64 rc5:4; + u64 rc6:4; + u64 rc7:4; + u64 rc8:4; + u64 rc9:4; + u64 rc10:4; + u64 rc11:4; + u64 rc12:4; + u64 rc13:4; + u64 rc14:4; + u64 rc15:4; +#endif + } s; +}; + +union cvmx_lmcx_dimm_ctl { + u64 u64; + struct cvmx_lmcx_dimm_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 parity:1; + u64 tcws:13; + u64 dimm1_wmask:16; + u64 dimm0_wmask:16; +#else + u64 dimm0_wmask:16; + u64 dimm1_wmask:16; + u64 tcws:13; + u64 parity:1; + u64 reserved_46_63:18; +#endif + } s; +}; + +union cvmx_lmcx_dll_ctl { + u64 u64; + struct cvmx_lmcx_dll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dreset:1; + u64 dll90_byp:1; + u64 dll90_ena:1; + u64 dll90_vlu:5; +#else + u64 dll90_vlu:5; + u64 dll90_ena:1; + u64 dll90_byp:1; + u64 dreset:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_lmcx_dll_ctl2 { + u64 u64; + struct cvmx_lmcx_dll_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 intf_en:1; + u64 dll_bringup:1; + u64 dreset:1; + u64 quad_dll_ena:1; + u64 byp_sel:4; + u64 byp_setting:8; +#else + u64 byp_setting:8; + u64 byp_sel:4; + u64 quad_dll_ena:1; + u64 dreset:1; + u64 dll_bringup:1; + u64 intf_en:1; + u64 reserved_16_63:48; +#endif + } s; + struct cvmx_lmcx_dll_ctl2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 dll_bringup:1; + u64 dreset:1; + u64 quad_dll_ena:1; + u64 byp_sel:4; + u64 byp_setting:8; +#else + u64 byp_setting:8; + u64 byp_sel:4; + u64 quad_dll_ena:1; + u64 dreset:1; + u64 dll_bringup:1; + u64 reserved_15_63:49; +#endif + } cn63xx; +}; + +union cvmx_lmcx_dll_ctl3 { + u64 u64; + struct cvmx_lmcx_dll_ctl3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_41_63:23; + u64 dclk90_fwd:1; + u64 ddr_90_dly_byp:1; + u64 dclk90_recal_dis:1; + u64 dclk90_byp_sel:1; + u64 dclk90_byp_setting:8; + u64 dll_fast:1; + u64 dll90_setting:8; + u64 fine_tune_mode:1; + u64 dll_mode:1; + u64 dll90_byte_sel:4; + u64 offset_ena:1; + u64 load_offset:1; + u64 mode_sel:2; + u64 byte_sel:4; + u64 offset:6; +#else + u64 offset:6; + u64 byte_sel:4; + u64 mode_sel:2; + u64 load_offset:1; + u64 offset_ena:1; + u64 dll90_byte_sel:4; + u64 dll_mode:1; + u64 fine_tune_mode:1; + u64 dll90_setting:8; + u64 dll_fast:1; + u64 dclk90_byp_setting:8; + u64 dclk90_byp_sel:1; + u64 dclk90_recal_dis:1; + u64 ddr_90_dly_byp:1; + u64 dclk90_fwd:1; + u64 reserved_41_63:23; +#endif + } s; + struct cvmx_lmcx_dll_ctl3_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 dll_fast:1; + u64 dll90_setting:8; + u64 fine_tune_mode:1; + u64 dll_mode:1; + u64 dll90_byte_sel:4; + u64 offset_ena:1; + u64 load_offset:1; + u64 mode_sel:2; + u64 byte_sel:4; + u64 offset:6; +#else + u64 offset:6; + u64 byte_sel:4; + u64 mode_sel:2; + u64 load_offset:1; + u64 offset_ena:1; + u64 dll90_byte_sel:4; + u64 dll_mode:1; + u64 fine_tune_mode:1; + u64 dll90_setting:8; + u64 dll_fast:1; + u64 reserved_29_63:35; +#endif + } cn63xx; +}; + +union cvmx_lmcx_dual_memcfg { + u64 u64; + struct cvmx_lmcx_dual_memcfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 bank8:1; + u64 row_lsb:3; + u64 reserved_8_15:8; + u64 cs_mask:8; +#else + u64 cs_mask:8; + u64 reserved_8_15:8; + u64 row_lsb:3; + u64 bank8:1; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_lmcx_dual_memcfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 row_lsb:3; + u64 reserved_8_15:8; + u64 cs_mask:8; +#else + u64 cs_mask:8; + u64 reserved_8_15:8; + u64 row_lsb:3; + u64 reserved_19_63:45; +#endif + } cn61xx; +}; + +union cvmx_lmcx_ecc_synd { + u64 u64; + struct cvmx_lmcx_ecc_synd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 mrdsyn3:8; + u64 mrdsyn2:8; + u64 mrdsyn1:8; + u64 mrdsyn0:8; +#else + u64 mrdsyn0:8; + u64 mrdsyn1:8; + u64 mrdsyn2:8; + u64 mrdsyn3:8; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_fadr { + u64 u64; + struct cvmx_lmcx_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_lmcx_fadr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 fdimm:2; + u64 fbunk:1; + u64 fbank:3; + u64 frow:14; + u64 fcol:12; +#else + u64 fcol:12; + u64 frow:14; + u64 fbank:3; + u64 fbunk:1; + u64 fdimm:2; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_fadr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 fdimm:2; + u64 fbunk:1; + u64 fbank:3; + u64 frow:16; + u64 fcol:14; +#else + u64 fcol:14; + u64 frow:16; + u64 fbank:3; + u64 fbunk:1; + u64 fdimm:2; + u64 reserved_36_63:28; +#endif + } cn61xx; +}; + +union cvmx_lmcx_ifb_cnt { + u64 u64; + struct cvmx_lmcx_ifb_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ifbcnt:64; +#else + u64 ifbcnt:64; +#endif + } s; +}; + +union cvmx_lmcx_ifb_cnt_hi { + u64 u64; + struct cvmx_lmcx_ifb_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ifbcnt_hi:32; +#else + u64 ifbcnt_hi:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_ifb_cnt_lo { + u64 u64; + struct cvmx_lmcx_ifb_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ifbcnt_lo:32; +#else + u64 ifbcnt_lo:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_int { + u64 u64; + struct cvmx_lmcx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 ded_err:4; + u64 sec_err:4; + u64 nxm_wr_err:1; +#else + u64 nxm_wr_err:1; + u64 sec_err:4; + u64 ded_err:4; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_lmcx_int_en { + u64 u64; + struct cvmx_lmcx_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 intr_ded_ena:1; + u64 intr_sec_ena:1; + u64 intr_nxm_wr_ena:1; +#else + u64 intr_nxm_wr_ena:1; + u64 intr_sec_ena:1; + u64 intr_ded_ena:1; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_lmcx_mem_cfg0 { + u64 u64; + struct cvmx_lmcx_mem_cfg0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 reset:1; + u64 silo_qc:1; + u64 bunk_ena:1; + u64 ded_err:4; + u64 sec_err:4; + u64 intr_ded_ena:1; + u64 intr_sec_ena:1; + u64 tcl:4; + u64 ref_int:6; + u64 pbank_lsb:4; + u64 row_lsb:3; + u64 ecc_ena:1; + u64 init_start:1; +#else + u64 init_start:1; + u64 ecc_ena:1; + u64 row_lsb:3; + u64 pbank_lsb:4; + u64 ref_int:6; + u64 tcl:4; + u64 intr_sec_ena:1; + u64 intr_ded_ena:1; + u64 sec_err:4; + u64 ded_err:4; + u64 bunk_ena:1; + u64 silo_qc:1; + u64 reset:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_mem_cfg1 { + u64 u64; + struct cvmx_lmcx_mem_cfg1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 comp_bypass:1; + u64 trrd:3; + u64 caslat:3; + u64 tmrd:3; + u64 trfc:5; + u64 trp:4; + u64 twtr:4; + u64 trcd:4; + u64 tras:5; +#else + u64 tras:5; + u64 trcd:4; + u64 twtr:4; + u64 trp:4; + u64 trfc:5; + u64 tmrd:3; + u64 caslat:3; + u64 trrd:3; + u64 comp_bypass:1; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_mem_cfg1_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 trrd:3; + u64 caslat:3; + u64 tmrd:3; + u64 trfc:5; + u64 trp:4; + u64 twtr:4; + u64 trcd:4; + u64 tras:5; +#else + u64 tras:5; + u64 trcd:4; + u64 twtr:4; + u64 trp:4; + u64 trfc:5; + u64 tmrd:3; + u64 caslat:3; + u64 trrd:3; + u64 reserved_31_63:33; +#endif + } cn38xx; +}; + +union cvmx_lmcx_modereg_params0 { + u64 u64; + struct cvmx_lmcx_modereg_params0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 ppd:1; + u64 wrp:3; + u64 dllr:1; + u64 tm:1; + u64 rbt:1; + u64 cl:4; + u64 bl:2; + u64 qoff:1; + u64 tdqs:1; + u64 wlev:1; + u64 al:2; + u64 dll:1; + u64 mpr:1; + u64 mprloc:2; + u64 cwl:3; +#else + u64 cwl:3; + u64 mprloc:2; + u64 mpr:1; + u64 dll:1; + u64 al:2; + u64 wlev:1; + u64 tdqs:1; + u64 qoff:1; + u64 bl:2; + u64 cl:4; + u64 rbt:1; + u64 tm:1; + u64 dllr:1; + u64 wrp:3; + u64 ppd:1; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_lmcx_modereg_params1 { + u64 u64; + struct cvmx_lmcx_modereg_params1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 rtt_nom_11:3; + u64 dic_11:2; + u64 rtt_wr_11:2; + u64 srt_11:1; + u64 asr_11:1; + u64 pasr_11:3; + u64 rtt_nom_10:3; + u64 dic_10:2; + u64 rtt_wr_10:2; + u64 srt_10:1; + u64 asr_10:1; + u64 pasr_10:3; + u64 rtt_nom_01:3; + u64 dic_01:2; + u64 rtt_wr_01:2; + u64 srt_01:1; + u64 asr_01:1; + u64 pasr_01:3; + u64 rtt_nom_00:3; + u64 dic_00:2; + u64 rtt_wr_00:2; + u64 srt_00:1; + u64 asr_00:1; + u64 pasr_00:3; +#else + u64 pasr_00:3; + u64 asr_00:1; + u64 srt_00:1; + u64 rtt_wr_00:2; + u64 dic_00:2; + u64 rtt_nom_00:3; + u64 pasr_01:3; + u64 asr_01:1; + u64 srt_01:1; + u64 rtt_wr_01:2; + u64 dic_01:2; + u64 rtt_nom_01:3; + u64 pasr_10:3; + u64 asr_10:1; + u64 srt_10:1; + u64 rtt_wr_10:2; + u64 dic_10:2; + u64 rtt_nom_10:3; + u64 pasr_11:3; + u64 asr_11:1; + u64 srt_11:1; + u64 rtt_wr_11:2; + u64 dic_11:2; + u64 rtt_nom_11:3; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_lmcx_nxm { + u64 u64; + struct cvmx_lmcx_nxm_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 mem_msb_d3_r1:4; + u64 mem_msb_d3_r0:4; + u64 mem_msb_d2_r1:4; + u64 mem_msb_d2_r0:4; + u64 mem_msb_d1_r1:4; + u64 mem_msb_d1_r0:4; + u64 mem_msb_d0_r1:4; + u64 mem_msb_d0_r0:4; + u64 cs_mask:8; +#else + u64 cs_mask:8; + u64 mem_msb_d0_r0:4; + u64 mem_msb_d0_r1:4; + u64 mem_msb_d1_r0:4; + u64 mem_msb_d1_r1:4; + u64 mem_msb_d2_r0:4; + u64 mem_msb_d2_r1:4; + u64 mem_msb_d3_r0:4; + u64 mem_msb_d3_r1:4; + u64 reserved_40_63:24; +#endif + } s; + struct cvmx_lmcx_nxm_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 cs_mask:8; +#else + u64 cs_mask:8; + u64 reserved_8_63:56; +#endif + } cn52xx; +}; + +union cvmx_lmcx_ops_cnt { + u64 u64; + struct cvmx_lmcx_ops_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 opscnt:64; +#else + u64 opscnt:64; +#endif + } s; +}; + +union cvmx_lmcx_ops_cnt_hi { + u64 u64; + struct cvmx_lmcx_ops_cnt_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 opscnt_hi:32; +#else + u64 opscnt_hi:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_ops_cnt_lo { + u64 u64; + struct cvmx_lmcx_ops_cnt_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 opscnt_lo:32; +#else + u64 opscnt_lo:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_phy_ctl { + u64 u64; + struct cvmx_lmcx_phy_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 rx_always_on:1; + u64 lv_mode:1; + u64 ck_tune1:1; + u64 ck_dlyout1:4; + u64 ck_tune0:1; + u64 ck_dlyout0:4; + u64 loopback:1; + u64 loopback_pos:1; + u64 ts_stagger:1; +#else + u64 ts_stagger:1; + u64 loopback_pos:1; + u64 loopback:1; + u64 ck_dlyout0:4; + u64 ck_tune0:1; + u64 ck_dlyout1:4; + u64 ck_tune1:1; + u64 lv_mode:1; + u64 rx_always_on:1; + u64 reserved_15_63:49; +#endif + } s; + struct cvmx_lmcx_phy_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 lv_mode:1; + u64 ck_tune1:1; + u64 ck_dlyout1:4; + u64 ck_tune0:1; + u64 ck_dlyout0:4; + u64 loopback:1; + u64 loopback_pos:1; + u64 ts_stagger:1; +#else + u64 ts_stagger:1; + u64 loopback_pos:1; + u64 loopback:1; + u64 ck_dlyout0:4; + u64 ck_tune0:1; + u64 ck_dlyout1:4; + u64 ck_tune1:1; + u64 lv_mode:1; + u64 reserved_14_63:50; +#endif + } cn63xxp1; +}; + +union cvmx_lmcx_pll_bwctl { + u64 u64; + struct cvmx_lmcx_pll_bwctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 bwupd:1; + u64 bwctl:4; +#else + u64 bwctl:4; + u64 bwupd:1; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_lmcx_pll_ctl { + u64 u64; + struct cvmx_lmcx_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_30_63:34; + u64 bypass:1; + u64 fasten_n:1; + u64 div_reset:1; + u64 reset_n:1; + u64 clkf:12; + u64 clkr:6; + u64 reserved_6_7:2; + u64 en16:1; + u64 en12:1; + u64 en8:1; + u64 en6:1; + u64 en4:1; + u64 en2:1; +#else + u64 en2:1; + u64 en4:1; + u64 en6:1; + u64 en8:1; + u64 en12:1; + u64 en16:1; + u64 reserved_6_7:2; + u64 clkr:6; + u64 clkf:12; + u64 reset_n:1; + u64 div_reset:1; + u64 fasten_n:1; + u64 bypass:1; + u64 reserved_30_63:34; +#endif + } s; + struct cvmx_lmcx_pll_ctl_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 fasten_n:1; + u64 div_reset:1; + u64 reset_n:1; + u64 clkf:12; + u64 clkr:6; + u64 reserved_6_7:2; + u64 en16:1; + u64 en12:1; + u64 en8:1; + u64 en6:1; + u64 en4:1; + u64 en2:1; +#else + u64 en2:1; + u64 en4:1; + u64 en6:1; + u64 en8:1; + u64 en12:1; + u64 en16:1; + u64 reserved_6_7:2; + u64 clkr:6; + u64 clkf:12; + u64 reset_n:1; + u64 div_reset:1; + u64 fasten_n:1; + u64 reserved_29_63:35; +#endif + } cn50xx; + struct cvmx_lmcx_pll_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 div_reset:1; + u64 reset_n:1; + u64 clkf:12; + u64 clkr:6; + u64 reserved_6_7:2; + u64 en16:1; + u64 en12:1; + u64 en8:1; + u64 en6:1; + u64 en4:1; + u64 en2:1; +#else + u64 en2:1; + u64 en4:1; + u64 en6:1; + u64 en8:1; + u64 en12:1; + u64 en16:1; + u64 reserved_6_7:2; + u64 clkr:6; + u64 clkf:12; + u64 reset_n:1; + u64 div_reset:1; + u64 reserved_28_63:36; +#endif + } cn56xxp1; +}; + +union cvmx_lmcx_pll_status { + u64 u64; + struct cvmx_lmcx_pll_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ddr__nctl:5; + u64 ddr__pctl:5; + u64 reserved_2_21:20; + u64 rfslip:1; + u64 fbslip:1; +#else + u64 fbslip:1; + u64 rfslip:1; + u64 reserved_2_21:20; + u64 ddr__pctl:5; + u64 ddr__nctl:5; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_lmcx_pll_status_cn58xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 rfslip:1; + u64 fbslip:1; +#else + u64 fbslip:1; + u64 rfslip:1; + u64 reserved_2_63:62; +#endif + } cn58xxp1; +}; + +union cvmx_lmcx_read_level_ctl { + u64 u64; + struct cvmx_lmcx_read_level_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 rankmask:4; + u64 pattern:8; + u64 row:16; + u64 col:12; + u64 reserved_3_3:1; + u64 bnk:3; +#else + u64 bnk:3; + u64 reserved_3_3:1; + u64 col:12; + u64 row:16; + u64 pattern:8; + u64 rankmask:4; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_lmcx_read_level_dbg { + u64 u64; + struct cvmx_lmcx_read_level_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bitmask:16; + u64 reserved_4_15:12; + u64 byte:4; +#else + u64 byte:4; + u64 reserved_4_15:12; + u64 bitmask:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_read_level_rankx { + u64 u64; + struct cvmx_lmcx_read_level_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 status:2; + u64 byte8:4; + u64 byte7:4; + u64 byte6:4; + u64 byte5:4; + u64 byte4:4; + u64 byte3:4; + u64 byte2:4; + u64 byte1:4; + u64 byte0:4; +#else + u64 byte0:4; + u64 byte1:4; + u64 byte2:4; + u64 byte3:4; + u64 byte4:4; + u64 byte5:4; + u64 byte6:4; + u64 byte7:4; + u64 byte8:4; + u64 status:2; + u64 reserved_38_63:26; +#endif + } s; +}; + +union cvmx_lmcx_reset_ctl { + u64 u64; + struct cvmx_lmcx_reset_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 ddr3psv:1; + u64 ddr3psoft:1; + u64 ddr3pwarm:1; + u64 ddr3rst:1; +#else + u64 ddr3rst:1; + u64 ddr3pwarm:1; + u64 ddr3psoft:1; + u64 ddr3psv:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_lmcx_rlevel_ctl { + u64 u64; + struct cvmx_lmcx_rlevel_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 delay_unload_3:1; + u64 delay_unload_2:1; + u64 delay_unload_1:1; + u64 delay_unload_0:1; + u64 bitmask:8; + u64 or_dis:1; + u64 offset_en:1; + u64 offset:4; + u64 byte:4; +#else + u64 byte:4; + u64 offset:4; + u64 offset_en:1; + u64 or_dis:1; + u64 bitmask:8; + u64 delay_unload_0:1; + u64 delay_unload_1:1; + u64 delay_unload_2:1; + u64 delay_unload_3:1; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_lmcx_rlevel_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 offset_en:1; + u64 offset:4; + u64 byte:4; +#else + u64 byte:4; + u64 offset:4; + u64 offset_en:1; + u64 reserved_9_63:55; +#endif + } cn63xxp1; +}; + +union cvmx_lmcx_rlevel_dbg { + u64 u64; + struct cvmx_lmcx_rlevel_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bitmask:64; +#else + u64 bitmask:64; +#endif + } s; +}; + +union cvmx_lmcx_rlevel_rankx { + u64 u64; + struct cvmx_lmcx_rlevel_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 status:2; + u64 byte8:6; + u64 byte7:6; + u64 byte6:6; + u64 byte5:6; + u64 byte4:6; + u64 byte3:6; + u64 byte2:6; + u64 byte1:6; + u64 byte0:6; +#else + u64 byte0:6; + u64 byte1:6; + u64 byte2:6; + u64 byte3:6; + u64 byte4:6; + u64 byte5:6; + u64 byte6:6; + u64 byte7:6; + u64 byte8:6; + u64 status:2; + u64 reserved_56_63:8; +#endif + } s; +}; + +union cvmx_lmcx_rodt_comp_ctl { + u64 u64; + struct cvmx_lmcx_rodt_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 enable:1; + u64 reserved_12_15:4; + u64 nctl:4; + u64 reserved_5_7:3; + u64 pctl:5; +#else + u64 pctl:5; + u64 reserved_5_7:3; + u64 nctl:4; + u64 reserved_12_15:4; + u64 enable:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_lmcx_rodt_ctl { + u64 u64; + struct cvmx_lmcx_rodt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rodt_hi3:4; + u64 rodt_hi2:4; + u64 rodt_hi1:4; + u64 rodt_hi0:4; + u64 rodt_lo3:4; + u64 rodt_lo2:4; + u64 rodt_lo1:4; + u64 rodt_lo0:4; +#else + u64 rodt_lo0:4; + u64 rodt_lo1:4; + u64 rodt_lo2:4; + u64 rodt_lo3:4; + u64 rodt_hi0:4; + u64 rodt_hi1:4; + u64 rodt_hi2:4; + u64 rodt_hi3:4; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_rodt_mask { + u64 u64; + struct cvmx_lmcx_rodt_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rodt_d3_r1:8; + u64 rodt_d3_r0:8; + u64 rodt_d2_r1:8; + u64 rodt_d2_r0:8; + u64 rodt_d1_r1:8; + u64 rodt_d1_r0:8; + u64 rodt_d0_r1:8; + u64 rodt_d0_r0:8; +#else + u64 rodt_d0_r0:8; + u64 rodt_d0_r1:8; + u64 rodt_d1_r0:8; + u64 rodt_d1_r1:8; + u64 rodt_d2_r0:8; + u64 rodt_d2_r1:8; + u64 rodt_d3_r0:8; + u64 rodt_d3_r1:8; +#endif + } s; +}; + +union cvmx_lmcx_scramble_cfg0 { + u64 u64; + struct cvmx_lmcx_scramble_cfg0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 key:64; +#else + u64 key:64; +#endif + } s; +}; + +union cvmx_lmcx_scramble_cfg1 { + u64 u64; + struct cvmx_lmcx_scramble_cfg1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 key:64; +#else + u64 key:64; +#endif + } s; +}; + +union cvmx_lmcx_scrambled_fadr { + u64 u64; + struct cvmx_lmcx_scrambled_fadr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 fdimm:2; + u64 fbunk:1; + u64 fbank:3; + u64 frow:16; + u64 fcol:14; +#else + u64 fcol:14; + u64 frow:16; + u64 fbank:3; + u64 fbunk:1; + u64 fdimm:2; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_lmcx_slot_ctl0 { + u64 u64; + struct cvmx_lmcx_slot_ctl0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 w2w_init:6; + u64 w2r_init:6; + u64 r2w_init:6; + u64 r2r_init:6; +#else + u64 r2r_init:6; + u64 r2w_init:6; + u64 w2r_init:6; + u64 w2w_init:6; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_lmcx_slot_ctl1 { + u64 u64; + struct cvmx_lmcx_slot_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 w2w_xrank_init:6; + u64 w2r_xrank_init:6; + u64 r2w_xrank_init:6; + u64 r2r_xrank_init:6; +#else + u64 r2r_xrank_init:6; + u64 r2w_xrank_init:6; + u64 w2r_xrank_init:6; + u64 w2w_xrank_init:6; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_lmcx_slot_ctl2 { + u64 u64; + struct cvmx_lmcx_slot_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 w2w_xdimm_init:6; + u64 w2r_xdimm_init:6; + u64 r2w_xdimm_init:6; + u64 r2r_xdimm_init:6; +#else + u64 r2r_xdimm_init:6; + u64 r2w_xdimm_init:6; + u64 w2r_xdimm_init:6; + u64 w2w_xdimm_init:6; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_lmcx_timing_params0 { + u64 u64; + struct cvmx_lmcx_timing_params0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 trp_ext:1; + u64 tcksre:4; + u64 trp:4; + u64 tzqinit:4; + u64 tdllk:4; + u64 tmod:4; + u64 tmrd:4; + u64 txpr:4; + u64 tcke:4; + u64 tzqcs:4; + u64 tckeon:10; +#else + u64 tckeon:10; + u64 tzqcs:4; + u64 tcke:4; + u64 txpr:4; + u64 tmrd:4; + u64 tmod:4; + u64 tdllk:4; + u64 tzqinit:4; + u64 trp:4; + u64 tcksre:4; + u64 trp_ext:1; + u64 reserved_47_63:17; +#endif + } s; + struct cvmx_lmcx_timing_params0_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 trp_ext:1; + u64 tcksre:4; + u64 trp:4; + u64 tzqinit:4; + u64 tdllk:4; + u64 tmod:4; + u64 tmrd:4; + u64 txpr:4; + u64 tcke:4; + u64 tzqcs:4; + u64 reserved_0_9:10; +#else + u64 reserved_0_9:10; + u64 tzqcs:4; + u64 tcke:4; + u64 txpr:4; + u64 tmrd:4; + u64 tmod:4; + u64 tdllk:4; + u64 tzqinit:4; + u64 trp:4; + u64 tcksre:4; + u64 trp_ext:1; + u64 reserved_47_63:17; +#endif + } cn61xx; + struct cvmx_lmcx_timing_params0_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 tcksre:4; + u64 trp:4; + u64 tzqinit:4; + u64 tdllk:4; + u64 tmod:4; + u64 tmrd:4; + u64 txpr:4; + u64 tcke:4; + u64 tzqcs:4; + u64 tckeon:10; +#else + u64 tckeon:10; + u64 tzqcs:4; + u64 tcke:4; + u64 txpr:4; + u64 tmrd:4; + u64 tmod:4; + u64 tdllk:4; + u64 tzqinit:4; + u64 trp:4; + u64 tcksre:4; + u64 reserved_46_63:18; +#endif + } cn63xxp1; +}; + +union cvmx_lmcx_timing_params1 { + u64 u64; + struct cvmx_lmcx_timing_params1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 tras_ext:1; + u64 txpdll:5; + u64 tfaw:5; + u64 twldqsen:4; + u64 twlmrd:4; + u64 txp:3; + u64 trrd:3; + u64 trfc:5; + u64 twtr:4; + u64 trcd:4; + u64 tras:5; + u64 tmprr:4; +#else + u64 tmprr:4; + u64 tras:5; + u64 trcd:4; + u64 twtr:4; + u64 trfc:5; + u64 trrd:3; + u64 txp:3; + u64 twlmrd:4; + u64 twldqsen:4; + u64 tfaw:5; + u64 txpdll:5; + u64 tras_ext:1; + u64 reserved_47_63:17; +#endif + } s; + struct cvmx_lmcx_timing_params1_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 txpdll:5; + u64 tfaw:5; + u64 twldqsen:4; + u64 twlmrd:4; + u64 txp:3; + u64 trrd:3; + u64 trfc:5; + u64 twtr:4; + u64 trcd:4; + u64 tras:5; + u64 tmprr:4; +#else + u64 tmprr:4; + u64 tras:5; + u64 trcd:4; + u64 twtr:4; + u64 trfc:5; + u64 trrd:3; + u64 txp:3; + u64 twlmrd:4; + u64 twldqsen:4; + u64 tfaw:5; + u64 txpdll:5; + u64 reserved_46_63:18; +#endif + } cn63xxp1; +}; + +union cvmx_lmcx_tro_ctl { + u64 u64; + struct cvmx_lmcx_tro_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 rclk_cnt:32; + u64 treset:1; +#else + u64 treset:1; + u64 rclk_cnt:32; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_lmcx_tro_stat { + u64 u64; + struct cvmx_lmcx_tro_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ring_cnt:32; +#else + u64 ring_cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_wlevel_ctl { + u64 u64; + struct cvmx_lmcx_wlevel_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 rtt_nom:3; + u64 bitmask:8; + u64 or_dis:1; + u64 sset:1; + u64 lanemask:9; +#else + u64 lanemask:9; + u64 sset:1; + u64 or_dis:1; + u64 bitmask:8; + u64 rtt_nom:3; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_lmcx_wlevel_ctl_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 sset:1; + u64 lanemask:9; +#else + u64 lanemask:9; + u64 sset:1; + u64 reserved_10_63:54; +#endif + } cn63xxp1; +}; + +union cvmx_lmcx_wlevel_dbg { + u64 u64; + struct cvmx_lmcx_wlevel_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 bitmask:8; + u64 byte:4; +#else + u64 byte:4; + u64 bitmask:8; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_lmcx_wlevel_rankx { + u64 u64; + struct cvmx_lmcx_wlevel_rankx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 status:2; + u64 byte8:5; + u64 byte7:5; + u64 byte6:5; + u64 byte5:5; + u64 byte4:5; + u64 byte3:5; + u64 byte2:5; + u64 byte1:5; + u64 byte0:5; +#else + u64 byte0:5; + u64 byte1:5; + u64 byte2:5; + u64 byte3:5; + u64 byte4:5; + u64 byte5:5; + u64 byte6:5; + u64 byte7:5; + u64 byte8:5; + u64 status:2; + u64 reserved_47_63:17; +#endif + } s; +}; + +union cvmx_lmcx_wodt_ctl0 { + u64 u64; + struct cvmx_lmcx_wodt_ctl0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_lmcx_wodt_ctl0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wodt_d1_r1:8; + u64 wodt_d1_r0:8; + u64 wodt_d0_r1:8; + u64 wodt_d0_r0:8; +#else + u64 wodt_d0_r0:8; + u64 wodt_d0_r1:8; + u64 wodt_d1_r0:8; + u64 wodt_d1_r1:8; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_lmcx_wodt_ctl0_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wodt_hi3:4; + u64 wodt_hi2:4; + u64 wodt_hi1:4; + u64 wodt_hi0:4; + u64 wodt_lo3:4; + u64 wodt_lo2:4; + u64 wodt_lo1:4; + u64 wodt_lo0:4; +#else + u64 wodt_lo0:4; + u64 wodt_lo1:4; + u64 wodt_lo2:4; + u64 wodt_lo3:4; + u64 wodt_hi0:4; + u64 wodt_hi1:4; + u64 wodt_hi2:4; + u64 wodt_hi3:4; + u64 reserved_32_63:32; +#endif + } cn38xx; +}; + +union cvmx_lmcx_wodt_ctl1 { + u64 u64; + struct cvmx_lmcx_wodt_ctl1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wodt_d3_r1:8; + u64 wodt_d3_r0:8; + u64 wodt_d2_r1:8; + u64 wodt_d2_r0:8; +#else + u64 wodt_d2_r0:8; + u64 wodt_d2_r1:8; + u64 wodt_d3_r0:8; + u64 wodt_d3_r1:8; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_lmcx_wodt_mask { + u64 u64; + struct cvmx_lmcx_wodt_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wodt_d3_r1:8; + u64 wodt_d3_r0:8; + u64 wodt_d2_r1:8; + u64 wodt_d2_r0:8; + u64 wodt_d1_r1:8; + u64 wodt_d1_r0:8; + u64 wodt_d0_r1:8; + u64 wodt_d0_r0:8; +#else + u64 wodt_d0_r0:8; + u64 wodt_d0_r1:8; + u64 wodt_d1_r0:8; + u64 wodt_d1_r1:8; + u64 wodt_d2_r0:8; + u64 wodt_d2_r1:8; + u64 wodt_d3_r0:8; + u64 wodt_d3_r1:8; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-mio-defs.h b/drivers/staging/octeon/cvmx-mio-defs.h new file mode 100644 index 000000000000..462934fd6fef --- /dev/null +++ b/drivers/staging/octeon/cvmx-mio-defs.h @@ -0,0 +1,4395 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_MIO_DEFS_H__ +#define __CVMX_MIO_DEFS_H__ + +#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull)) +#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull)) +#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8) +#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8) +#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8) +#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8) +#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull)) +#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull)) +#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull)) +#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8) +#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull)) +#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull)) +#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) +#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) +#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) +#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull)) +#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull)) +#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull)) +#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull)) +#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull)) +#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull)) +#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull)) +#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8) +#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull)) +#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull)) +#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull)) +#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull)) +#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull)) +#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull)) +#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull)) +#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull)) +#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) +#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) +#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) +#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull)) +#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull)) +#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull)) +#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull)) +#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull)) +#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull)) +#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull)) +#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull)) +#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull)) +#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull)) +#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull)) +#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) +#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) +#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) +#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull)) +#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) +#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) +#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) +#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull)) +#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull)) +#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) +#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) +#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) +#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull)) +#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull)) +#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull)) +#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull)) +#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) +#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) +#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) +#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) +#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) +#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) +#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) +#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) +#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) +#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull)) +#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) +#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) +#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) +#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) +#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull)) +#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8) +#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) +#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) +#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) +#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull)) +#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512) +#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512) +#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512) +#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512) +#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull)) +#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull)) +#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull)) +#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull)) +#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull)) +#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull)) +#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull)) +#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull)) +#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull)) +#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull)) +#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull)) +#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull)) +#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull)) +#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull)) +#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull)) +#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull)) +#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull)) +#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull)) +#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull)) +#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull)) +#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull)) +#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull)) +#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull)) +#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull)) +#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull)) +#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024) +#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024) + +union cvmx_mio_boot_bist_stat { + u64 u64; + struct cvmx_mio_boot_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_mio_boot_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 ncbo_1:1; + u64 ncbo_0:1; + u64 loc:1; + u64 ncbi:1; +#else + u64 ncbi:1; + u64 loc:1; + u64 ncbo_0:1; + u64 ncbo_1:1; + u64 reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_mio_boot_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 ncbo_0:1; + u64 loc:1; + u64 ncbi:1; +#else + u64 ncbi:1; + u64 loc:1; + u64 ncbo_0:1; + u64 reserved_3_63:61; +#endif + } cn38xx; + struct cvmx_mio_boot_bist_stat_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 pcm_1:1; + u64 pcm_0:1; + u64 ncbo_1:1; + u64 ncbo_0:1; + u64 loc:1; + u64 ncbi:1; +#else + u64 ncbi:1; + u64 loc:1; + u64 ncbo_0:1; + u64 ncbo_1:1; + u64 pcm_0:1; + u64 pcm_1:1; + u64 reserved_6_63:58; +#endif + } cn50xx; + struct cvmx_mio_boot_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 ndf:2; + u64 ncbo_0:1; + u64 dma:1; + u64 loc:1; + u64 ncbi:1; +#else + u64 ncbi:1; + u64 loc:1; + u64 dma:1; + u64 ncbo_0:1; + u64 ndf:2; + u64 reserved_6_63:58; +#endif + } cn52xx; + struct cvmx_mio_boot_bist_stat_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 ncbo_0:1; + u64 dma:1; + u64 loc:1; + u64 ncbi:1; +#else + u64 ncbi:1; + u64 loc:1; + u64 dma:1; + u64 ncbo_0:1; + u64 reserved_4_63:60; +#endif + } cn52xxp1; + struct cvmx_mio_boot_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 stat:12; +#else + u64 stat:12; + u64 reserved_12_63:52; +#endif + } cn61xx; + struct cvmx_mio_boot_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 stat:9; +#else + u64 stat:9; + u64 reserved_9_63:55; +#endif + } cn63xx; + struct cvmx_mio_boot_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 stat:10; +#else + u64 stat:10; + u64 reserved_10_63:54; +#endif + } cn66xx; +}; + +union cvmx_mio_boot_comp { + u64 u64; + struct cvmx_mio_boot_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_mio_boot_comp_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pctl:5; + u64 nctl:5; +#else + u64 nctl:5; + u64 pctl:5; + u64 reserved_10_63:54; +#endif + } cn50xx; + struct cvmx_mio_boot_comp_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 pctl:6; + u64 nctl:6; +#else + u64 nctl:6; + u64 pctl:6; + u64 reserved_12_63:52; +#endif + } cn61xx; +}; + +union cvmx_mio_boot_dma_cfgx { + u64 u64; + struct cvmx_mio_boot_dma_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 en:1; + u64 rw:1; + u64 clr:1; + u64 reserved_60_60:1; + u64 swap32:1; + u64 swap16:1; + u64 swap8:1; + u64 endian:1; + u64 size:20; + u64 adr:36; +#else + u64 adr:36; + u64 size:20; + u64 endian:1; + u64 swap8:1; + u64 swap16:1; + u64 swap32:1; + u64 reserved_60_60:1; + u64 clr:1; + u64 rw:1; + u64 en:1; +#endif + } s; +}; + +union cvmx_mio_boot_dma_intx { + u64 u64; + struct cvmx_mio_boot_dma_intx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 dmarq:1; + u64 done:1; +#else + u64 done:1; + u64 dmarq:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_boot_dma_int_enx { + u64 u64; + struct cvmx_mio_boot_dma_int_enx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 dmarq:1; + u64 done:1; +#else + u64 done:1; + u64 dmarq:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_boot_dma_timx { + u64 u64; + struct cvmx_mio_boot_dma_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dmack_pi:1; + u64 dmarq_pi:1; + u64 tim_mult:2; + u64 rd_dly:3; + u64 ddr:1; + u64 width:1; + u64 reserved_48_54:7; + u64 pause:6; + u64 dmack_h:6; + u64 we_n:6; + u64 we_a:6; + u64 oe_n:6; + u64 oe_a:6; + u64 dmack_s:6; + u64 dmarq:6; +#else + u64 dmarq:6; + u64 dmack_s:6; + u64 oe_a:6; + u64 oe_n:6; + u64 we_a:6; + u64 we_n:6; + u64 dmack_h:6; + u64 pause:6; + u64 reserved_48_54:7; + u64 width:1; + u64 ddr:1; + u64 rd_dly:3; + u64 tim_mult:2; + u64 dmarq_pi:1; + u64 dmack_pi:1; +#endif + } s; +}; + +union cvmx_mio_boot_err { + u64 u64; + struct cvmx_mio_boot_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 wait_err:1; + u64 adr_err:1; +#else + u64 adr_err:1; + u64 wait_err:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_boot_int { + u64 u64; + struct cvmx_mio_boot_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 wait_int:1; + u64 adr_int:1; +#else + u64 adr_int:1; + u64 wait_int:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_boot_loc_adr { + u64 u64; + struct cvmx_mio_boot_loc_adr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 adr:5; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 adr:5; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_boot_loc_cfgx { + u64 u64; + struct cvmx_mio_boot_loc_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 en:1; + u64 reserved_28_30:3; + u64 base:25; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 base:25; + u64 reserved_28_30:3; + u64 en:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_boot_loc_dat { + u64 u64; + struct cvmx_mio_boot_loc_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_mio_boot_pin_defs { + u64 u64; + struct cvmx_mio_boot_pin_defs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 user1:16; + u64 ale:1; + u64 width:1; + u64 dmack_p2:1; + u64 dmack_p1:1; + u64 dmack_p0:1; + u64 term:2; + u64 nand:1; + u64 user0:8; +#else + u64 user0:8; + u64 nand:1; + u64 term:2; + u64 dmack_p0:1; + u64 dmack_p1:1; + u64 dmack_p2:1; + u64 width:1; + u64 ale:1; + u64 user1:16; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_mio_boot_pin_defs_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 ale:1; + u64 width:1; + u64 reserved_13_13:1; + u64 dmack_p1:1; + u64 dmack_p0:1; + u64 term:2; + u64 nand:1; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 nand:1; + u64 term:2; + u64 dmack_p0:1; + u64 dmack_p1:1; + u64 reserved_13_13:1; + u64 width:1; + u64 ale:1; + u64 reserved_16_63:48; +#endif + } cn52xx; + struct cvmx_mio_boot_pin_defs_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 ale:1; + u64 width:1; + u64 dmack_p2:1; + u64 dmack_p1:1; + u64 dmack_p0:1; + u64 term:2; + u64 reserved_0_8:9; +#else + u64 reserved_0_8:9; + u64 term:2; + u64 dmack_p0:1; + u64 dmack_p1:1; + u64 dmack_p2:1; + u64 width:1; + u64 ale:1; + u64 reserved_16_63:48; +#endif + } cn56xx; + struct cvmx_mio_boot_pin_defs_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 user1:16; + u64 ale:1; + u64 width:1; + u64 reserved_13_13:1; + u64 dmack_p1:1; + u64 dmack_p0:1; + u64 term:2; + u64 nand:1; + u64 user0:8; +#else + u64 user0:8; + u64 nand:1; + u64 term:2; + u64 dmack_p0:1; + u64 dmack_p1:1; + u64 reserved_13_13:1; + u64 width:1; + u64 ale:1; + u64 user1:16; + u64 reserved_32_63:32; +#endif + } cn61xx; +}; + +union cvmx_mio_boot_reg_cfgx { + u64 u64; + struct cvmx_mio_boot_reg_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 dmack:2; + u64 tim_mult:2; + u64 rd_dly:3; + u64 sam:1; + u64 we_ext:2; + u64 oe_ext:2; + u64 en:1; + u64 orbit:1; + u64 ale:1; + u64 width:1; + u64 size:12; + u64 base:16; +#else + u64 base:16; + u64 size:12; + u64 width:1; + u64 ale:1; + u64 orbit:1; + u64 en:1; + u64 oe_ext:2; + u64 we_ext:2; + u64 sam:1; + u64 rd_dly:3; + u64 tim_mult:2; + u64 dmack:2; + u64 reserved_44_63:20; +#endif + } s; + struct cvmx_mio_boot_reg_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 sam:1; + u64 we_ext:2; + u64 oe_ext:2; + u64 en:1; + u64 orbit:1; + u64 ale:1; + u64 width:1; + u64 size:12; + u64 base:16; +#else + u64 base:16; + u64 size:12; + u64 width:1; + u64 ale:1; + u64 orbit:1; + u64 en:1; + u64 oe_ext:2; + u64 we_ext:2; + u64 sam:1; + u64 reserved_37_63:27; +#endif + } cn30xx; + struct cvmx_mio_boot_reg_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 en:1; + u64 orbit:1; + u64 reserved_28_29:2; + u64 size:12; + u64 base:16; +#else + u64 base:16; + u64 size:12; + u64 reserved_28_29:2; + u64 orbit:1; + u64 en:1; + u64 reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_mio_boot_reg_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 tim_mult:2; + u64 rd_dly:3; + u64 sam:1; + u64 we_ext:2; + u64 oe_ext:2; + u64 en:1; + u64 orbit:1; + u64 ale:1; + u64 width:1; + u64 size:12; + u64 base:16; +#else + u64 base:16; + u64 size:12; + u64 width:1; + u64 ale:1; + u64 orbit:1; + u64 en:1; + u64 oe_ext:2; + u64 we_ext:2; + u64 sam:1; + u64 rd_dly:3; + u64 tim_mult:2; + u64 reserved_42_63:22; +#endif + } cn50xx; +}; + +union cvmx_mio_boot_reg_timx { + u64 u64; + struct cvmx_mio_boot_reg_timx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pagem:1; + u64 waitm:1; + u64 pages:2; + u64 ale:6; + u64 page:6; + u64 wait:6; + u64 pause:6; + u64 wr_hld:6; + u64 rd_hld:6; + u64 we:6; + u64 oe:6; + u64 ce:6; + u64 adr:6; +#else + u64 adr:6; + u64 ce:6; + u64 oe:6; + u64 we:6; + u64 rd_hld:6; + u64 wr_hld:6; + u64 pause:6; + u64 wait:6; + u64 page:6; + u64 ale:6; + u64 pages:2; + u64 waitm:1; + u64 pagem:1; +#endif + } s; + struct cvmx_mio_boot_reg_timx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pagem:1; + u64 waitm:1; + u64 pages:2; + u64 reserved_54_59:6; + u64 page:6; + u64 wait:6; + u64 pause:6; + u64 wr_hld:6; + u64 rd_hld:6; + u64 we:6; + u64 oe:6; + u64 ce:6; + u64 adr:6; +#else + u64 adr:6; + u64 ce:6; + u64 oe:6; + u64 we:6; + u64 rd_hld:6; + u64 wr_hld:6; + u64 pause:6; + u64 wait:6; + u64 page:6; + u64 reserved_54_59:6; + u64 pages:2; + u64 waitm:1; + u64 pagem:1; +#endif + } cn38xx; +}; + +union cvmx_mio_boot_thr { + u64 u64; + struct cvmx_mio_boot_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 dma_thr:6; + u64 reserved_14_15:2; + u64 fif_cnt:6; + u64 reserved_6_7:2; + u64 fif_thr:6; +#else + u64 fif_thr:6; + u64 reserved_6_7:2; + u64 fif_cnt:6; + u64 reserved_14_15:2; + u64 dma_thr:6; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_mio_boot_thr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 fif_cnt:6; + u64 reserved_6_7:2; + u64 fif_thr:6; +#else + u64 fif_thr:6; + u64 reserved_6_7:2; + u64 fif_cnt:6; + u64 reserved_14_63:50; +#endif + } cn30xx; +}; + +union cvmx_mio_emm_buf_dat { + u64 u64; + struct cvmx_mio_emm_buf_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dat:64; +#else + u64 dat:64; +#endif + } s; +}; + +union cvmx_mio_emm_buf_idx { + u64 u64; + struct cvmx_mio_emm_buf_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 inc:1; + u64 reserved_7_15:9; + u64 buf_num:1; + u64 offset:6; +#else + u64 offset:6; + u64 buf_num:1; + u64 reserved_7_15:9; + u64 inc:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_mio_emm_cfg { + u64 u64; + struct cvmx_mio_emm_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 boot_fail:1; + u64 reserved_4_15:12; + u64 bus_ena:4; +#else + u64 bus_ena:4; + u64 reserved_4_15:12; + u64 boot_fail:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_mio_emm_cmd { + u64 u64; + struct cvmx_mio_emm_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 bus_id:2; + u64 cmd_val:1; + u64 reserved_56_58:3; + u64 dbuf:1; + u64 offset:6; + u64 reserved_43_48:6; + u64 ctype_xor:2; + u64 rtype_xor:3; + u64 cmd_idx:6; + u64 arg:32; +#else + u64 arg:32; + u64 cmd_idx:6; + u64 rtype_xor:3; + u64 ctype_xor:2; + u64 reserved_43_48:6; + u64 offset:6; + u64 dbuf:1; + u64 reserved_56_58:3; + u64 cmd_val:1; + u64 bus_id:2; + u64 reserved_62_63:2; +#endif + } s; +}; + +union cvmx_mio_emm_dma { + u64 u64; + struct cvmx_mio_emm_dma_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 bus_id:2; + u64 dma_val:1; + u64 sector:1; + u64 dat_null:1; + u64 thres:6; + u64 rel_wr:1; + u64 rw:1; + u64 multi:1; + u64 block_cnt:16; + u64 card_addr:32; +#else + u64 card_addr:32; + u64 block_cnt:16; + u64 multi:1; + u64 rw:1; + u64 rel_wr:1; + u64 thres:6; + u64 dat_null:1; + u64 sector:1; + u64 dma_val:1; + u64 bus_id:2; + u64 reserved_62_63:2; +#endif + } s; +}; + +union cvmx_mio_emm_int { + u64 u64; + struct cvmx_mio_emm_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 switch_err:1; + u64 switch_done:1; + u64 dma_err:1; + u64 cmd_err:1; + u64 dma_done:1; + u64 cmd_done:1; + u64 buf_done:1; +#else + u64 buf_done:1; + u64 cmd_done:1; + u64 dma_done:1; + u64 cmd_err:1; + u64 dma_err:1; + u64 switch_done:1; + u64 switch_err:1; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_emm_int_en { + u64 u64; + struct cvmx_mio_emm_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 switch_err:1; + u64 switch_done:1; + u64 dma_err:1; + u64 cmd_err:1; + u64 dma_done:1; + u64 cmd_done:1; + u64 buf_done:1; +#else + u64 buf_done:1; + u64 cmd_done:1; + u64 dma_done:1; + u64 cmd_err:1; + u64 dma_err:1; + u64 switch_done:1; + u64 switch_err:1; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_emm_modex { + u64 u64; + struct cvmx_mio_emm_modex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 hs_timing:1; + u64 reserved_43_47:5; + u64 bus_width:3; + u64 reserved_36_39:4; + u64 power_class:4; + u64 clk_hi:16; + u64 clk_lo:16; +#else + u64 clk_lo:16; + u64 clk_hi:16; + u64 power_class:4; + u64 reserved_36_39:4; + u64 bus_width:3; + u64 reserved_43_47:5; + u64 hs_timing:1; + u64 reserved_49_63:15; +#endif + } s; +}; + +union cvmx_mio_emm_rca { + u64 u64; + struct cvmx_mio_emm_rca_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 card_rca:16; +#else + u64 card_rca:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_mio_emm_rsp_hi { + u64 u64; + struct cvmx_mio_emm_rsp_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dat:64; +#else + u64 dat:64; +#endif + } s; +}; + +union cvmx_mio_emm_rsp_lo { + u64 u64; + struct cvmx_mio_emm_rsp_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dat:64; +#else + u64 dat:64; +#endif + } s; +}; + +union cvmx_mio_emm_rsp_sts { + u64 u64; + struct cvmx_mio_emm_rsp_sts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 bus_id:2; + u64 cmd_val:1; + u64 switch_val:1; + u64 dma_val:1; + u64 dma_pend:1; + u64 reserved_29_55:27; + u64 dbuf_err:1; + u64 reserved_24_27:4; + u64 dbuf:1; + u64 blk_timeout:1; + u64 blk_crc_err:1; + u64 rsp_busybit:1; + u64 stp_timeout:1; + u64 stp_crc_err:1; + u64 stp_bad_sts:1; + u64 stp_val:1; + u64 rsp_timeout:1; + u64 rsp_crc_err:1; + u64 rsp_bad_sts:1; + u64 rsp_val:1; + u64 rsp_type:3; + u64 cmd_type:2; + u64 cmd_idx:6; + u64 cmd_done:1; +#else + u64 cmd_done:1; + u64 cmd_idx:6; + u64 cmd_type:2; + u64 rsp_type:3; + u64 rsp_val:1; + u64 rsp_bad_sts:1; + u64 rsp_crc_err:1; + u64 rsp_timeout:1; + u64 stp_val:1; + u64 stp_bad_sts:1; + u64 stp_crc_err:1; + u64 stp_timeout:1; + u64 rsp_busybit:1; + u64 blk_crc_err:1; + u64 blk_timeout:1; + u64 dbuf:1; + u64 reserved_24_27:4; + u64 dbuf_err:1; + u64 reserved_29_55:27; + u64 dma_pend:1; + u64 dma_val:1; + u64 switch_val:1; + u64 cmd_val:1; + u64 bus_id:2; + u64 reserved_62_63:2; +#endif + } s; +}; + +union cvmx_mio_emm_sample { + u64 u64; + struct cvmx_mio_emm_sample_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 cmd_cnt:10; + u64 reserved_10_15:6; + u64 dat_cnt:10; +#else + u64 dat_cnt:10; + u64 reserved_10_15:6; + u64 cmd_cnt:10; + u64 reserved_26_63:38; +#endif + } s; +}; + +union cvmx_mio_emm_sts_mask { + u64 u64; + struct cvmx_mio_emm_sts_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 sts_msk:32; +#else + u64 sts_msk:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_emm_switch { + u64 u64; + struct cvmx_mio_emm_switch_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 bus_id:2; + u64 switch_exe:1; + u64 switch_err0:1; + u64 switch_err1:1; + u64 switch_err2:1; + u64 reserved_49_55:7; + u64 hs_timing:1; + u64 reserved_43_47:5; + u64 bus_width:3; + u64 reserved_36_39:4; + u64 power_class:4; + u64 clk_hi:16; + u64 clk_lo:16; +#else + u64 clk_lo:16; + u64 clk_hi:16; + u64 power_class:4; + u64 reserved_36_39:4; + u64 bus_width:3; + u64 reserved_43_47:5; + u64 hs_timing:1; + u64 reserved_49_55:7; + u64 switch_err2:1; + u64 switch_err1:1; + u64 switch_err0:1; + u64 switch_exe:1; + u64 bus_id:2; + u64 reserved_62_63:2; +#endif + } s; +}; + +union cvmx_mio_emm_wdog { + u64 u64; + struct cvmx_mio_emm_wdog_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 clk_cnt:26; +#else + u64 clk_cnt:26; + u64 reserved_26_63:38; +#endif + } s; +}; + +union cvmx_mio_fus_bnk_datx { + u64 u64; + struct cvmx_mio_fus_bnk_datx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dat:64; +#else + u64 dat:64; +#endif + } s; +}; + +union cvmx_mio_fus_dat0 { + u64 u64; + struct cvmx_mio_fus_dat0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 man_info:32; +#else + u64 man_info:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_fus_dat1 { + u64 u64; + struct cvmx_mio_fus_dat1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 man_info:32; +#else + u64 man_info:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_fus_dat2 { + u64 u64; + struct cvmx_mio_fus_dat2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 run_platform:3; + u64 gbl_pwr_throttle:8; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_30_31:2; + u64 nokasu:1; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 nokasu:1; + u64 reserved_30_31:2; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 gbl_pwr_throttle:8; + u64 run_platform:3; + u64 reserved_59_63:5; +#endif + } s; + struct cvmx_mio_fus_dat2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 pll_off:4; + u64 reserved_1_11:11; + u64 pp_dis:1; +#else + u64 pp_dis:1; + u64 reserved_1_11:11; + u64 pll_off:4; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_mio_fus_dat2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 pll_off:4; + u64 reserved_2_11:10; + u64 pp_dis:2; +#else + u64 pp_dis:2; + u64 reserved_2_11:10; + u64 pll_off:4; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_63:35; +#endif + } cn31xx; + struct cvmx_mio_fus_dat2_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 pp_dis:16; +#else + u64 pp_dis:16; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_63:35; +#endif + } cn38xx; + struct cvmx_mio_fus_dat2_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_30_31:2; + u64 nokasu:1; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 reserved_2_15:14; + u64 pp_dis:2; +#else + u64 pp_dis:2; + u64 reserved_2_15:14; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 nokasu:1; + u64 reserved_30_31:2; + u64 raid_en:1; + u64 fus318:1; + u64 reserved_34_63:30; +#endif + } cn50xx; + struct cvmx_mio_fus_dat2_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_30_31:2; + u64 nokasu:1; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 reserved_4_15:12; + u64 pp_dis:4; +#else + u64 pp_dis:4; + u64 reserved_4_15:12; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 nokasu:1; + u64 reserved_30_31:2; + u64 raid_en:1; + u64 fus318:1; + u64 reserved_34_63:30; +#endif + } cn52xx; + struct cvmx_mio_fus_dat2_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_30_31:2; + u64 nokasu:1; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 reserved_12_15:4; + u64 pp_dis:12; +#else + u64 pp_dis:12; + u64 reserved_12_15:4; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 nokasu:1; + u64 reserved_30_31:2; + u64 raid_en:1; + u64 fus318:1; + u64 reserved_34_63:30; +#endif + } cn56xx; + struct cvmx_mio_fus_dat2_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_30_63:34; + u64 nokasu:1; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 rst_sht:1; + u64 bist_dis:1; + u64 chip_id:8; + u64 pp_dis:16; +#else + u64 pp_dis:16; + u64 chip_id:8; + u64 bist_dis:1; + u64 rst_sht:1; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 nokasu:1; + u64 reserved_30_63:34; +#endif + } cn58xx; + struct cvmx_mio_fus_dat2_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_29_31:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_24_25:2; + u64 chip_id:8; + u64 reserved_4_15:12; + u64 pp_dis:4; +#else + u64 pp_dis:4; + u64 reserved_4_15:12; + u64 chip_id:8; + u64 reserved_24_25:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_31:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 reserved_48_63:16; +#endif + } cn61xx; + struct cvmx_mio_fus_dat2_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_29_31:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_24_25:2; + u64 chip_id:8; + u64 reserved_6_15:10; + u64 pp_dis:6; +#else + u64 pp_dis:6; + u64 reserved_6_15:10; + u64 chip_id:8; + u64 reserved_24_25:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_31:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 reserved_35_63:29; +#endif + } cn63xx; + struct cvmx_mio_fus_dat2_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_29_31:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_24_25:2; + u64 chip_id:8; + u64 reserved_10_15:6; + u64 pp_dis:10; +#else + u64 pp_dis:10; + u64 reserved_10_15:6; + u64 chip_id:8; + u64 reserved_24_25:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_31:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 reserved_48_63:16; +#endif + } cn66xx; + struct cvmx_mio_fus_dat2_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_29_31:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_24_25:2; + u64 chip_id:8; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 chip_id:8; + u64 reserved_24_25:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_29_31:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 reserved_37_63:27; +#endif + } cn68xx; + struct cvmx_mio_fus_dat2_cn70xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_31_29:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_25_24:2; + u64 chip_id:8; + u64 reserved_15_0:16; +#else + u64 reserved_15_0:16; + u64 chip_id:8; + u64 reserved_25_24:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_31_29:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 reserved_48_63:16; +#endif + } cn70xx; + struct cvmx_mio_fus_dat2_cn73xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 run_platform:3; + u64 gbl_pwr_throttle:8; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_31_29:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_25_24:2; + u64 chip_id:8; + u64 reserved_15_0:16; +#else + u64 reserved_15_0:16; + u64 chip_id:8; + u64 reserved_25_24:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_31_29:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 gbl_pwr_throttle:8; + u64 run_platform:3; + u64 reserved_59_63:5; +#endif + } cn73xx; + struct cvmx_mio_fus_dat2_cn78xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 run_platform:3; + u64 reserved_48_55:8; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_31_29:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_25_24:2; + u64 chip_id:8; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 chip_id:8; + u64 reserved_25_24:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_31_29:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 reserved_48_55:8; + u64 run_platform:3; + u64 reserved_59_63:5; +#endif + } cn78xx; + struct cvmx_mio_fus_dat2_cn78xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 run_platform:3; + u64 gbl_pwr_throttle:8; + u64 fus118:1; + u64 rom_info:10; + u64 power_limit:2; + u64 dorm_crypto:1; + u64 fus318:1; + u64 raid_en:1; + u64 reserved_31_29:3; + u64 nodfa_cp2:1; + u64 nomul:1; + u64 nocrypto:1; + u64 reserved_25_24:2; + u64 chip_id:8; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 chip_id:8; + u64 reserved_25_24:2; + u64 nocrypto:1; + u64 nomul:1; + u64 nodfa_cp2:1; + u64 reserved_31_29:3; + u64 raid_en:1; + u64 fus318:1; + u64 dorm_crypto:1; + u64 power_limit:2; + u64 rom_info:10; + u64 fus118:1; + u64 gbl_pwr_throttle:8; + u64 run_platform:3; + u64 reserved_59_63:5; +#endif + } cn78xxp2; +}; + +union cvmx_mio_fus_dat3 { + u64 u64; + struct cvmx_mio_fus_dat3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 pll_alt_matrix:1; + u64 reserved_38_39:2; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 reserved_28_31:4; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 reserved_0_23:24; +#else + u64 reserved_0_23:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 reserved_28_31:4; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 reserved_38_39:2; + u64 pll_alt_matrix:1; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } s; + struct cvmx_mio_fus_dat3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pll_div4:1; + u64 reserved_29_30:2; + u64 bar2_en:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 icache:24; +#else + u64 icache:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_en:1; + u64 reserved_29_30:2; + u64 pll_div4:1; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_mio_fus_dat3_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pll_div4:1; + u64 zip_crip:2; + u64 bar2_en:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 icache:24; +#else + u64 icache:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_en:1; + u64 zip_crip:2; + u64 pll_div4:1; + u64 reserved_32_63:32; +#endif + } cn31xx; + struct cvmx_mio_fus_dat3_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 zip_crip:2; + u64 bar2_en:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 icache:24; +#else + u64 icache:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_en:1; + u64 zip_crip:2; + u64 reserved_31_63:33; +#endif + } cn38xx; + struct cvmx_mio_fus_dat3_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 bar2_en:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 icache:24; +#else + u64 icache:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_en:1; + u64 reserved_29_63:35; +#endif + } cn38xxp2; + struct cvmx_mio_fus_dat3_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_58_63:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 reserved_40_40:1; + u64 ema:2; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 reserved_31_31:1; + u64 zip_info:2; + u64 bar2_en:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 reserved_0_23:24; +#else + u64 reserved_0_23:24; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_en:1; + u64 zip_info:2; + u64 reserved_31_31:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 ema:2; + u64 reserved_40_40:1; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 reserved_58_63:6; +#endif + } cn61xx; + struct cvmx_mio_fus_dat3_cn70xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 pll_alt_matrix:1; + u64 pll_bwadj_denom:2; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 use_int_refclk:1; + u64 zip_info:2; + u64 bar2_sz_conf:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 ema1:6; + u64 reserved_0_17:18; +#else + u64 reserved_0_17:18; + u64 ema1:6; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_sz_conf:1; + u64 zip_info:2; + u64 use_int_refclk:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 pll_bwadj_denom:2; + u64 pll_alt_matrix:1; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } cn70xx; + struct cvmx_mio_fus_dat3_cn70xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 reserved_38_40:3; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 reserved_31_31:1; + u64 zip_info:2; + u64 bar2_sz_conf:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 ema1:6; + u64 reserved_0_17:18; +#else + u64 reserved_0_17:18; + u64 ema1:6; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_sz_conf:1; + u64 zip_info:2; + u64 reserved_31_31:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 reserved_38_40:3; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } cn70xxp1; + struct cvmx_mio_fus_dat3_cn73xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 pll_alt_matrix:1; + u64 pll_bwadj_denom:2; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 use_int_refclk:1; + u64 zip_info:2; + u64 bar2_sz_conf:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 ema1:6; + u64 nohna_dte:1; + u64 hna_info_dte:3; + u64 hna_info_clm:4; + u64 reserved_9_9:1; + u64 core_pll_mul:5; + u64 pnr_pll_mul:4; +#else + u64 pnr_pll_mul:4; + u64 core_pll_mul:5; + u64 reserved_9_9:1; + u64 hna_info_clm:4; + u64 hna_info_dte:3; + u64 nohna_dte:1; + u64 ema1:6; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_sz_conf:1; + u64 zip_info:2; + u64 use_int_refclk:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 pll_bwadj_denom:2; + u64 pll_alt_matrix:1; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } cn73xx; + struct cvmx_mio_fus_dat3_cn78xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 reserved_38_40:3; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 reserved_31_31:1; + u64 zip_info:2; + u64 bar2_sz_conf:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 ema1:6; + u64 nohna_dte:1; + u64 hna_info_dte:3; + u64 hna_info_clm:4; + u64 reserved_0_9:10; +#else + u64 reserved_0_9:10; + u64 hna_info_clm:4; + u64 hna_info_dte:3; + u64 nohna_dte:1; + u64 ema1:6; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_sz_conf:1; + u64 zip_info:2; + u64 reserved_31_31:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 reserved_38_40:3; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } cn78xx; + struct cvmx_mio_fus_dat3_cnf75xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ema0:6; + u64 pll_ctl:10; + u64 dfa_info_dte:3; + u64 dfa_info_clm:4; + u64 pll_alt_matrix:1; + u64 pll_bwadj_denom:2; + u64 efus_lck_rsv:1; + u64 efus_lck_man:1; + u64 pll_half_dis:1; + u64 l2c_crip:3; + u64 use_int_refclk:1; + u64 zip_info:2; + u64 bar2_sz_conf:1; + u64 efus_lck:1; + u64 efus_ign:1; + u64 nozip:1; + u64 nodfa_dte:1; + u64 ema1:6; + u64 reserved_9_17:9; + u64 core_pll_mul:5; + u64 pnr_pll_mul:4; +#else + u64 pnr_pll_mul:4; + u64 core_pll_mul:5; + u64 reserved_9_17:9; + u64 ema1:6; + u64 nodfa_dte:1; + u64 nozip:1; + u64 efus_ign:1; + u64 efus_lck:1; + u64 bar2_sz_conf:1; + u64 zip_info:2; + u64 use_int_refclk:1; + u64 l2c_crip:3; + u64 pll_half_dis:1; + u64 efus_lck_man:1; + u64 efus_lck_rsv:1; + u64 pll_bwadj_denom:2; + u64 pll_alt_matrix:1; + u64 dfa_info_clm:4; + u64 dfa_info_dte:3; + u64 pll_ctl:10; + u64 ema0:6; +#endif + } cnf75xx; +}; + +union cvmx_mio_fus_ema { + u64 u64; + struct cvmx_mio_fus_ema_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 eff_ema:3; + u64 reserved_3_3:1; + u64 ema:3; +#else + u64 ema:3; + u64 reserved_3_3:1; + u64 eff_ema:3; + u64 reserved_7_63:57; +#endif + } s; + struct cvmx_mio_fus_ema_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 ema:2; +#else + u64 ema:2; + u64 reserved_2_63:62; +#endif + } cn58xx; +}; + +union cvmx_mio_fus_pdf { + u64 u64; + struct cvmx_mio_fus_pdf_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pdf:64; +#else + u64 pdf:64; +#endif + } s; +}; + +union cvmx_mio_fus_pll { + u64 u64; + struct cvmx_mio_fus_pll_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 rclk_align_r:8; + u64 rclk_align_l:8; + u64 reserved_8_31:24; + u64 c_cout_rst:1; + u64 c_cout_sel:2; + u64 pnr_cout_rst:1; + u64 pnr_cout_sel:2; + u64 rfslip:1; + u64 fbslip:1; +#else + u64 fbslip:1; + u64 rfslip:1; + u64 pnr_cout_sel:2; + u64 pnr_cout_rst:1; + u64 c_cout_sel:2; + u64 c_cout_rst:1; + u64 reserved_8_31:24; + u64 rclk_align_l:8; + u64 rclk_align_r:8; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_mio_fus_pll_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 rfslip:1; + u64 fbslip:1; +#else + u64 fbslip:1; + u64 rfslip:1; + u64 reserved_2_63:62; +#endif + } cn50xx; + struct cvmx_mio_fus_pll_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 c_cout_rst:1; + u64 c_cout_sel:2; + u64 pnr_cout_rst:1; + u64 pnr_cout_sel:2; + u64 rfslip:1; + u64 fbslip:1; +#else + u64 fbslip:1; + u64 rfslip:1; + u64 pnr_cout_sel:2; + u64 pnr_cout_rst:1; + u64 c_cout_sel:2; + u64 c_cout_rst:1; + u64 reserved_8_63:56; +#endif + } cn61xx; +}; + +union cvmx_mio_fus_prog { + u64 u64; + struct cvmx_mio_fus_prog_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 soft:1; + u64 prog:1; +#else + u64 prog:1; + u64 soft:1; + u64 reserved_2_63:62; +#endif + } s; + struct cvmx_mio_fus_prog_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 prog:1; +#else + u64 prog:1; + u64 reserved_1_63:63; +#endif + } cn30xx; +}; + +union cvmx_mio_fus_prog_times { + u64 u64; + struct cvmx_mio_fus_prog_times_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 vgate_pin:1; + u64 fsrc_pin:1; + u64 prog_pin:1; + u64 reserved_6_31:26; + u64 setup:6; +#else + u64 setup:6; + u64 reserved_6_31:26; + u64 prog_pin:1; + u64 fsrc_pin:1; + u64 vgate_pin:1; + u64 reserved_35_63:29; +#endif + } s; + struct cvmx_mio_fus_prog_times_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 prog_pin:1; + u64 out:8; + u64 sclk_lo:4; + u64 sclk_hi:12; + u64 setup:8; +#else + u64 setup:8; + u64 sclk_hi:12; + u64 sclk_lo:4; + u64 out:8; + u64 prog_pin:1; + u64 reserved_33_63:31; +#endif + } cn50xx; + struct cvmx_mio_fus_prog_times_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 vgate_pin:1; + u64 fsrc_pin:1; + u64 prog_pin:1; + u64 out:7; + u64 sclk_lo:4; + u64 sclk_hi:15; + u64 setup:6; +#else + u64 setup:6; + u64 sclk_hi:15; + u64 sclk_lo:4; + u64 out:7; + u64 prog_pin:1; + u64 fsrc_pin:1; + u64 vgate_pin:1; + u64 reserved_35_63:29; +#endif + } cn61xx; +}; + +union cvmx_mio_fus_rcmd { + u64 u64; + struct cvmx_mio_fus_rcmd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 dat:8; + u64 reserved_13_15:3; + u64 pend:1; + u64 reserved_9_11:3; + u64 efuse:1; + u64 addr:8; +#else + u64 addr:8; + u64 efuse:1; + u64 reserved_9_11:3; + u64 pend:1; + u64 reserved_13_15:3; + u64 dat:8; + u64 reserved_24_63:40; +#endif + } s; + struct cvmx_mio_fus_rcmd_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 dat:8; + u64 reserved_13_15:3; + u64 pend:1; + u64 reserved_9_11:3; + u64 efuse:1; + u64 reserved_7_7:1; + u64 addr:7; +#else + u64 addr:7; + u64 reserved_7_7:1; + u64 efuse:1; + u64 reserved_9_11:3; + u64 pend:1; + u64 reserved_13_15:3; + u64 dat:8; + u64 reserved_24_63:40; +#endif + } cn30xx; +}; + +union cvmx_mio_fus_read_times { + u64 u64; + struct cvmx_mio_fus_read_times_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 sch:4; + u64 fsh:4; + u64 prh:4; + u64 sdh:4; + u64 setup:10; +#else + u64 setup:10; + u64 sdh:4; + u64 prh:4; + u64 fsh:4; + u64 sch:4; + u64 reserved_26_63:38; +#endif + } s; +}; + +union cvmx_mio_fus_repair_res0 { + u64 u64; + struct cvmx_mio_fus_repair_res0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_55_63:9; + u64 too_many:1; + u64 repair2:18; + u64 repair1:18; + u64 repair0:18; +#else + u64 repair0:18; + u64 repair1:18; + u64 repair2:18; + u64 too_many:1; + u64 reserved_55_63:9; +#endif + } s; +}; + +union cvmx_mio_fus_repair_res1 { + u64 u64; + struct cvmx_mio_fus_repair_res1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 repair5:18; + u64 repair4:18; + u64 repair3:18; +#else + u64 repair3:18; + u64 repair4:18; + u64 repair5:18; + u64 reserved_54_63:10; +#endif + } s; +}; + +union cvmx_mio_fus_repair_res2 { + u64 u64; + struct cvmx_mio_fus_repair_res2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 repair6:18; +#else + u64 repair6:18; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_mio_fus_spr_repair_res { + u64 u64; + struct cvmx_mio_fus_spr_repair_res_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 repair2:14; + u64 repair1:14; + u64 repair0:14; +#else + u64 repair0:14; + u64 repair1:14; + u64 repair2:14; + u64 reserved_42_63:22; +#endif + } s; +}; + +union cvmx_mio_fus_spr_repair_sum { + u64 u64; + struct cvmx_mio_fus_spr_repair_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 too_many:1; +#else + u64 too_many:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_fus_tgg { + u64 u64; + struct cvmx_mio_fus_tgg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 val:1; + u64 dat:63; +#else + u64 dat:63; + u64 val:1; +#endif + } s; +}; + +union cvmx_mio_fus_unlock { + u64 u64; + struct cvmx_mio_fus_unlock_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 key:24; +#else + u64 key:24; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_mio_fus_wadr { + u64 u64; + struct cvmx_mio_fus_wadr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 addr:10; +#else + u64 addr:10; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_mio_fus_wadr_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 addr:2; +#else + u64 addr:2; + u64 reserved_2_63:62; +#endif + } cn50xx; + struct cvmx_mio_fus_wadr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 addr:3; +#else + u64 addr:3; + u64 reserved_3_63:61; +#endif + } cn52xx; + struct cvmx_mio_fus_wadr_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 addr:4; +#else + u64 addr:4; + u64 reserved_4_63:60; +#endif + } cn61xx; +}; + +union cvmx_mio_gpio_comp { + u64 u64; + struct cvmx_mio_gpio_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 pctl:6; + u64 nctl:6; +#else + u64 nctl:6; + u64 pctl:6; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_mio_ndf_dma_cfg { + u64 u64; + struct cvmx_mio_ndf_dma_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 en:1; + u64 rw:1; + u64 clr:1; + u64 reserved_60_60:1; + u64 swap32:1; + u64 swap16:1; + u64 swap8:1; + u64 endian:1; + u64 size:20; + u64 adr:36; +#else + u64 adr:36; + u64 size:20; + u64 endian:1; + u64 swap8:1; + u64 swap16:1; + u64 swap32:1; + u64 reserved_60_60:1; + u64 clr:1; + u64 rw:1; + u64 en:1; +#endif + } s; +}; + +union cvmx_mio_ndf_dma_int { + u64 u64; + struct cvmx_mio_ndf_dma_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 done:1; +#else + u64 done:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_ndf_dma_int_en { + u64 u64; + struct cvmx_mio_ndf_dma_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 done:1; +#else + u64 done:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_pll_ctl { + u64 u64; + struct cvmx_mio_pll_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 bw_ctl:5; +#else + u64 bw_ctl:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_mio_pll_setting { + u64 u64; + struct cvmx_mio_pll_setting_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 setting:17; +#else + u64 setting:17; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_mio_ptp_ckout_hi_incr { + u64 u64; + struct cvmx_mio_ptp_ckout_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 nanosec:32; +#endif + } s; +}; + +union cvmx_mio_ptp_ckout_lo_incr { + u64 u64; + struct cvmx_mio_ptp_ckout_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 nanosec:32; +#endif + } s; +}; + +union cvmx_mio_ptp_ckout_thresh_hi { + u64 u64; + struct cvmx_mio_ptp_ckout_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:64; +#else + u64 nanosec:64; +#endif + } s; +}; + +union cvmx_mio_ptp_ckout_thresh_lo { + u64 u64; + struct cvmx_mio_ptp_ckout_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_ptp_clock_cfg { + u64 u64; + struct cvmx_mio_ptp_clock_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 pps:1; + u64 ckout:1; + u64 ext_clk_edge:2; + u64 ckout_out4:1; + u64 pps_out:5; + u64 pps_inv:1; + u64 pps_en:1; + u64 ckout_out:4; + u64 ckout_inv:1; + u64 ckout_en:1; + u64 evcnt_in:6; + u64 evcnt_edge:1; + u64 evcnt_en:1; + u64 tstmp_in:6; + u64 tstmp_edge:1; + u64 tstmp_en:1; + u64 ext_clk_in:6; + u64 ext_clk_en:1; + u64 ptp_en:1; +#else + u64 ptp_en:1; + u64 ext_clk_en:1; + u64 ext_clk_in:6; + u64 tstmp_en:1; + u64 tstmp_edge:1; + u64 tstmp_in:6; + u64 evcnt_en:1; + u64 evcnt_edge:1; + u64 evcnt_in:6; + u64 ckout_en:1; + u64 ckout_inv:1; + u64 ckout_out:4; + u64 pps_en:1; + u64 pps_inv:1; + u64 pps_out:5; + u64 ckout_out4:1; + u64 ext_clk_edge:2; + u64 ckout:1; + u64 pps:1; + u64 reserved_42_63:22; +#endif + } s; + struct cvmx_mio_ptp_clock_cfg_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 evcnt_in:6; + u64 evcnt_edge:1; + u64 evcnt_en:1; + u64 tstmp_in:6; + u64 tstmp_edge:1; + u64 tstmp_en:1; + u64 ext_clk_in:6; + u64 ext_clk_en:1; + u64 ptp_en:1; +#else + u64 ptp_en:1; + u64 ext_clk_en:1; + u64 ext_clk_in:6; + u64 tstmp_en:1; + u64 tstmp_edge:1; + u64 tstmp_in:6; + u64 evcnt_en:1; + u64 evcnt_edge:1; + u64 evcnt_in:6; + u64 reserved_24_63:40; +#endif + } cn63xx; + struct cvmx_mio_ptp_clock_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 ext_clk_edge:2; + u64 ckout_out4:1; + u64 pps_out:5; + u64 pps_inv:1; + u64 pps_en:1; + u64 ckout_out:4; + u64 ckout_inv:1; + u64 ckout_en:1; + u64 evcnt_in:6; + u64 evcnt_edge:1; + u64 evcnt_en:1; + u64 tstmp_in:6; + u64 tstmp_edge:1; + u64 tstmp_en:1; + u64 ext_clk_in:6; + u64 ext_clk_en:1; + u64 ptp_en:1; +#else + u64 ptp_en:1; + u64 ext_clk_en:1; + u64 ext_clk_in:6; + u64 tstmp_en:1; + u64 tstmp_edge:1; + u64 tstmp_in:6; + u64 evcnt_en:1; + u64 evcnt_edge:1; + u64 evcnt_in:6; + u64 ckout_en:1; + u64 ckout_inv:1; + u64 ckout_out:4; + u64 pps_en:1; + u64 pps_inv:1; + u64 pps_out:5; + u64 ckout_out4:1; + u64 ext_clk_edge:2; + u64 reserved_40_63:24; +#endif + } cn66xx; +}; + +union cvmx_mio_ptp_clock_comp { + u64 u64; + struct cvmx_mio_ptp_clock_comp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 nanosec:32; +#endif + } s; +}; + +union cvmx_mio_ptp_clock_hi { + u64 u64; + struct cvmx_mio_ptp_clock_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:64; +#else + u64 nanosec:64; +#endif + } s; +}; + +union cvmx_mio_ptp_clock_lo { + u64 u64; + struct cvmx_mio_ptp_clock_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_ptp_evt_cnt { + u64 u64; + struct cvmx_mio_ptp_evt_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 cntr:64; +#else + u64 cntr:64; +#endif + } s; +}; + +union cvmx_mio_ptp_phy_1pps_in { + u64 u64; + struct cvmx_mio_ptp_phy_1pps_in_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 sel:5; +#else + u64 sel:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_mio_ptp_pps_hi_incr { + u64 u64; + struct cvmx_mio_ptp_pps_hi_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 nanosec:32; +#endif + } s; +}; + +union cvmx_mio_ptp_pps_lo_incr { + u64 u64; + struct cvmx_mio_ptp_pps_lo_incr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 nanosec:32; +#endif + } s; +}; + +union cvmx_mio_ptp_pps_thresh_hi { + u64 u64; + struct cvmx_mio_ptp_pps_thresh_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:64; +#else + u64 nanosec:64; +#endif + } s; +}; + +union cvmx_mio_ptp_pps_thresh_lo { + u64 u64; + struct cvmx_mio_ptp_pps_thresh_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 frnanosec:32; +#else + u64 frnanosec:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_ptp_timestamp { + u64 u64; + struct cvmx_mio_ptp_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 nanosec:64; +#else + u64 nanosec:64; +#endif + } s; +}; + +union cvmx_mio_qlmx_cfg { + u64 u64; + struct cvmx_mio_qlmx_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 prtmode:1; + u64 reserved_12_13:2; + u64 qlm_spd:4; + u64 reserved_4_7:4; + u64 qlm_cfg:4; +#else + u64 qlm_cfg:4; + u64 reserved_4_7:4; + u64 qlm_spd:4; + u64 reserved_12_13:2; + u64 prtmode:1; + u64 reserved_15_63:49; +#endif + } s; + struct cvmx_mio_qlmx_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 prtmode:1; + u64 reserved_12_13:2; + u64 qlm_spd:4; + u64 reserved_2_7:6; + u64 qlm_cfg:2; +#else + u64 qlm_cfg:2; + u64 reserved_2_7:6; + u64 qlm_spd:4; + u64 reserved_12_13:2; + u64 prtmode:1; + u64 reserved_15_63:49; +#endif + } cn61xx; + struct cvmx_mio_qlmx_cfg_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 qlm_spd:4; + u64 reserved_4_7:4; + u64 qlm_cfg:4; +#else + u64 qlm_cfg:4; + u64 reserved_4_7:4; + u64 qlm_spd:4; + u64 reserved_12_63:52; +#endif + } cn66xx; + struct cvmx_mio_qlmx_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 qlm_spd:4; + u64 reserved_3_7:5; + u64 qlm_cfg:3; +#else + u64 qlm_cfg:3; + u64 reserved_3_7:5; + u64 qlm_spd:4; + u64 reserved_12_63:52; +#endif + } cn68xx; +}; + +union cvmx_mio_rst_boot { + u64 u64; + struct cvmx_mio_rst_boot_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 chipkill:1; + u64 jtcsrdis:1; + u64 ejtagdis:1; + u64 romen:1; + u64 ckill_ppdis:1; + u64 jt_tstmode:1; + u64 reserved_50_57:8; + u64 lboot_ext:2; + u64 reserved_44_47:4; + u64 qlm4_spd:4; + u64 qlm3_spd:4; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 qlm3_spd:4; + u64 qlm4_spd:4; + u64 reserved_44_47:4; + u64 lboot_ext:2; + u64 reserved_50_57:8; + u64 jt_tstmode:1; + u64 ckill_ppdis:1; + u64 romen:1; + u64 ejtagdis:1; + u64 jtcsrdis:1; + u64 chipkill:1; +#endif + } s; + struct cvmx_mio_rst_boot_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 chipkill:1; + u64 jtcsrdis:1; + u64 ejtagdis:1; + u64 romen:1; + u64 ckill_ppdis:1; + u64 jt_tstmode:1; + u64 reserved_50_57:8; + u64 lboot_ext:2; + u64 reserved_36_47:12; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 reserved_36_47:12; + u64 lboot_ext:2; + u64 reserved_50_57:8; + u64 jt_tstmode:1; + u64 ckill_ppdis:1; + u64 romen:1; + u64 ejtagdis:1; + u64 jtcsrdis:1; + u64 chipkill:1; +#endif + } cn61xx; + struct cvmx_mio_rst_boot_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 reserved_36_63:28; +#endif + } cn63xx; + struct cvmx_mio_rst_boot_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 chipkill:1; + u64 jtcsrdis:1; + u64 ejtagdis:1; + u64 romen:1; + u64 ckill_ppdis:1; + u64 reserved_50_58:9; + u64 lboot_ext:2; + u64 reserved_36_47:12; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 reserved_36_47:12; + u64 lboot_ext:2; + u64 reserved_50_58:9; + u64 ckill_ppdis:1; + u64 romen:1; + u64 ejtagdis:1; + u64 jtcsrdis:1; + u64 chipkill:1; +#endif + } cn66xx; + struct cvmx_mio_rst_boot_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 jt_tstmode:1; + u64 reserved_44_57:14; + u64 qlm4_spd:4; + u64 qlm3_spd:4; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 qlm3_spd:4; + u64 qlm4_spd:4; + u64 reserved_44_57:14; + u64 jt_tstmode:1; + u64 reserved_59_63:5; +#endif + } cn68xx; + struct cvmx_mio_rst_boot_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 qlm4_spd:4; + u64 qlm3_spd:4; + u64 c_mul:6; + u64 pnr_mul:6; + u64 qlm2_spd:4; + u64 qlm1_spd:4; + u64 qlm0_spd:4; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 qlm0_spd:4; + u64 qlm1_spd:4; + u64 qlm2_spd:4; + u64 pnr_mul:6; + u64 c_mul:6; + u64 qlm3_spd:4; + u64 qlm4_spd:4; + u64 reserved_44_63:20; +#endif + } cn68xxp1; +}; + +union cvmx_mio_rst_cfg { + u64 u64; + struct cvmx_mio_rst_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 cntl_clr_bist:1; + u64 warm_clr_bist:1; + u64 soft_clr_bist:1; +#else + u64 soft_clr_bist:1; + u64 warm_clr_bist:1; + u64 cntl_clr_bist:1; + u64 reserved_3_63:61; +#endif + } s; + struct cvmx_mio_rst_cfg_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bist_delay:58; + u64 reserved_3_5:3; + u64 cntl_clr_bist:1; + u64 warm_clr_bist:1; + u64 soft_clr_bist:1; +#else + u64 soft_clr_bist:1; + u64 warm_clr_bist:1; + u64 cntl_clr_bist:1; + u64 reserved_3_5:3; + u64 bist_delay:58; +#endif + } cn61xx; + struct cvmx_mio_rst_cfg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bist_delay:58; + u64 reserved_2_5:4; + u64 warm_clr_bist:1; + u64 soft_clr_bist:1; +#else + u64 soft_clr_bist:1; + u64 warm_clr_bist:1; + u64 reserved_2_5:4; + u64 bist_delay:58; +#endif + } cn63xxp1; + struct cvmx_mio_rst_cfg_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bist_delay:56; + u64 reserved_3_7:5; + u64 cntl_clr_bist:1; + u64 warm_clr_bist:1; + u64 soft_clr_bist:1; +#else + u64 soft_clr_bist:1; + u64 warm_clr_bist:1; + u64 cntl_clr_bist:1; + u64 reserved_3_7:5; + u64 bist_delay:56; +#endif + } cn68xx; +}; + +union cvmx_mio_rst_ckill { + u64 u64; + struct cvmx_mio_rst_ckill_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 timer:47; +#else + u64 timer:47; + u64 reserved_47_63:17; +#endif + } s; +}; + +union cvmx_mio_rst_cntlx { + u64 u64; + struct cvmx_mio_rst_cntlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 in_rev_ln:1; + u64 rev_lanes:1; + u64 gen1_only:1; + u64 prst_link:1; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 prtmode:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 prtmode:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 prst_link:1; + u64 gen1_only:1; + u64 rev_lanes:1; + u64 in_rev_ln:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_mio_rst_cntlx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 prst_link:1; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 prtmode:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 prtmode:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 prst_link:1; + u64 reserved_10_63:54; +#endif + } cn66xx; +}; + +union cvmx_mio_rst_ctlx { + u64 u64; + struct cvmx_mio_rst_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 in_rev_ln:1; + u64 rev_lanes:1; + u64 gen1_only:1; + u64 prst_link:1; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 prtmode:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 prtmode:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 prst_link:1; + u64 gen1_only:1; + u64 rev_lanes:1; + u64 in_rev_ln:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_mio_rst_ctlx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 prst_link:1; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 prtmode:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 prtmode:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 prst_link:1; + u64 reserved_10_63:54; +#endif + } cn63xx; + struct cvmx_mio_rst_ctlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 prtmode:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 prtmode:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 reserved_9_63:55; +#endif + } cn63xxp1; +}; + +union cvmx_mio_rst_delay { + u64 u64; + struct cvmx_mio_rst_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 warm_rst_dly:16; + u64 soft_rst_dly:16; +#else + u64 soft_rst_dly:16; + u64 warm_rst_dly:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_mio_rst_int { + u64 u64; + struct cvmx_mio_rst_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 perst1:1; + u64 perst0:1; + u64 reserved_4_7:4; + u64 rst_link3:1; + u64 rst_link2:1; + u64 rst_link1:1; + u64 rst_link0:1; +#else + u64 rst_link0:1; + u64 rst_link1:1; + u64 rst_link2:1; + u64 rst_link3:1; + u64 reserved_4_7:4; + u64 perst0:1; + u64 perst1:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_mio_rst_int_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 perst1:1; + u64 perst0:1; + u64 reserved_2_7:6; + u64 rst_link1:1; + u64 rst_link0:1; +#else + u64 rst_link0:1; + u64 rst_link1:1; + u64 reserved_2_7:6; + u64 perst0:1; + u64 perst1:1; + u64 reserved_10_63:54; +#endif + } cn61xx; +}; + +union cvmx_mio_rst_int_en { + u64 u64; + struct cvmx_mio_rst_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 perst1:1; + u64 perst0:1; + u64 reserved_4_7:4; + u64 rst_link3:1; + u64 rst_link2:1; + u64 rst_link1:1; + u64 rst_link0:1; +#else + u64 rst_link0:1; + u64 rst_link1:1; + u64 rst_link2:1; + u64 rst_link3:1; + u64 reserved_4_7:4; + u64 perst0:1; + u64 perst1:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_mio_rst_int_en_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 perst1:1; + u64 perst0:1; + u64 reserved_2_7:6; + u64 rst_link1:1; + u64 rst_link0:1; +#else + u64 rst_link0:1; + u64 rst_link1:1; + u64 reserved_2_7:6; + u64 perst0:1; + u64 perst1:1; + u64 reserved_10_63:54; +#endif + } cn61xx; +}; + +union cvmx_mio_twsx_int { + u64 u64; + struct cvmx_mio_twsx_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 scl:1; + u64 sda:1; + u64 scl_ovr:1; + u64 sda_ovr:1; + u64 reserved_7_7:1; + u64 core_en:1; + u64 ts_en:1; + u64 st_en:1; + u64 reserved_3_3:1; + u64 core_int:1; + u64 ts_int:1; + u64 st_int:1; +#else + u64 st_int:1; + u64 ts_int:1; + u64 core_int:1; + u64 reserved_3_3:1; + u64 st_en:1; + u64 ts_en:1; + u64 core_en:1; + u64 reserved_7_7:1; + u64 sda_ovr:1; + u64 scl_ovr:1; + u64 sda:1; + u64 scl:1; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_mio_twsx_int_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 core_en:1; + u64 ts_en:1; + u64 st_en:1; + u64 reserved_3_3:1; + u64 core_int:1; + u64 ts_int:1; + u64 st_int:1; +#else + u64 st_int:1; + u64 ts_int:1; + u64 core_int:1; + u64 reserved_3_3:1; + u64 st_en:1; + u64 ts_en:1; + u64 core_en:1; + u64 reserved_7_63:57; +#endif + } cn38xxp2; +}; + +union cvmx_mio_twsx_sw_twsi { + u64 u64; + struct cvmx_mio_twsx_sw_twsi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 v:1; + u64 slonly:1; + u64 eia:1; + u64 op:4; + u64 r:1; + u64 sovr:1; + u64 size:3; + u64 scr:2; + u64 a:10; + u64 ia:5; + u64 eop_ia:3; + u64 d:32; +#else + u64 d:32; + u64 eop_ia:3; + u64 ia:5; + u64 a:10; + u64 scr:2; + u64 size:3; + u64 sovr:1; + u64 r:1; + u64 op:4; + u64 eia:1; + u64 slonly:1; + u64 v:1; +#endif + } s; +}; + +union cvmx_mio_twsx_sw_twsi_ext { + u64 u64; + struct cvmx_mio_twsx_sw_twsi_ext_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 ia:8; + u64 d:32; +#else + u64 d:32; + u64 ia:8; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_mio_twsx_twsi_sw { + u64 u64; + struct cvmx_mio_twsx_twsi_sw_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 v:2; + u64 reserved_32_61:30; + u64 d:32; +#else + u64 d:32; + u64 reserved_32_61:30; + u64 v:2; +#endif + } s; +}; + +union cvmx_mio_uartx_dlh { + u64 u64; + struct cvmx_mio_uartx_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dlh:8; +#else + u64 dlh:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_dll { + u64 u64; + struct cvmx_mio_uartx_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dll:8; +#else + u64 dll:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_far { + u64 u64; + struct cvmx_mio_uartx_far_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 far:1; +#else + u64 far:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uartx_fcr { + u64 u64; + struct cvmx_mio_uartx_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rxtrig:2; + u64 txtrig:2; + u64 reserved_3_3:1; + u64 txfr:1; + u64 rxfr:1; + u64 en:1; +#else + u64 en:1; + u64 rxfr:1; + u64 txfr:1; + u64 reserved_3_3:1; + u64 txtrig:2; + u64 rxtrig:2; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_htx { + u64 u64; + struct cvmx_mio_uartx_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 htx:1; +#else + u64 htx:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uartx_ier { + u64 u64; + struct cvmx_mio_uartx_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ptime:1; + u64 reserved_4_6:3; + u64 edssi:1; + u64 elsi:1; + u64 etbei:1; + u64 erbfi:1; +#else + u64 erbfi:1; + u64 etbei:1; + u64 elsi:1; + u64 edssi:1; + u64 reserved_4_6:3; + u64 ptime:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_iir { + u64 u64; + struct cvmx_mio_uartx_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 fen:2; + u64 reserved_4_5:2; + u64 iid:4; +#else + u64 iid:4; + u64 reserved_4_5:2; + u64 fen:2; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_lcr { + u64 u64; + struct cvmx_mio_uartx_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dlab:1; + u64 brk:1; + u64 reserved_5_5:1; + u64 eps:1; + u64 pen:1; + u64 stop:1; + u64 cls:2; +#else + u64 cls:2; + u64 stop:1; + u64 pen:1; + u64 eps:1; + u64 reserved_5_5:1; + u64 brk:1; + u64 dlab:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_lsr { + u64 u64; + struct cvmx_mio_uartx_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ferr:1; + u64 temt:1; + u64 thre:1; + u64 bi:1; + u64 fe:1; + u64 pe:1; + u64 oe:1; + u64 dr:1; +#else + u64 dr:1; + u64 oe:1; + u64 pe:1; + u64 fe:1; + u64 bi:1; + u64 thre:1; + u64 temt:1; + u64 ferr:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_mcr { + u64 u64; + struct cvmx_mio_uartx_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 afce:1; + u64 loop:1; + u64 out2:1; + u64 out1:1; + u64 rts:1; + u64 dtr:1; +#else + u64 dtr:1; + u64 rts:1; + u64 out1:1; + u64 out2:1; + u64 loop:1; + u64 afce:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_mio_uartx_msr { + u64 u64; + struct cvmx_mio_uartx_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dcd:1; + u64 ri:1; + u64 dsr:1; + u64 cts:1; + u64 ddcd:1; + u64 teri:1; + u64 ddsr:1; + u64 dcts:1; +#else + u64 dcts:1; + u64 ddsr:1; + u64 teri:1; + u64 ddcd:1; + u64 cts:1; + u64 dsr:1; + u64 ri:1; + u64 dcd:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_rbr { + u64 u64; + struct cvmx_mio_uartx_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rbr:8; +#else + u64 rbr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_rfl { + u64 u64; + struct cvmx_mio_uartx_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 rfl:7; +#else + u64 rfl:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_uartx_rfw { + u64 u64; + struct cvmx_mio_uartx_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 rffe:1; + u64 rfpe:1; + u64 rfwd:8; +#else + u64 rfwd:8; + u64 rfpe:1; + u64 rffe:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_mio_uartx_sbcr { + u64 u64; + struct cvmx_mio_uartx_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 sbcr:1; +#else + u64 sbcr:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uartx_scr { + u64 u64; + struct cvmx_mio_uartx_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 scr:8; +#else + u64 scr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_sfe { + u64 u64; + struct cvmx_mio_uartx_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 sfe:1; +#else + u64 sfe:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uartx_srr { + u64 u64; + struct cvmx_mio_uartx_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 stfr:1; + u64 srfr:1; + u64 usr:1; +#else + u64 usr:1; + u64 srfr:1; + u64 stfr:1; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_mio_uartx_srt { + u64 u64; + struct cvmx_mio_uartx_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 srt:2; +#else + u64 srt:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_uartx_srts { + u64 u64; + struct cvmx_mio_uartx_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 srts:1; +#else + u64 srts:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uartx_stt { + u64 u64; + struct cvmx_mio_uartx_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 stt:2; +#else + u64 stt:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_uartx_tfl { + u64 u64; + struct cvmx_mio_uartx_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 tfl:7; +#else + u64 tfl:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_uartx_tfr { + u64 u64; + struct cvmx_mio_uartx_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 tfr:8; +#else + u64 tfr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_thr { + u64 u64; + struct cvmx_mio_uartx_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 thr:8; +#else + u64 thr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uartx_usr { + u64 u64; + struct cvmx_mio_uartx_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 rff:1; + u64 rfne:1; + u64 tfe:1; + u64 tfnf:1; + u64 busy:1; +#else + u64 busy:1; + u64 tfnf:1; + u64 tfe:1; + u64 rfne:1; + u64 rff:1; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_mio_uart2_dlh { + u64 u64; + struct cvmx_mio_uart2_dlh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dlh:8; +#else + u64 dlh:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_dll { + u64 u64; + struct cvmx_mio_uart2_dll_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dll:8; +#else + u64 dll:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_far { + u64 u64; + struct cvmx_mio_uart2_far_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 far:1; +#else + u64 far:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uart2_fcr { + u64 u64; + struct cvmx_mio_uart2_fcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rxtrig:2; + u64 txtrig:2; + u64 reserved_3_3:1; + u64 txfr:1; + u64 rxfr:1; + u64 en:1; +#else + u64 en:1; + u64 rxfr:1; + u64 txfr:1; + u64 reserved_3_3:1; + u64 txtrig:2; + u64 rxtrig:2; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_htx { + u64 u64; + struct cvmx_mio_uart2_htx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 htx:1; +#else + u64 htx:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uart2_ier { + u64 u64; + struct cvmx_mio_uart2_ier_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ptime:1; + u64 reserved_4_6:3; + u64 edssi:1; + u64 elsi:1; + u64 etbei:1; + u64 erbfi:1; +#else + u64 erbfi:1; + u64 etbei:1; + u64 elsi:1; + u64 edssi:1; + u64 reserved_4_6:3; + u64 ptime:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_iir { + u64 u64; + struct cvmx_mio_uart2_iir_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 fen:2; + u64 reserved_4_5:2; + u64 iid:4; +#else + u64 iid:4; + u64 reserved_4_5:2; + u64 fen:2; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_lcr { + u64 u64; + struct cvmx_mio_uart2_lcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dlab:1; + u64 brk:1; + u64 reserved_5_5:1; + u64 eps:1; + u64 pen:1; + u64 stop:1; + u64 cls:2; +#else + u64 cls:2; + u64 stop:1; + u64 pen:1; + u64 eps:1; + u64 reserved_5_5:1; + u64 brk:1; + u64 dlab:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_lsr { + u64 u64; + struct cvmx_mio_uart2_lsr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ferr:1; + u64 temt:1; + u64 thre:1; + u64 bi:1; + u64 fe:1; + u64 pe:1; + u64 oe:1; + u64 dr:1; +#else + u64 dr:1; + u64 oe:1; + u64 pe:1; + u64 fe:1; + u64 bi:1; + u64 thre:1; + u64 temt:1; + u64 ferr:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_mcr { + u64 u64; + struct cvmx_mio_uart2_mcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 afce:1; + u64 loop:1; + u64 out2:1; + u64 out1:1; + u64 rts:1; + u64 dtr:1; +#else + u64 dtr:1; + u64 rts:1; + u64 out1:1; + u64 out2:1; + u64 loop:1; + u64 afce:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_mio_uart2_msr { + u64 u64; + struct cvmx_mio_uart2_msr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 dcd:1; + u64 ri:1; + u64 dsr:1; + u64 cts:1; + u64 ddcd:1; + u64 teri:1; + u64 ddsr:1; + u64 dcts:1; +#else + u64 dcts:1; + u64 ddsr:1; + u64 teri:1; + u64 ddcd:1; + u64 cts:1; + u64 dsr:1; + u64 ri:1; + u64 dcd:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_rbr { + u64 u64; + struct cvmx_mio_uart2_rbr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rbr:8; +#else + u64 rbr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_rfl { + u64 u64; + struct cvmx_mio_uart2_rfl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 rfl:7; +#else + u64 rfl:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_uart2_rfw { + u64 u64; + struct cvmx_mio_uart2_rfw_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 rffe:1; + u64 rfpe:1; + u64 rfwd:8; +#else + u64 rfwd:8; + u64 rfpe:1; + u64 rffe:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_mio_uart2_sbcr { + u64 u64; + struct cvmx_mio_uart2_sbcr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 sbcr:1; +#else + u64 sbcr:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uart2_scr { + u64 u64; + struct cvmx_mio_uart2_scr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 scr:8; +#else + u64 scr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_sfe { + u64 u64; + struct cvmx_mio_uart2_sfe_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 sfe:1; +#else + u64 sfe:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uart2_srr { + u64 u64; + struct cvmx_mio_uart2_srr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 stfr:1; + u64 srfr:1; + u64 usr:1; +#else + u64 usr:1; + u64 srfr:1; + u64 stfr:1; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_mio_uart2_srt { + u64 u64; + struct cvmx_mio_uart2_srt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 srt:2; +#else + u64 srt:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_uart2_srts { + u64 u64; + struct cvmx_mio_uart2_srts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 srts:1; +#else + u64 srts:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_mio_uart2_stt { + u64 u64; + struct cvmx_mio_uart2_stt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 stt:2; +#else + u64 stt:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_mio_uart2_tfl { + u64 u64; + struct cvmx_mio_uart2_tfl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 tfl:7; +#else + u64 tfl:7; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_mio_uart2_tfr { + u64 u64; + struct cvmx_mio_uart2_tfr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 tfr:8; +#else + u64 tfr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_thr { + u64 u64; + struct cvmx_mio_uart2_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 thr:8; +#else + u64 thr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_mio_uart2_usr { + u64 u64; + struct cvmx_mio_uart2_usr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 rff:1; + u64 rfne:1; + u64 tfe:1; + u64 tfnf:1; + u64 busy:1; +#else + u64 busy:1; + u64 tfnf:1; + u64 tfe:1; + u64 rfne:1; + u64 rff:1; + u64 reserved_5_63:59; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-mixx-defs.h b/drivers/staging/octeon/cvmx-mixx-defs.h new file mode 100644 index 000000000000..c8d0a7630cdf --- /dev/null +++ b/drivers/staging/octeon/cvmx-mixx-defs.h @@ -0,0 +1,429 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_MIXX_DEFS_H__ +#define __CVMX_MIXX_DEFS_H__ + +#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048) +#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048) + +union cvmx_mixx_bist { + u64 u64; + struct cvmx_mixx_bist_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 opfdat:1; + u64 mrgdat:1; + u64 mrqdat:1; + u64 ipfdat:1; + u64 irfdat:1; + u64 orfdat:1; +#else + u64 orfdat:1; + u64 irfdat:1; + u64 ipfdat:1; + u64 mrqdat:1; + u64 mrgdat:1; + u64 opfdat:1; + u64 reserved_6_63:58; +#endif + } s; + struct cvmx_mixx_bist_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 mrqdat:1; + u64 ipfdat:1; + u64 irfdat:1; + u64 orfdat:1; +#else + u64 orfdat:1; + u64 irfdat:1; + u64 ipfdat:1; + u64 mrqdat:1; + u64 reserved_4_63:60; +#endif + } cn52xx; +}; + +union cvmx_mixx_ctl { + u64 u64; + struct cvmx_mixx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 ts_thresh:4; + u64 crc_strip:1; + u64 busy:1; + u64 en:1; + u64 reset:1; + u64 lendian:1; + u64 nbtarb:1; + u64 mrq_hwm:2; +#else + u64 mrq_hwm:2; + u64 nbtarb:1; + u64 lendian:1; + u64 reset:1; + u64 en:1; + u64 busy:1; + u64 crc_strip:1; + u64 ts_thresh:4; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_mixx_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 crc_strip:1; + u64 busy:1; + u64 en:1; + u64 reset:1; + u64 lendian:1; + u64 nbtarb:1; + u64 mrq_hwm:2; +#else + u64 mrq_hwm:2; + u64 nbtarb:1; + u64 lendian:1; + u64 reset:1; + u64 en:1; + u64 busy:1; + u64 crc_strip:1; + u64 reserved_8_63:56; +#endif + } cn52xx; +}; + +union cvmx_mixx_intena { + u64 u64; + struct cvmx_mixx_intena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 tsena:1; + u64 orunena:1; + u64 irunena:1; + u64 data_drpena:1; + u64 ithena:1; + u64 othena:1; + u64 ivfena:1; + u64 ovfena:1; +#else + u64 ovfena:1; + u64 ivfena:1; + u64 othena:1; + u64 ithena:1; + u64 data_drpena:1; + u64 irunena:1; + u64 orunena:1; + u64 tsena:1; + u64 reserved_8_63:56; +#endif + } s; + struct cvmx_mixx_intena_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 orunena:1; + u64 irunena:1; + u64 data_drpena:1; + u64 ithena:1; + u64 othena:1; + u64 ivfena:1; + u64 ovfena:1; +#else + u64 ovfena:1; + u64 ivfena:1; + u64 othena:1; + u64 ithena:1; + u64 data_drpena:1; + u64 irunena:1; + u64 orunena:1; + u64 reserved_7_63:57; +#endif + } cn52xx; +}; + +union cvmx_mixx_ircnt { + u64 u64; + struct cvmx_mixx_ircnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 ircnt:20; +#else + u64 ircnt:20; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_mixx_irhwm { + u64 u64; + struct cvmx_mixx_irhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 ibplwm:20; + u64 irhwm:20; +#else + u64 irhwm:20; + u64 ibplwm:20; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_mixx_iring1 { + u64 u64; + struct cvmx_mixx_iring1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 isize:20; + u64 ibase:37; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 ibase:37; + u64 isize:20; + u64 reserved_60_63:4; +#endif + } s; + struct cvmx_mixx_iring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 isize:20; + u64 reserved_36_39:4; + u64 ibase:33; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 ibase:33; + u64 reserved_36_39:4; + u64 isize:20; + u64 reserved_60_63:4; +#endif + } cn52xx; +}; + +union cvmx_mixx_iring2 { + u64 u64; + struct cvmx_mixx_iring2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + u64 itlptr:20; + u64 reserved_20_31:12; + u64 idbell:20; +#else + u64 idbell:20; + u64 reserved_20_31:12; + u64 itlptr:20; + u64 reserved_52_63:12; +#endif + } s; +}; + +union cvmx_mixx_isr { + u64 u64; + struct cvmx_mixx_isr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ts:1; + u64 orun:1; + u64 irun:1; + u64 data_drp:1; + u64 irthresh:1; + u64 orthresh:1; + u64 idblovf:1; + u64 odblovf:1; +#else + u64 odblovf:1; + u64 idblovf:1; + u64 orthresh:1; + u64 irthresh:1; + u64 data_drp:1; + u64 irun:1; + u64 orun:1; + u64 ts:1; + u64 reserved_8_63:56; +#endif + } s; + struct cvmx_mixx_isr_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 orun:1; + u64 irun:1; + u64 data_drp:1; + u64 irthresh:1; + u64 orthresh:1; + u64 idblovf:1; + u64 odblovf:1; +#else + u64 odblovf:1; + u64 idblovf:1; + u64 orthresh:1; + u64 irthresh:1; + u64 data_drp:1; + u64 irun:1; + u64 orun:1; + u64 reserved_7_63:57; +#endif + } cn52xx; +}; + +union cvmx_mixx_orcnt { + u64 u64; + struct cvmx_mixx_orcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 orcnt:20; +#else + u64 orcnt:20; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_mixx_orhwm { + u64 u64; + struct cvmx_mixx_orhwm_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 orhwm:20; +#else + u64 orhwm:20; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_mixx_oring1 { + u64 u64; + struct cvmx_mixx_oring1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 osize:20; + u64 obase:37; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 obase:37; + u64 osize:20; + u64 reserved_60_63:4; +#endif + } s; + struct cvmx_mixx_oring1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 osize:20; + u64 reserved_36_39:4; + u64 obase:33; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 obase:33; + u64 reserved_36_39:4; + u64 osize:20; + u64 reserved_60_63:4; +#endif + } cn52xx; +}; + +union cvmx_mixx_oring2 { + u64 u64; + struct cvmx_mixx_oring2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + u64 otlptr:20; + u64 reserved_20_31:12; + u64 odbell:20; +#else + u64 odbell:20; + u64 reserved_20_31:12; + u64 otlptr:20; + u64 reserved_52_63:12; +#endif + } s; +}; + +union cvmx_mixx_remcnt { + u64 u64; + struct cvmx_mixx_remcnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + u64 iremcnt:20; + u64 reserved_20_31:12; + u64 oremcnt:20; +#else + u64 oremcnt:20; + u64 reserved_20_31:12; + u64 iremcnt:20; + u64 reserved_52_63:12; +#endif + } s; +}; + +union cvmx_mixx_tsctl { + u64 u64; + struct cvmx_mixx_tsctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 tsavl:5; + u64 reserved_13_15:3; + u64 tstot:5; + u64 reserved_5_7:3; + u64 tscnt:5; +#else + u64 tscnt:5; + u64 reserved_5_7:3; + u64 tstot:5; + u64 reserved_13_15:3; + u64 tsavl:5; + u64 reserved_21_63:43; +#endif + } s; +}; + +union cvmx_mixx_tstamp { + u64 u64; + struct cvmx_mixx_tstamp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 tstamp:64; +#else + u64 tstamp:64; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-npei-defs.h b/drivers/staging/octeon/cvmx-npei-defs.h new file mode 100644 index 000000000000..22e6d334ca3f --- /dev/null +++ b/drivers/staging/octeon/cvmx-npei-defs.h @@ -0,0 +1,3924 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_NPEI_DEFS_H__ +#define __CVMX_NPEI_DEFS_H__ + +#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16) +#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull) +#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull) +#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull) +#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull) +#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull) +#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull) +#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull) +#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull) +#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull) +#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull) +#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull) +#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull) +#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull) +#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull) +#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull) +#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull) +#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull) +#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull) +#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull) +#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull) +#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull) +#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull) +#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull) +#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull) +#define CVMX_NPEI_INT_ENB (0x0000000000000540ull) +#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull) +#define CVMX_NPEI_INT_INFO (0x0000000000000590ull) +#define CVMX_NPEI_INT_SUM (0x0000000000000530ull) +#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull) +#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) +#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) +#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) +#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16 * 12) +#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) +#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) +#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) +#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull) +#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull) +#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull) +#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull) +#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull) +#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull) +#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull) +#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull) +#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull) +#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull) +#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull) +#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull) +#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull) +#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull) +#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull) +#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull) +#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) +#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull) +#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull) +#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull) +#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull) +#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull) +#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull) +#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull) +#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull) +#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull) +#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull) +#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull) +#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull) +#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) +#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull) +#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull) +#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull) +#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull) +#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull) +#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull) +#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull) +#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull) +#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull) +#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull) +#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull) +#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull) +#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull) +#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull) +#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull) +#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull) +#define CVMX_NPEI_STATE1 (0x0000000000000620ull) +#define CVMX_NPEI_STATE2 (0x0000000000000630ull) +#define CVMX_NPEI_STATE3 (0x0000000000000640ull) +#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull) +#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull) +#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull) +#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull) +#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull) +#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull) + +union cvmx_npei_bar1_indexx { + u32 u32; + struct cvmx_npei_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_18_31:14; + u32 addr_idx:14; + u32 ca:1; + u32 end_swp:2; + u32 addr_v:1; +#else + u32 addr_v:1; + u32 end_swp:2; + u32 ca:1; + u32 addr_idx:14; + u32 reserved_18_31:14; +#endif + } s; +}; + +union cvmx_npei_bist_status { + u64 u64; + struct cvmx_npei_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pkt_rdf:1; + u64 reserved_60_62:3; + u64 pcr_gim:1; + u64 pkt_pif:1; + u64 pcsr_int:1; + u64 pcsr_im:1; + u64 pcsr_cnt:1; + u64 pcsr_id:1; + u64 pcsr_sl:1; + u64 reserved_50_52:3; + u64 pkt_ind:1; + u64 pkt_slm:1; + u64 reserved_36_47:12; + u64 d0_pst:1; + u64 d1_pst:1; + u64 d2_pst:1; + u64 d3_pst:1; + u64 reserved_31_31:1; + u64 n2p0_c:1; + u64 n2p0_o:1; + u64 n2p1_c:1; + u64 n2p1_o:1; + u64 cpl_p0:1; + u64 cpl_p1:1; + u64 p2n1_po:1; + u64 p2n1_no:1; + u64 p2n1_co:1; + u64 p2n0_po:1; + u64 p2n0_no:1; + u64 p2n0_co:1; + u64 p2n0_c0:1; + u64 p2n0_c1:1; + u64 p2n0_n:1; + u64 p2n0_p0:1; + u64 p2n0_p1:1; + u64 p2n1_c0:1; + u64 p2n1_c1:1; + u64 p2n1_n:1; + u64 p2n1_p0:1; + u64 p2n1_p1:1; + u64 csm0:1; + u64 csm1:1; + u64 dif0:1; + u64 dif1:1; + u64 dif2:1; + u64 dif3:1; + u64 reserved_2_2:1; + u64 msi:1; + u64 ncb_cmd:1; +#else + u64 ncb_cmd:1; + u64 msi:1; + u64 reserved_2_2:1; + u64 dif3:1; + u64 dif2:1; + u64 dif1:1; + u64 dif0:1; + u64 csm1:1; + u64 csm0:1; + u64 p2n1_p1:1; + u64 p2n1_p0:1; + u64 p2n1_n:1; + u64 p2n1_c1:1; + u64 p2n1_c0:1; + u64 p2n0_p1:1; + u64 p2n0_p0:1; + u64 p2n0_n:1; + u64 p2n0_c1:1; + u64 p2n0_c0:1; + u64 p2n0_co:1; + u64 p2n0_no:1; + u64 p2n0_po:1; + u64 p2n1_co:1; + u64 p2n1_no:1; + u64 p2n1_po:1; + u64 cpl_p1:1; + u64 cpl_p0:1; + u64 n2p1_o:1; + u64 n2p1_c:1; + u64 n2p0_o:1; + u64 n2p0_c:1; + u64 reserved_31_31:1; + u64 d3_pst:1; + u64 d2_pst:1; + u64 d1_pst:1; + u64 d0_pst:1; + u64 reserved_36_47:12; + u64 pkt_slm:1; + u64 pkt_ind:1; + u64 reserved_50_52:3; + u64 pcsr_sl:1; + u64 pcsr_id:1; + u64 pcsr_cnt:1; + u64 pcsr_im:1; + u64 pcsr_int:1; + u64 pkt_pif:1; + u64 pcr_gim:1; + u64 reserved_60_62:3; + u64 pkt_rdf:1; +#endif + } s; + struct cvmx_npei_bist_status_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pkt_rdf:1; + u64 reserved_60_62:3; + u64 pcr_gim:1; + u64 pkt_pif:1; + u64 pcsr_int:1; + u64 pcsr_im:1; + u64 pcsr_cnt:1; + u64 pcsr_id:1; + u64 pcsr_sl:1; + u64 pkt_imem:1; + u64 pkt_pfm:1; + u64 pkt_pof:1; + u64 reserved_48_49:2; + u64 pkt_pop0:1; + u64 pkt_pop1:1; + u64 d0_mem:1; + u64 d1_mem:1; + u64 d2_mem:1; + u64 d3_mem:1; + u64 d4_mem:1; + u64 ds_mem:1; + u64 reserved_36_39:4; + u64 d0_pst:1; + u64 d1_pst:1; + u64 d2_pst:1; + u64 d3_pst:1; + u64 d4_pst:1; + u64 n2p0_c:1; + u64 n2p0_o:1; + u64 n2p1_c:1; + u64 n2p1_o:1; + u64 cpl_p0:1; + u64 cpl_p1:1; + u64 p2n1_po:1; + u64 p2n1_no:1; + u64 p2n1_co:1; + u64 p2n0_po:1; + u64 p2n0_no:1; + u64 p2n0_co:1; + u64 p2n0_c0:1; + u64 p2n0_c1:1; + u64 p2n0_n:1; + u64 p2n0_p0:1; + u64 p2n0_p1:1; + u64 p2n1_c0:1; + u64 p2n1_c1:1; + u64 p2n1_n:1; + u64 p2n1_p0:1; + u64 p2n1_p1:1; + u64 csm0:1; + u64 csm1:1; + u64 dif0:1; + u64 dif1:1; + u64 dif2:1; + u64 dif3:1; + u64 dif4:1; + u64 msi:1; + u64 ncb_cmd:1; +#else + u64 ncb_cmd:1; + u64 msi:1; + u64 dif4:1; + u64 dif3:1; + u64 dif2:1; + u64 dif1:1; + u64 dif0:1; + u64 csm1:1; + u64 csm0:1; + u64 p2n1_p1:1; + u64 p2n1_p0:1; + u64 p2n1_n:1; + u64 p2n1_c1:1; + u64 p2n1_c0:1; + u64 p2n0_p1:1; + u64 p2n0_p0:1; + u64 p2n0_n:1; + u64 p2n0_c1:1; + u64 p2n0_c0:1; + u64 p2n0_co:1; + u64 p2n0_no:1; + u64 p2n0_po:1; + u64 p2n1_co:1; + u64 p2n1_no:1; + u64 p2n1_po:1; + u64 cpl_p1:1; + u64 cpl_p0:1; + u64 n2p1_o:1; + u64 n2p1_c:1; + u64 n2p0_o:1; + u64 n2p0_c:1; + u64 d4_pst:1; + u64 d3_pst:1; + u64 d2_pst:1; + u64 d1_pst:1; + u64 d0_pst:1; + u64 reserved_36_39:4; + u64 ds_mem:1; + u64 d4_mem:1; + u64 d3_mem:1; + u64 d2_mem:1; + u64 d1_mem:1; + u64 d0_mem:1; + u64 pkt_pop1:1; + u64 pkt_pop0:1; + u64 reserved_48_49:2; + u64 pkt_pof:1; + u64 pkt_pfm:1; + u64 pkt_imem:1; + u64 pcsr_sl:1; + u64 pcsr_id:1; + u64 pcsr_cnt:1; + u64 pcsr_im:1; + u64 pcsr_int:1; + u64 pkt_pif:1; + u64 pcr_gim:1; + u64 reserved_60_62:3; + u64 pkt_rdf:1; +#endif + } cn52xx; + struct cvmx_npei_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 d0_mem0:1; + u64 d1_mem1:1; + u64 d2_mem2:1; + u64 d3_mem3:1; + u64 dr0_mem:1; + u64 d0_mem:1; + u64 d1_mem:1; + u64 d2_mem:1; + u64 d3_mem:1; + u64 dr1_mem:1; + u64 d0_pst:1; + u64 d1_pst:1; + u64 d2_pst:1; + u64 d3_pst:1; + u64 dr2_mem:1; + u64 n2p0_c:1; + u64 n2p0_o:1; + u64 n2p1_c:1; + u64 n2p1_o:1; + u64 cpl_p0:1; + u64 cpl_p1:1; + u64 p2n1_po:1; + u64 p2n1_no:1; + u64 p2n1_co:1; + u64 p2n0_po:1; + u64 p2n0_no:1; + u64 p2n0_co:1; + u64 p2n0_c0:1; + u64 p2n0_c1:1; + u64 p2n0_n:1; + u64 p2n0_p0:1; + u64 p2n0_p1:1; + u64 p2n1_c0:1; + u64 p2n1_c1:1; + u64 p2n1_n:1; + u64 p2n1_p0:1; + u64 p2n1_p1:1; + u64 csm0:1; + u64 csm1:1; + u64 dif0:1; + u64 dif1:1; + u64 dif2:1; + u64 dif3:1; + u64 dr3_mem:1; + u64 msi:1; + u64 ncb_cmd:1; +#else + u64 ncb_cmd:1; + u64 msi:1; + u64 dr3_mem:1; + u64 dif3:1; + u64 dif2:1; + u64 dif1:1; + u64 dif0:1; + u64 csm1:1; + u64 csm0:1; + u64 p2n1_p1:1; + u64 p2n1_p0:1; + u64 p2n1_n:1; + u64 p2n1_c1:1; + u64 p2n1_c0:1; + u64 p2n0_p1:1; + u64 p2n0_p0:1; + u64 p2n0_n:1; + u64 p2n0_c1:1; + u64 p2n0_c0:1; + u64 p2n0_co:1; + u64 p2n0_no:1; + u64 p2n0_po:1; + u64 p2n1_co:1; + u64 p2n1_no:1; + u64 p2n1_po:1; + u64 cpl_p1:1; + u64 cpl_p0:1; + u64 n2p1_o:1; + u64 n2p1_c:1; + u64 n2p0_o:1; + u64 n2p0_c:1; + u64 dr2_mem:1; + u64 d3_pst:1; + u64 d2_pst:1; + u64 d1_pst:1; + u64 d0_pst:1; + u64 dr1_mem:1; + u64 d3_mem:1; + u64 d2_mem:1; + u64 d1_mem:1; + u64 d0_mem:1; + u64 dr0_mem:1; + u64 d3_mem3:1; + u64 d2_mem2:1; + u64 d1_mem1:1; + u64 d0_mem0:1; + u64 reserved_46_63:18; +#endif + } cn52xxp1; + struct cvmx_npei_bist_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_58_63:6; + u64 pcsr_int:1; + u64 pcsr_im:1; + u64 pcsr_cnt:1; + u64 pcsr_id:1; + u64 pcsr_sl:1; + u64 pkt_pout:1; + u64 pkt_imem:1; + u64 pkt_cntm:1; + u64 pkt_ind:1; + u64 pkt_slm:1; + u64 pkt_odf:1; + u64 pkt_oif:1; + u64 pkt_out:1; + u64 pkt_i0:1; + u64 pkt_i1:1; + u64 pkt_s0:1; + u64 pkt_s1:1; + u64 d0_mem:1; + u64 d1_mem:1; + u64 d2_mem:1; + u64 d3_mem:1; + u64 d4_mem:1; + u64 d0_pst:1; + u64 d1_pst:1; + u64 d2_pst:1; + u64 d3_pst:1; + u64 d4_pst:1; + u64 n2p0_c:1; + u64 n2p0_o:1; + u64 n2p1_c:1; + u64 n2p1_o:1; + u64 cpl_p0:1; + u64 cpl_p1:1; + u64 p2n1_po:1; + u64 p2n1_no:1; + u64 p2n1_co:1; + u64 p2n0_po:1; + u64 p2n0_no:1; + u64 p2n0_co:1; + u64 p2n0_c0:1; + u64 p2n0_c1:1; + u64 p2n0_n:1; + u64 p2n0_p0:1; + u64 p2n0_p1:1; + u64 p2n1_c0:1; + u64 p2n1_c1:1; + u64 p2n1_n:1; + u64 p2n1_p0:1; + u64 p2n1_p1:1; + u64 csm0:1; + u64 csm1:1; + u64 dif0:1; + u64 dif1:1; + u64 dif2:1; + u64 dif3:1; + u64 dif4:1; + u64 msi:1; + u64 ncb_cmd:1; +#else + u64 ncb_cmd:1; + u64 msi:1; + u64 dif4:1; + u64 dif3:1; + u64 dif2:1; + u64 dif1:1; + u64 dif0:1; + u64 csm1:1; + u64 csm0:1; + u64 p2n1_p1:1; + u64 p2n1_p0:1; + u64 p2n1_n:1; + u64 p2n1_c1:1; + u64 p2n1_c0:1; + u64 p2n0_p1:1; + u64 p2n0_p0:1; + u64 p2n0_n:1; + u64 p2n0_c1:1; + u64 p2n0_c0:1; + u64 p2n0_co:1; + u64 p2n0_no:1; + u64 p2n0_po:1; + u64 p2n1_co:1; + u64 p2n1_no:1; + u64 p2n1_po:1; + u64 cpl_p1:1; + u64 cpl_p0:1; + u64 n2p1_o:1; + u64 n2p1_c:1; + u64 n2p0_o:1; + u64 n2p0_c:1; + u64 d4_pst:1; + u64 d3_pst:1; + u64 d2_pst:1; + u64 d1_pst:1; + u64 d0_pst:1; + u64 d4_mem:1; + u64 d3_mem:1; + u64 d2_mem:1; + u64 d1_mem:1; + u64 d0_mem:1; + u64 pkt_s1:1; + u64 pkt_s0:1; + u64 pkt_i1:1; + u64 pkt_i0:1; + u64 pkt_out:1; + u64 pkt_oif:1; + u64 pkt_odf:1; + u64 pkt_slm:1; + u64 pkt_ind:1; + u64 pkt_cntm:1; + u64 pkt_imem:1; + u64 pkt_pout:1; + u64 pcsr_sl:1; + u64 pcsr_id:1; + u64 pcsr_cnt:1; + u64 pcsr_im:1; + u64 pcsr_int:1; + u64 reserved_58_63:6; +#endif + } cn56xxp1; +}; + +union cvmx_npei_bist_status2 { + u64 u64; + struct cvmx_npei_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 prd_tag:1; + u64 prd_st0:1; + u64 prd_st1:1; + u64 prd_err:1; + u64 nrd_st:1; + u64 nwe_st:1; + u64 nwe_wr0:1; + u64 nwe_wr1:1; + u64 pkt_rd:1; + u64 psc_p0:1; + u64 psc_p1:1; + u64 pkt_gd:1; + u64 pkt_gl:1; + u64 pkt_blk:1; +#else + u64 pkt_blk:1; + u64 pkt_gl:1; + u64 pkt_gd:1; + u64 psc_p1:1; + u64 psc_p0:1; + u64 pkt_rd:1; + u64 nwe_wr1:1; + u64 nwe_wr0:1; + u64 nwe_st:1; + u64 nrd_st:1; + u64 prd_err:1; + u64 prd_st1:1; + u64 prd_st0:1; + u64 prd_tag:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_npei_ctl_port0 { + u64 u64; + struct cvmx_npei_ctl_port0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 waitl_com:1; + u64 intd:1; + u64 intc:1; + u64 intb:1; + u64 inta:1; + u64 intd_map:2; + u64 intc_map:2; + u64 intb_map:2; + u64 inta_map:2; + u64 ctlp_ro:1; + u64 reserved_6_6:1; + u64 ptlp_ro:1; + u64 bar2_enb:1; + u64 bar2_esx:2; + u64 bar2_cax:1; + u64 wait_com:1; +#else + u64 wait_com:1; + u64 bar2_cax:1; + u64 bar2_esx:2; + u64 bar2_enb:1; + u64 ptlp_ro:1; + u64 reserved_6_6:1; + u64 ctlp_ro:1; + u64 inta_map:2; + u64 intb_map:2; + u64 intc_map:2; + u64 intd_map:2; + u64 inta:1; + u64 intb:1; + u64 intc:1; + u64 intd:1; + u64 waitl_com:1; + u64 reserved_21_63:43; +#endif + } s; +}; + +union cvmx_npei_ctl_port1 { + u64 u64; + struct cvmx_npei_ctl_port1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 waitl_com:1; + u64 intd:1; + u64 intc:1; + u64 intb:1; + u64 inta:1; + u64 intd_map:2; + u64 intc_map:2; + u64 intb_map:2; + u64 inta_map:2; + u64 ctlp_ro:1; + u64 reserved_6_6:1; + u64 ptlp_ro:1; + u64 bar2_enb:1; + u64 bar2_esx:2; + u64 bar2_cax:1; + u64 wait_com:1; +#else + u64 wait_com:1; + u64 bar2_cax:1; + u64 bar2_esx:2; + u64 bar2_enb:1; + u64 ptlp_ro:1; + u64 reserved_6_6:1; + u64 ctlp_ro:1; + u64 inta_map:2; + u64 intb_map:2; + u64 intc_map:2; + u64 intd_map:2; + u64 inta:1; + u64 intb:1; + u64 intc:1; + u64 intd:1; + u64 waitl_com:1; + u64 reserved_21_63:43; +#endif + } s; +}; + +union cvmx_npei_ctl_status { + u64 u64; + struct cvmx_npei_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 p1_ntags:6; + u64 p0_ntags:6; + u64 cfg_rtry:16; + u64 ring_en:1; + u64 lnk_rst:1; + u64 arb:1; + u64 pkt_bp:4; + u64 host_mode:1; + u64 chip_rev:8; +#else + u64 chip_rev:8; + u64 host_mode:1; + u64 pkt_bp:4; + u64 arb:1; + u64 lnk_rst:1; + u64 ring_en:1; + u64 cfg_rtry:16; + u64 p0_ntags:6; + u64 p1_ntags:6; + u64 reserved_44_63:20; +#endif + } s; + struct cvmx_npei_ctl_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 p1_ntags:6; + u64 p0_ntags:6; + u64 cfg_rtry:16; + u64 reserved_15_15:1; + u64 lnk_rst:1; + u64 arb:1; + u64 reserved_9_12:4; + u64 host_mode:1; + u64 chip_rev:8; +#else + u64 chip_rev:8; + u64 host_mode:1; + u64 reserved_9_12:4; + u64 arb:1; + u64 lnk_rst:1; + u64 reserved_15_15:1; + u64 cfg_rtry:16; + u64 p0_ntags:6; + u64 p1_ntags:6; + u64 reserved_44_63:20; +#endif + } cn52xxp1; + struct cvmx_npei_ctl_status_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 lnk_rst:1; + u64 arb:1; + u64 pkt_bp:4; + u64 host_mode:1; + u64 chip_rev:8; +#else + u64 chip_rev:8; + u64 host_mode:1; + u64 pkt_bp:4; + u64 arb:1; + u64 lnk_rst:1; + u64 reserved_15_63:49; +#endif + } cn56xxp1; +}; + +union cvmx_npei_ctl_status2 { + u64 u64; + struct cvmx_npei_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 mps:1; + u64 mrrs:3; + u64 c1_w_flt:1; + u64 c0_w_flt:1; + u64 c1_b1_s:3; + u64 c0_b1_s:3; + u64 c1_wi_d:1; + u64 c1_b0_d:1; + u64 c0_wi_d:1; + u64 c0_b0_d:1; +#else + u64 c0_b0_d:1; + u64 c0_wi_d:1; + u64 c1_b0_d:1; + u64 c1_wi_d:1; + u64 c0_b1_s:3; + u64 c1_b1_s:3; + u64 c0_w_flt:1; + u64 c1_w_flt:1; + u64 mrrs:3; + u64 mps:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npei_data_out_cnt { + u64 u64; + struct cvmx_npei_data_out_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 p1_ucnt:16; + u64 p1_fcnt:6; + u64 p0_ucnt:16; + u64 p0_fcnt:6; +#else + u64 p0_fcnt:6; + u64 p0_ucnt:16; + u64 p1_fcnt:6; + u64 p1_ucnt:16; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npei_dbg_data { + u64 u64; + struct cvmx_npei_dbg_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 qlm0_rev_lanes:1; + u64 reserved_25_26:2; + u64 qlm1_spd:2; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 qlm1_spd:2; + u64 reserved_25_26:2; + u64 qlm0_rev_lanes:1; + u64 reserved_28_63:36; +#endif + } s; + struct cvmx_npei_dbg_data_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 qlm0_link_width:1; + u64 qlm0_rev_lanes:1; + u64 qlm1_mode:2; + u64 qlm1_spd:2; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 qlm1_spd:2; + u64 qlm1_mode:2; + u64 qlm0_rev_lanes:1; + u64 qlm0_link_width:1; + u64 reserved_29_63:35; +#endif + } cn52xx; + struct cvmx_npei_dbg_data_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 qlm2_rev_lanes:1; + u64 qlm0_rev_lanes:1; + u64 qlm3_spd:2; + u64 qlm1_spd:2; + u64 c_mul:5; + u64 dsel_ext:1; + u64 data:17; +#else + u64 data:17; + u64 dsel_ext:1; + u64 c_mul:5; + u64 qlm1_spd:2; + u64 qlm3_spd:2; + u64 qlm0_rev_lanes:1; + u64 qlm2_rev_lanes:1; + u64 reserved_29_63:35; +#endif + } cn56xx; +}; + +union cvmx_npei_dbg_select { + u64 u64; + struct cvmx_npei_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dbg_sel:16; +#else + u64 dbg_sel:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npei_dmax_counts { + u64 u64; + struct cvmx_npei_dmax_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 fcnt:7; + u64 dbell:32; +#else + u64 dbell:32; + u64 fcnt:7; + u64 reserved_39_63:25; +#endif + } s; +}; + +union cvmx_npei_dmax_dbell { + u32 u32; + struct cvmx_npei_dmax_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_16_31:16; + u32 dbell:16; +#else + u32 dbell:16; + u32 reserved_16_31:16; +#endif + } s; +}; + +union cvmx_npei_dmax_ibuff_saddr { + u64 u64; + struct cvmx_npei_dmax_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 idle:1; + u64 saddr:29; + u64 reserved_0_6:7; +#else + u64 reserved_0_6:7; + u64 saddr:29; + u64 idle:1; + u64 reserved_37_63:27; +#endif + } s; + struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 saddr:29; + u64 reserved_0_6:7; +#else + u64 reserved_0_6:7; + u64 saddr:29; + u64 reserved_36_63:28; +#endif + } cn52xxp1; +}; + +union cvmx_npei_dmax_naddr { + u64 u64; + struct cvmx_npei_dmax_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 addr:36; +#else + u64 addr:36; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_npei_dma0_int_level { + u64 u64; + struct cvmx_npei_dma0_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 time:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 time:32; +#endif + } s; +}; + +union cvmx_npei_dma1_int_level { + u64 u64; + struct cvmx_npei_dma1_int_level_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 time:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 time:32; +#endif + } s; +}; + +union cvmx_npei_dma_cnts { + u64 u64; + struct cvmx_npei_dma_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dma1:32; + u64 dma0:32; +#else + u64 dma0:32; + u64 dma1:32; +#endif + } s; +}; + +union cvmx_npei_dma_control { + u64 u64; + struct cvmx_npei_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 p_32b_m:1; + u64 dma4_enb:1; + u64 dma3_enb:1; + u64 dma2_enb:1; + u64 dma1_enb:1; + u64 dma0_enb:1; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 csize:14; +#else + u64 csize:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 dma0_enb:1; + u64 dma1_enb:1; + u64 dma2_enb:1; + u64 dma3_enb:1; + u64 dma4_enb:1; + u64 p_32b_m:1; + u64 reserved_40_63:24; +#endif + } s; + struct cvmx_npei_dma_control_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 dma3_enb:1; + u64 dma2_enb:1; + u64 dma1_enb:1; + u64 dma0_enb:1; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 csize:14; +#else + u64 csize:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 dma0_enb:1; + u64 dma1_enb:1; + u64 dma2_enb:1; + u64 dma3_enb:1; + u64 reserved_38_63:26; +#endif + } cn52xxp1; + struct cvmx_npei_dma_control_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 dma4_enb:1; + u64 dma3_enb:1; + u64 dma2_enb:1; + u64 dma1_enb:1; + u64 dma0_enb:1; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 csize:14; +#else + u64 csize:14; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 dma0_enb:1; + u64 dma1_enb:1; + u64 dma2_enb:1; + u64 dma3_enb:1; + u64 dma4_enb:1; + u64 reserved_39_63:25; +#endif + } cn56xxp1; +}; + +union cvmx_npei_dma_pcie_req_num { + u64 u64; + struct cvmx_npei_dma_pcie_req_num_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dma_arb:1; + u64 reserved_53_62:10; + u64 pkt_cnt:5; + u64 reserved_45_47:3; + u64 dma4_cnt:5; + u64 reserved_37_39:3; + u64 dma3_cnt:5; + u64 reserved_29_31:3; + u64 dma2_cnt:5; + u64 reserved_21_23:3; + u64 dma1_cnt:5; + u64 reserved_13_15:3; + u64 dma0_cnt:5; + u64 reserved_5_7:3; + u64 dma_cnt:5; +#else + u64 dma_cnt:5; + u64 reserved_5_7:3; + u64 dma0_cnt:5; + u64 reserved_13_15:3; + u64 dma1_cnt:5; + u64 reserved_21_23:3; + u64 dma2_cnt:5; + u64 reserved_29_31:3; + u64 dma3_cnt:5; + u64 reserved_37_39:3; + u64 dma4_cnt:5; + u64 reserved_45_47:3; + u64 pkt_cnt:5; + u64 reserved_53_62:10; + u64 dma_arb:1; +#endif + } s; +}; + +union cvmx_npei_dma_state1 { + u64 u64; + struct cvmx_npei_dma_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 d4_dwe:8; + u64 d3_dwe:8; + u64 d2_dwe:8; + u64 d1_dwe:8; + u64 d0_dwe:8; +#else + u64 d0_dwe:8; + u64 d1_dwe:8; + u64 d2_dwe:8; + u64 d3_dwe:8; + u64 d4_dwe:8; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_npei_dma_state1_p1 { + u64 u64; + struct cvmx_npei_dma_state1_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 d0_difst:7; + u64 d1_difst:7; + u64 d2_difst:7; + u64 d3_difst:7; + u64 d4_difst:7; + u64 d0_reqst:5; + u64 d1_reqst:5; + u64 d2_reqst:5; + u64 d3_reqst:5; + u64 d4_reqst:5; +#else + u64 d4_reqst:5; + u64 d3_reqst:5; + u64 d2_reqst:5; + u64 d1_reqst:5; + u64 d0_reqst:5; + u64 d4_difst:7; + u64 d3_difst:7; + u64 d2_difst:7; + u64 d1_difst:7; + u64 d0_difst:7; + u64 reserved_60_63:4; +#endif + } s; + struct cvmx_npei_dma_state1_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 d0_difst:7; + u64 d1_difst:7; + u64 d2_difst:7; + u64 d3_difst:7; + u64 reserved_25_31:7; + u64 d0_reqst:5; + u64 d1_reqst:5; + u64 d2_reqst:5; + u64 d3_reqst:5; + u64 reserved_0_4:5; +#else + u64 reserved_0_4:5; + u64 d3_reqst:5; + u64 d2_reqst:5; + u64 d1_reqst:5; + u64 d0_reqst:5; + u64 reserved_25_31:7; + u64 d3_difst:7; + u64 d2_difst:7; + u64 d1_difst:7; + u64 d0_difst:7; + u64 reserved_60_63:4; +#endif + } cn52xxp1; +}; + +union cvmx_npei_dma_state2 { + u64 u64; + struct cvmx_npei_dma_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 ndwe:4; + u64 reserved_21_23:3; + u64 ndre:5; + u64 reserved_10_15:6; + u64 prd:10; +#else + u64 prd:10; + u64 reserved_10_15:6; + u64 ndre:5; + u64 reserved_21_23:3; + u64 ndwe:4; + u64 reserved_28_63:36; +#endif + } s; +}; + +union cvmx_npei_dma_state2_p1 { + u64 u64; + struct cvmx_npei_dma_state2_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 d0_dffst:9; + u64 d1_dffst:9; + u64 d2_dffst:9; + u64 d3_dffst:9; + u64 d4_dffst:9; +#else + u64 d4_dffst:9; + u64 d3_dffst:9; + u64 d2_dffst:9; + u64 d1_dffst:9; + u64 d0_dffst:9; + u64 reserved_45_63:19; +#endif + } s; + struct cvmx_npei_dma_state2_p1_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 d0_dffst:9; + u64 d1_dffst:9; + u64 d2_dffst:9; + u64 d3_dffst:9; + u64 reserved_0_8:9; +#else + u64 reserved_0_8:9; + u64 d3_dffst:9; + u64 d2_dffst:9; + u64 d1_dffst:9; + u64 d0_dffst:9; + u64 reserved_45_63:19; +#endif + } cn52xxp1; +}; + +union cvmx_npei_dma_state3_p1 { + u64 u64; + struct cvmx_npei_dma_state3_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 d0_drest:15; + u64 d1_drest:15; + u64 d2_drest:15; + u64 d3_drest:15; +#else + u64 d3_drest:15; + u64 d2_drest:15; + u64 d1_drest:15; + u64 d0_drest:15; + u64 reserved_60_63:4; +#endif + } s; +}; + +union cvmx_npei_dma_state4_p1 { + u64 u64; + struct cvmx_npei_dma_state4_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + u64 d0_dwest:13; + u64 d1_dwest:13; + u64 d2_dwest:13; + u64 d3_dwest:13; +#else + u64 d3_dwest:13; + u64 d2_dwest:13; + u64 d1_dwest:13; + u64 d0_dwest:13; + u64 reserved_52_63:12; +#endif + } s; +}; + +union cvmx_npei_dma_state5_p1 { + u64 u64; + struct cvmx_npei_dma_state5_p1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 d4_drest:15; + u64 d4_dwest:13; +#else + u64 d4_dwest:13; + u64 d4_drest:15; + u64 reserved_28_63:36; +#endif + } s; +}; + +union cvmx_npei_int_a_enb { + u64 u64; + struct cvmx_npei_int_a_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pout_err:1; + u64 pin_bp:1; + u64 p1_rdlk:1; + u64 p0_rdlk:1; + u64 pgl_err:1; + u64 pdi_err:1; + u64 pop_err:1; + u64 pins_err:1; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 pins_err:1; + u64 pop_err:1; + u64 pdi_err:1; + u64 pgl_err:1; + u64 p0_rdlk:1; + u64 p1_rdlk:1; + u64 pin_bp:1; + u64 pout_err:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_npei_int_a_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 reserved_2_63:62; +#endif + } cn52xxp1; +}; + +union cvmx_npei_int_a_enb2 { + u64 u64; + struct cvmx_npei_int_a_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pout_err:1; + u64 pin_bp:1; + u64 p1_rdlk:1; + u64 p0_rdlk:1; + u64 pgl_err:1; + u64 pdi_err:1; + u64 pop_err:1; + u64 pins_err:1; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 pins_err:1; + u64 pop_err:1; + u64 pdi_err:1; + u64 pgl_err:1; + u64 p0_rdlk:1; + u64 p1_rdlk:1; + u64 pin_bp:1; + u64 pout_err:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_npei_int_a_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 reserved_2_63:62; +#endif + } cn52xxp1; +}; + +union cvmx_npei_int_a_sum { + u64 u64; + struct cvmx_npei_int_a_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pout_err:1; + u64 pin_bp:1; + u64 p1_rdlk:1; + u64 p0_rdlk:1; + u64 pgl_err:1; + u64 pdi_err:1; + u64 pop_err:1; + u64 pins_err:1; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 pins_err:1; + u64 pop_err:1; + u64 pdi_err:1; + u64 pgl_err:1; + u64 p0_rdlk:1; + u64 p1_rdlk:1; + u64 pin_bp:1; + u64 pout_err:1; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_npei_int_a_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 dma1_cpl:1; + u64 dma0_cpl:1; +#else + u64 dma0_cpl:1; + u64 dma1_cpl:1; + u64 reserved_2_63:62; +#endif + } cn52xxp1; +}; + +union cvmx_npei_int_enb { + u64 u64; + struct cvmx_npei_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_62_62:1; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_62:1; + u64 mio_inta:1; +#endif + } s; + struct cvmx_npei_int_enb_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_62_62:1; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 reserved_8_8:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 reserved_8_8:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_62:1; + u64 mio_inta:1; +#endif + } cn52xxp1; + struct cvmx_npei_int_enb_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_61_62:2; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 reserved_29_29:1; + u64 c1_se:1; + u64 reserved_27_27:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 reserved_22_22:1; + u64 c0_se:1; + u64 reserved_20_20:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 reserved_20_20:1; + u64 c0_se:1; + u64 reserved_22_22:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 reserved_27_27:1; + u64 c1_se:1; + u64 reserved_29_29:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 reserved_61_62:2; + u64 mio_inta:1; +#endif + } cn56xxp1; +}; + +union cvmx_npei_int_enb2 { + u64 u64; + struct cvmx_npei_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_63:2; +#endif + } s; + struct cvmx_npei_int_enb2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 reserved_8_8:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 reserved_8_8:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_63:2; +#endif + } cn52xxp1; + struct cvmx_npei_int_enb2_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 reserved_29_29:1; + u64 c1_se:1; + u64 reserved_27_27:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 reserved_22_22:1; + u64 c0_se:1; + u64 reserved_20_20:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 reserved_20_20:1; + u64 c0_se:1; + u64 reserved_22_22:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 reserved_27_27:1; + u64 c1_se:1; + u64 reserved_29_29:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 reserved_61_63:3; +#endif + } cn56xxp1; +}; + +union cvmx_npei_int_info { + u64 u64; + struct cvmx_npei_int_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 pidbof:6; + u64 psldbof:6; +#else + u64 psldbof:6; + u64 pidbof:6; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_npei_int_sum { + u64 u64; + struct cvmx_npei_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_62_62:1; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 ptime:1; + u64 pcnt:1; + u64 pidbof:1; + u64 psldbof:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 psldbof:1; + u64 pidbof:1; + u64 pcnt:1; + u64 ptime:1; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_62:1; + u64 mio_inta:1; +#endif + } s; + struct cvmx_npei_int_sum_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_62_62:1; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 reserved_15_18:4; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 reserved_8_8:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 reserved_8_8:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 reserved_15_18:4; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_62:1; + u64 mio_inta:1; +#endif + } cn52xxp1; + struct cvmx_npei_int_sum_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_61_62:2; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 reserved_29_29:1; + u64 c1_se:1; + u64 reserved_27_27:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 reserved_22_22:1; + u64 c0_se:1; + u64 reserved_20_20:1; + u64 c0_aeri:1; + u64 reserved_15_18:4; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 dma4dbo:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 dma4dbo:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 reserved_15_18:4; + u64 c0_aeri:1; + u64 reserved_20_20:1; + u64 c0_se:1; + u64 reserved_22_22:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 reserved_27_27:1; + u64 c1_se:1; + u64 reserved_29_29:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 reserved_61_62:2; + u64 mio_inta:1; +#endif + } cn56xxp1; +}; + +union cvmx_npei_int_sum2 { + u64 u64; + struct cvmx_npei_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 mio_inta:1; + u64 reserved_62_62:1; + u64 int_a:1; + u64 c1_ldwn:1; + u64 c0_ldwn:1; + u64 c1_exc:1; + u64 c0_exc:1; + u64 c1_up_wf:1; + u64 c0_up_wf:1; + u64 c1_un_wf:1; + u64 c0_un_wf:1; + u64 c1_un_bx:1; + u64 c1_un_wi:1; + u64 c1_un_b2:1; + u64 c1_un_b1:1; + u64 c1_un_b0:1; + u64 c1_up_bx:1; + u64 c1_up_wi:1; + u64 c1_up_b2:1; + u64 c1_up_b1:1; + u64 c1_up_b0:1; + u64 c0_un_bx:1; + u64 c0_un_wi:1; + u64 c0_un_b2:1; + u64 c0_un_b1:1; + u64 c0_un_b0:1; + u64 c0_up_bx:1; + u64 c0_up_wi:1; + u64 c0_up_b2:1; + u64 c0_up_b1:1; + u64 c0_up_b0:1; + u64 c1_hpint:1; + u64 c1_pmei:1; + u64 c1_wake:1; + u64 crs1_dr:1; + u64 c1_se:1; + u64 crs1_er:1; + u64 c1_aeri:1; + u64 c0_hpint:1; + u64 c0_pmei:1; + u64 c0_wake:1; + u64 crs0_dr:1; + u64 c0_se:1; + u64 crs0_er:1; + u64 c0_aeri:1; + u64 reserved_15_18:4; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 dma1fi:1; + u64 dma0fi:1; + u64 reserved_8_8:1; + u64 dma3dbo:1; + u64 dma2dbo:1; + u64 dma1dbo:1; + u64 dma0dbo:1; + u64 iob2big:1; + u64 bar0_to:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 bar0_to:1; + u64 iob2big:1; + u64 dma0dbo:1; + u64 dma1dbo:1; + u64 dma2dbo:1; + u64 dma3dbo:1; + u64 reserved_8_8:1; + u64 dma0fi:1; + u64 dma1fi:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 reserved_15_18:4; + u64 c0_aeri:1; + u64 crs0_er:1; + u64 c0_se:1; + u64 crs0_dr:1; + u64 c0_wake:1; + u64 c0_pmei:1; + u64 c0_hpint:1; + u64 c1_aeri:1; + u64 crs1_er:1; + u64 c1_se:1; + u64 crs1_dr:1; + u64 c1_wake:1; + u64 c1_pmei:1; + u64 c1_hpint:1; + u64 c0_up_b0:1; + u64 c0_up_b1:1; + u64 c0_up_b2:1; + u64 c0_up_wi:1; + u64 c0_up_bx:1; + u64 c0_un_b0:1; + u64 c0_un_b1:1; + u64 c0_un_b2:1; + u64 c0_un_wi:1; + u64 c0_un_bx:1; + u64 c1_up_b0:1; + u64 c1_up_b1:1; + u64 c1_up_b2:1; + u64 c1_up_wi:1; + u64 c1_up_bx:1; + u64 c1_un_b0:1; + u64 c1_un_b1:1; + u64 c1_un_b2:1; + u64 c1_un_wi:1; + u64 c1_un_bx:1; + u64 c0_un_wf:1; + u64 c1_un_wf:1; + u64 c0_up_wf:1; + u64 c1_up_wf:1; + u64 c0_exc:1; + u64 c1_exc:1; + u64 c0_ldwn:1; + u64 c1_ldwn:1; + u64 int_a:1; + u64 reserved_62_62:1; + u64 mio_inta:1; +#endif + } s; +}; + +union cvmx_npei_last_win_rdata0 { + u64 u64; + struct cvmx_npei_last_win_rdata0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_npei_last_win_rdata1 { + u64 u64; + struct cvmx_npei_last_win_rdata1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_npei_mem_access_ctl { + u64 u64; + struct cvmx_npei_mem_access_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 max_word:4; + u64 timer:10; +#else + u64 timer:10; + u64 max_word:4; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_npei_mem_access_subidx { + u64 u64; + struct cvmx_npei_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 zero:1; + u64 port:2; + u64 nmerge:1; + u64 esr:2; + u64 esw:2; + u64 nsr:1; + u64 nsw:1; + u64 ror:1; + u64 row:1; + u64 ba:30; +#else + u64 ba:30; + u64 row:1; + u64 ror:1; + u64 nsw:1; + u64 nsr:1; + u64 esw:2; + u64 esr:2; + u64 nmerge:1; + u64 port:2; + u64 zero:1; + u64 reserved_42_63:22; +#endif + } s; +}; + +union cvmx_npei_msi_enb0 { + u64 u64; + struct cvmx_npei_msi_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 enb:64; +#else + u64 enb:64; +#endif + } s; +}; + +union cvmx_npei_msi_enb1 { + u64 u64; + struct cvmx_npei_msi_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 enb:64; +#else + u64 enb:64; +#endif + } s; +}; + +union cvmx_npei_msi_enb2 { + u64 u64; + struct cvmx_npei_msi_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 enb:64; +#else + u64 enb:64; +#endif + } s; +}; + +union cvmx_npei_msi_enb3 { + u64 u64; + struct cvmx_npei_msi_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 enb:64; +#else + u64 enb:64; +#endif + } s; +}; + +union cvmx_npei_msi_rcv0 { + u64 u64; + struct cvmx_npei_msi_rcv0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 intr:64; +#else + u64 intr:64; +#endif + } s; +}; + +union cvmx_npei_msi_rcv1 { + u64 u64; + struct cvmx_npei_msi_rcv1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 intr:64; +#else + u64 intr:64; +#endif + } s; +}; + +union cvmx_npei_msi_rcv2 { + u64 u64; + struct cvmx_npei_msi_rcv2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 intr:64; +#else + u64 intr:64; +#endif + } s; +}; + +union cvmx_npei_msi_rcv3 { + u64 u64; + struct cvmx_npei_msi_rcv3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 intr:64; +#else + u64 intr:64; +#endif + } s; +}; + +union cvmx_npei_msi_rd_map { + u64 u64; + struct cvmx_npei_msi_rd_map_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 rd_int:8; + u64 msi_int:8; +#else + u64 msi_int:8; + u64 rd_int:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npei_msi_w1c_enb0 { + u64 u64; + struct cvmx_npei_msi_w1c_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 clr:64; +#else + u64 clr:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1c_enb1 { + u64 u64; + struct cvmx_npei_msi_w1c_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 clr:64; +#else + u64 clr:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1c_enb2 { + u64 u64; + struct cvmx_npei_msi_w1c_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 clr:64; +#else + u64 clr:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1c_enb3 { + u64 u64; + struct cvmx_npei_msi_w1c_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 clr:64; +#else + u64 clr:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1s_enb0 { + u64 u64; + struct cvmx_npei_msi_w1s_enb0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 set:64; +#else + u64 set:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1s_enb1 { + u64 u64; + struct cvmx_npei_msi_w1s_enb1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 set:64; +#else + u64 set:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1s_enb2 { + u64 u64; + struct cvmx_npei_msi_w1s_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 set:64; +#else + u64 set:64; +#endif + } s; +}; + +union cvmx_npei_msi_w1s_enb3 { + u64 u64; + struct cvmx_npei_msi_w1s_enb3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 set:64; +#else + u64 set:64; +#endif + } s; +}; + +union cvmx_npei_msi_wr_map { + u64 u64; + struct cvmx_npei_msi_wr_map_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 ciu_int:8; + u64 msi_int:8; +#else + u64 msi_int:8; + u64 ciu_int:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npei_pcie_credit_cnt { + u64 u64; + struct cvmx_npei_pcie_credit_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 p1_ccnt:8; + u64 p1_ncnt:8; + u64 p1_pcnt:8; + u64 p0_ccnt:8; + u64 p0_ncnt:8; + u64 p0_pcnt:8; +#else + u64 p0_pcnt:8; + u64 p0_ncnt:8; + u64 p0_ccnt:8; + u64 p1_pcnt:8; + u64 p1_ncnt:8; + u64 p1_ccnt:8; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_npei_pcie_msi_rcv { + u64 u64; + struct cvmx_npei_pcie_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 intr:8; +#else + u64 intr:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_npei_pcie_msi_rcv_b1 { + u64 u64; + struct cvmx_npei_pcie_msi_rcv_b1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 intr:8; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 intr:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npei_pcie_msi_rcv_b2 { + u64 u64; + struct cvmx_npei_pcie_msi_rcv_b2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 intr:8; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 intr:8; + u64 reserved_24_63:40; +#endif + } s; +}; + +union cvmx_npei_pcie_msi_rcv_b3 { + u64 u64; + struct cvmx_npei_pcie_msi_rcv_b3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 intr:8; + u64 reserved_0_23:24; +#else + u64 reserved_0_23:24; + u64 intr:8; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pktx_cnts { + u64 u64; + struct cvmx_npei_pktx_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 timer:22; + u64 cnt:32; +#else + u64 cnt:32; + u64 timer:22; + u64 reserved_54_63:10; +#endif + } s; +}; + +union cvmx_npei_pktx_in_bp { + u64 u64; + struct cvmx_npei_pktx_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wmark:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 wmark:32; +#endif + } s; +}; + +union cvmx_npei_pktx_instr_baddr { + u64 u64; + struct cvmx_npei_pktx_instr_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:61; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 addr:61; +#endif + } s; +}; + +union cvmx_npei_pktx_instr_baoff_dbell { + u64 u64; + struct cvmx_npei_pktx_instr_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 aoff:32; + u64 dbell:32; +#else + u64 dbell:32; + u64 aoff:32; +#endif + } s; +}; + +union cvmx_npei_pktx_instr_fifo_rsize { + u64 u64; + struct cvmx_npei_pktx_instr_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 max:9; + u64 rrp:9; + u64 wrp:9; + u64 fcnt:5; + u64 rsize:32; +#else + u64 rsize:32; + u64 fcnt:5; + u64 wrp:9; + u64 rrp:9; + u64 max:9; +#endif + } s; +}; + +union cvmx_npei_pktx_instr_header { + u64 u64; + struct cvmx_npei_pktx_instr_header_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 pbp:1; + u64 reserved_38_42:5; + u64 rparmode:2; + u64 reserved_35_35:1; + u64 rskp_len:7; + u64 reserved_22_27:6; + u64 use_ihdr:1; + u64 reserved_16_20:5; + u64 par_mode:2; + u64 reserved_13_13:1; + u64 skp_len:7; + u64 reserved_0_5:6; +#else + u64 reserved_0_5:6; + u64 skp_len:7; + u64 reserved_13_13:1; + u64 par_mode:2; + u64 reserved_16_20:5; + u64 use_ihdr:1; + u64 reserved_22_27:6; + u64 rskp_len:7; + u64 reserved_35_35:1; + u64 rparmode:2; + u64 reserved_38_42:5; + u64 pbp:1; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npei_pktx_slist_baddr { + u64 u64; + struct cvmx_npei_pktx_slist_baddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:60; + u64 reserved_0_3:4; +#else + u64 reserved_0_3:4; + u64 addr:60; +#endif + } s; +}; + +union cvmx_npei_pktx_slist_baoff_dbell { + u64 u64; + struct cvmx_npei_pktx_slist_baoff_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 aoff:32; + u64 dbell:32; +#else + u64 dbell:32; + u64 aoff:32; +#endif + } s; +}; + +union cvmx_npei_pktx_slist_fifo_rsize { + u64 u64; + struct cvmx_npei_pktx_slist_fifo_rsize_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rsize:32; +#else + u64 rsize:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_cnt_int { + u64 u64; + struct cvmx_npei_pkt_cnt_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 port:32; +#else + u64 port:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_cnt_int_enb { + u64 u64; + struct cvmx_npei_pkt_cnt_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 port:32; +#else + u64 port:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_data_out_es { + u64 u64; + struct cvmx_npei_pkt_data_out_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 es:64; +#else + u64 es:64; +#endif + } s; +}; + +union cvmx_npei_pkt_data_out_ns { + u64 u64; + struct cvmx_npei_pkt_data_out_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nsr:32; +#else + u64 nsr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_data_out_ror { + u64 u64; + struct cvmx_npei_pkt_data_out_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ror:32; +#else + u64 ror:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_dpaddr { + u64 u64; + struct cvmx_npei_pkt_dpaddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 dptr:32; +#else + u64 dptr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_in_bp { + u64 u64; + struct cvmx_npei_pkt_in_bp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bp:32; +#else + u64 bp:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_in_donex_cnts { + u64 u64; + struct cvmx_npei_pkt_in_donex_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_in_instr_counts { + u64 u64; + struct cvmx_npei_pkt_in_instr_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wr_cnt:32; + u64 rd_cnt:32; +#else + u64 rd_cnt:32; + u64 wr_cnt:32; +#endif + } s; +}; + +union cvmx_npei_pkt_in_pcie_port { + u64 u64; + struct cvmx_npei_pkt_in_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pp:64; +#else + u64 pp:64; +#endif + } s; +}; + +union cvmx_npei_pkt_input_control { + u64 u64; + struct cvmx_npei_pkt_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 pkt_rr:1; + u64 pbp_dhi:13; + u64 d_nsr:1; + u64 d_esr:2; + u64 d_ror:1; + u64 use_csr:1; + u64 nsr:1; + u64 esr:2; + u64 ror:1; +#else + u64 ror:1; + u64 esr:2; + u64 nsr:1; + u64 use_csr:1; + u64 d_ror:1; + u64 d_esr:2; + u64 d_nsr:1; + u64 pbp_dhi:13; + u64 pkt_rr:1; + u64 reserved_23_63:41; +#endif + } s; +}; + +union cvmx_npei_pkt_instr_enb { + u64 u64; + struct cvmx_npei_pkt_instr_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enb:32; +#else + u64 enb:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_instr_rd_size { + u64 u64; + struct cvmx_npei_pkt_instr_rd_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rdsize:64; +#else + u64 rdsize:64; +#endif + } s; +}; + +union cvmx_npei_pkt_instr_size { + u64 u64; + struct cvmx_npei_pkt_instr_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 is_64b:32; +#else + u64 is_64b:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_int_levels { + u64 u64; + struct cvmx_npei_pkt_int_levels_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 time:22; + u64 cnt:32; +#else + u64 cnt:32; + u64 time:22; + u64 reserved_54_63:10; +#endif + } s; +}; + +union cvmx_npei_pkt_iptr { + u64 u64; + struct cvmx_npei_pkt_iptr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iptr:32; +#else + u64 iptr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_out_bmode { + u64 u64; + struct cvmx_npei_pkt_out_bmode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bmode:32; +#else + u64 bmode:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_out_enb { + u64 u64; + struct cvmx_npei_pkt_out_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enb:32; +#else + u64 enb:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_output_wmark { + u64 u64; + struct cvmx_npei_pkt_output_wmark_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wmark:32; +#else + u64 wmark:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_pcie_port { + u64 u64; + struct cvmx_npei_pkt_pcie_port_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pp:64; +#else + u64 pp:64; +#endif + } s; +}; + +union cvmx_npei_pkt_port_in_rst { + u64 u64; + struct cvmx_npei_pkt_port_in_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 in_rst:32; + u64 out_rst:32; +#else + u64 out_rst:32; + u64 in_rst:32; +#endif + } s; +}; + +union cvmx_npei_pkt_slist_es { + u64 u64; + struct cvmx_npei_pkt_slist_es_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 es:64; +#else + u64 es:64; +#endif + } s; +}; + +union cvmx_npei_pkt_slist_id_size { + u64 u64; + struct cvmx_npei_pkt_slist_id_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 isize:7; + u64 bsize:16; +#else + u64 bsize:16; + u64 isize:7; + u64 reserved_23_63:41; +#endif + } s; +}; + +union cvmx_npei_pkt_slist_ns { + u64 u64; + struct cvmx_npei_pkt_slist_ns_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 nsr:32; +#else + u64 nsr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_slist_ror { + u64 u64; + struct cvmx_npei_pkt_slist_ror_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ror:32; +#else + u64 ror:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_time_int { + u64 u64; + struct cvmx_npei_pkt_time_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 port:32; +#else + u64 port:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_pkt_time_int_enb { + u64 u64; + struct cvmx_npei_pkt_time_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 port:32; +#else + u64 port:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npei_rsl_int_blocks { + u64 u64; + struct cvmx_npei_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 iob:1; + u64 lmc1:1; + u64 agl:1; + u64 reserved_24_27:4; + u64 asxpcs1:1; + u64 asxpcs0:1; + u64 reserved_21_21:1; + u64 pip:1; + u64 spx1:1; + u64 spx0:1; + u64 lmc0:1; + u64 l2c:1; + u64 usb1:1; + u64 rad:1; + u64 usb:1; + u64 pow:1; + u64 tim:1; + u64 pko:1; + u64 ipd:1; + u64 reserved_8_8:1; + u64 zip:1; + u64 dfa:1; + u64 fpa:1; + u64 key:1; + u64 npei:1; + u64 gmx1:1; + u64 gmx0:1; + u64 mio:1; +#else + u64 mio:1; + u64 gmx0:1; + u64 gmx1:1; + u64 npei:1; + u64 key:1; + u64 fpa:1; + u64 dfa:1; + u64 zip:1; + u64 reserved_8_8:1; + u64 ipd:1; + u64 pko:1; + u64 tim:1; + u64 pow:1; + u64 usb:1; + u64 rad:1; + u64 usb1:1; + u64 l2c:1; + u64 lmc0:1; + u64 spx0:1; + u64 spx1:1; + u64 pip:1; + u64 reserved_21_21:1; + u64 asxpcs0:1; + u64 asxpcs1:1; + u64 reserved_24_27:4; + u64 agl:1; + u64 lmc1:1; + u64 iob:1; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_npei_scratch_1 { + u64 u64; + struct cvmx_npei_scratch_1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } s; +}; + +union cvmx_npei_state1 { + u64 u64; + struct cvmx_npei_state1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 cpl1:12; + u64 cpl0:12; + u64 arb:1; + u64 csr:39; +#else + u64 csr:39; + u64 arb:1; + u64 cpl0:12; + u64 cpl1:12; +#endif + } s; +}; + +union cvmx_npei_state2 { + u64 u64; + struct cvmx_npei_state2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 npei:1; + u64 rac:1; + u64 csm1:15; + u64 csm0:15; + u64 nnp0:8; + u64 nnd:8; +#else + u64 nnd:8; + u64 nnp0:8; + u64 csm0:15; + u64 csm1:15; + u64 rac:1; + u64 npei:1; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_npei_state3 { + u64 u64; + struct cvmx_npei_state3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 psm1:15; + u64 psm0:15; + u64 nsm1:13; + u64 nsm0:13; +#else + u64 nsm0:13; + u64 nsm1:13; + u64 psm0:15; + u64 psm1:15; + u64 reserved_56_63:8; +#endif + } s; +}; + +union cvmx_npei_win_rd_addr { + u64 u64; + struct cvmx_npei_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + u64 ld_cmd:2; + u64 iobit:1; + u64 rd_addr:48; +#else + u64 rd_addr:48; + u64 iobit:1; + u64 ld_cmd:2; + u64 reserved_51_63:13; +#endif + } s; +}; + +union cvmx_npei_win_rd_data { + u64 u64; + struct cvmx_npei_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rd_data:64; +#else + u64 rd_data:64; +#endif + } s; +}; + +union cvmx_npei_win_wr_addr { + u64 u64; + struct cvmx_npei_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 iobit:1; + u64 wr_addr:46; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 wr_addr:46; + u64 iobit:1; + u64 reserved_49_63:15; +#endif + } s; +}; + +union cvmx_npei_win_wr_data { + u64 u64; + struct cvmx_npei_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wr_data:64; +#else + u64 wr_data:64; +#endif + } s; +}; + +union cvmx_npei_win_wr_mask { + u64 u64; + struct cvmx_npei_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 wr_mask:8; +#else + u64 wr_mask:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_npei_window_ctl { + u64 u64; + struct cvmx_npei_window_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 time:32; +#else + u64 time:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-npi-defs.h b/drivers/staging/octeon/cvmx-npi-defs.h new file mode 100644 index 000000000000..b84647c324ca --- /dev/null +++ b/drivers/staging/octeon/cvmx-npi-defs.h @@ -0,0 +1,2513 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_NPI_DEFS_H__ +#define __CVMX_NPI_DEFS_H__ + +#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0) +#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1) +#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2) +#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3) +#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16) +#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0) +#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1) +#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2) +#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3) +#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8) +#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull)) +#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0) +#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1) +#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2) +#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3) +#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8) +#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull)) +#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull)) +#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull)) +#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull)) +#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull)) +#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull)) +#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull)) +#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull)) +#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull)) +#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull)) +#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull)) +#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull)) +#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull)) +#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull)) +#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull)) +#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3) +#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4) +#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5) +#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6) +#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8 * 3) +#define CVMX_NPI_MSI_RCV (0x0000000000000190ull) +#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull)) +#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0) +#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1) +#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2) +#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3) +#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8) +#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull)) +#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0) +#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0) +#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0) +#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0) +#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1) +#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1) +#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1) +#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1) +#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2) +#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2) +#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2) +#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2) +#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3) +#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3) +#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3) +#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3) +#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4) +#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull)) +#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull)) +#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull)) +#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull)) +#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull)) +#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull)) +#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull)) +#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull)) +#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull)) +#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull)) +#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull)) +#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull)) +#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull)) +#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull)) +#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull)) +#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull)) +#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull)) +#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull)) +#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull)) +#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull)) +#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull)) +#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull)) +#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull)) +#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull)) +#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull)) +#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull)) +#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull)) +#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull)) +#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull)) +#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull)) +#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull)) +#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull)) +#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull)) +#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull)) +#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull)) +#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull)) +#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull)) +#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull)) +#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull)) +#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull)) +#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull)) +#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull)) +#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull)) +#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull)) +#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull)) +#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull)) +#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull)) +#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull)) +#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8) +#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8) +#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8) +#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8) +#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull)) +#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0) +#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1) +#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2) +#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3) +#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16) +#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull)) + +union cvmx_npi_base_addr_inputx { + u64 u64; + struct cvmx_npi_base_addr_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 baddr:61; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 baddr:61; +#endif + } s; +}; + +union cvmx_npi_base_addr_outputx { + u64 u64; + struct cvmx_npi_base_addr_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 baddr:61; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 baddr:61; +#endif + } s; +}; + +union cvmx_npi_bist_status { + u64 u64; + struct cvmx_npi_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 csr_bs:1; + u64 dif_bs:1; + u64 rdp_bs:1; + u64 pcnc_bs:1; + u64 pcn_bs:1; + u64 rdn_bs:1; + u64 pcac_bs:1; + u64 pcad_bs:1; + u64 rdnl_bs:1; + u64 pgf_bs:1; + u64 pig_bs:1; + u64 pof0_bs:1; + u64 pof1_bs:1; + u64 pof2_bs:1; + u64 pof3_bs:1; + u64 pos_bs:1; + u64 nus_bs:1; + u64 dob_bs:1; + u64 pdf_bs:1; + u64 dpi_bs:1; +#else + u64 dpi_bs:1; + u64 pdf_bs:1; + u64 dob_bs:1; + u64 nus_bs:1; + u64 pos_bs:1; + u64 pof3_bs:1; + u64 pof2_bs:1; + u64 pof1_bs:1; + u64 pof0_bs:1; + u64 pig_bs:1; + u64 pgf_bs:1; + u64 rdnl_bs:1; + u64 pcad_bs:1; + u64 pcac_bs:1; + u64 rdn_bs:1; + u64 pcn_bs:1; + u64 pcnc_bs:1; + u64 rdp_bs:1; + u64 dif_bs:1; + u64 csr_bs:1; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_npi_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 csr_bs:1; + u64 dif_bs:1; + u64 rdp_bs:1; + u64 pcnc_bs:1; + u64 pcn_bs:1; + u64 rdn_bs:1; + u64 pcac_bs:1; + u64 pcad_bs:1; + u64 rdnl_bs:1; + u64 pgf_bs:1; + u64 pig_bs:1; + u64 pof0_bs:1; + u64 reserved_5_7:3; + u64 pos_bs:1; + u64 nus_bs:1; + u64 dob_bs:1; + u64 pdf_bs:1; + u64 dpi_bs:1; +#else + u64 dpi_bs:1; + u64 pdf_bs:1; + u64 dob_bs:1; + u64 nus_bs:1; + u64 pos_bs:1; + u64 reserved_5_7:3; + u64 pof0_bs:1; + u64 pig_bs:1; + u64 pgf_bs:1; + u64 rdnl_bs:1; + u64 pcad_bs:1; + u64 pcac_bs:1; + u64 rdn_bs:1; + u64 pcn_bs:1; + u64 pcnc_bs:1; + u64 rdp_bs:1; + u64 dif_bs:1; + u64 csr_bs:1; + u64 reserved_20_63:44; +#endif + } cn30xx; + struct cvmx_npi_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 csr_bs:1; + u64 dif_bs:1; + u64 rdp_bs:1; + u64 pcnc_bs:1; + u64 pcn_bs:1; + u64 rdn_bs:1; + u64 pcac_bs:1; + u64 pcad_bs:1; + u64 rdnl_bs:1; + u64 pgf_bs:1; + u64 pig_bs:1; + u64 pof0_bs:1; + u64 pof1_bs:1; + u64 reserved_5_6:2; + u64 pos_bs:1; + u64 nus_bs:1; + u64 dob_bs:1; + u64 pdf_bs:1; + u64 dpi_bs:1; +#else + u64 dpi_bs:1; + u64 pdf_bs:1; + u64 dob_bs:1; + u64 nus_bs:1; + u64 pos_bs:1; + u64 reserved_5_6:2; + u64 pof1_bs:1; + u64 pof0_bs:1; + u64 pig_bs:1; + u64 pgf_bs:1; + u64 rdnl_bs:1; + u64 pcad_bs:1; + u64 pcac_bs:1; + u64 rdn_bs:1; + u64 pcn_bs:1; + u64 pcnc_bs:1; + u64 rdp_bs:1; + u64 dif_bs:1; + u64 csr_bs:1; + u64 reserved_20_63:44; +#endif + } cn50xx; +}; + +union cvmx_npi_buff_size_outputx { + u64 u64; + struct cvmx_npi_buff_size_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 isize:7; + u64 bsize:16; +#else + u64 bsize:16; + u64 isize:7; + u64 reserved_23_63:41; +#endif + } s; +}; + +union cvmx_npi_comp_ctl { + u64 u64; + struct cvmx_npi_comp_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 pctl:5; + u64 nctl:5; +#else + u64 nctl:5; + u64 pctl:5; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_npi_ctl_status { + u64 u64; + struct cvmx_npi_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 chip_rev:8; + u64 dis_pniw:1; + u64 out3_enb:1; + u64 out2_enb:1; + u64 out1_enb:1; + u64 out0_enb:1; + u64 ins3_enb:1; + u64 ins2_enb:1; + u64 ins1_enb:1; + u64 ins0_enb:1; + u64 ins3_64b:1; + u64 ins2_64b:1; + u64 ins1_64b:1; + u64 ins0_64b:1; + u64 pci_wdis:1; + u64 wait_com:1; + u64 reserved_37_39:3; + u64 max_word:5; + u64 reserved_10_31:22; + u64 timer:10; +#else + u64 timer:10; + u64 reserved_10_31:22; + u64 max_word:5; + u64 reserved_37_39:3; + u64 wait_com:1; + u64 pci_wdis:1; + u64 ins0_64b:1; + u64 ins1_64b:1; + u64 ins2_64b:1; + u64 ins3_64b:1; + u64 ins0_enb:1; + u64 ins1_enb:1; + u64 ins2_enb:1; + u64 ins3_enb:1; + u64 out0_enb:1; + u64 out1_enb:1; + u64 out2_enb:1; + u64 out3_enb:1; + u64 dis_pniw:1; + u64 chip_rev:8; + u64 reserved_63_63:1; +#endif + } s; + struct cvmx_npi_ctl_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 chip_rev:8; + u64 dis_pniw:1; + u64 reserved_51_53:3; + u64 out0_enb:1; + u64 reserved_47_49:3; + u64 ins0_enb:1; + u64 reserved_43_45:3; + u64 ins0_64b:1; + u64 pci_wdis:1; + u64 wait_com:1; + u64 reserved_37_39:3; + u64 max_word:5; + u64 reserved_10_31:22; + u64 timer:10; +#else + u64 timer:10; + u64 reserved_10_31:22; + u64 max_word:5; + u64 reserved_37_39:3; + u64 wait_com:1; + u64 pci_wdis:1; + u64 ins0_64b:1; + u64 reserved_43_45:3; + u64 ins0_enb:1; + u64 reserved_47_49:3; + u64 out0_enb:1; + u64 reserved_51_53:3; + u64 dis_pniw:1; + u64 chip_rev:8; + u64 reserved_63_63:1; +#endif + } cn30xx; + struct cvmx_npi_ctl_status_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 chip_rev:8; + u64 dis_pniw:1; + u64 reserved_52_53:2; + u64 out1_enb:1; + u64 out0_enb:1; + u64 reserved_48_49:2; + u64 ins1_enb:1; + u64 ins0_enb:1; + u64 reserved_44_45:2; + u64 ins1_64b:1; + u64 ins0_64b:1; + u64 pci_wdis:1; + u64 wait_com:1; + u64 reserved_37_39:3; + u64 max_word:5; + u64 reserved_10_31:22; + u64 timer:10; +#else + u64 timer:10; + u64 reserved_10_31:22; + u64 max_word:5; + u64 reserved_37_39:3; + u64 wait_com:1; + u64 pci_wdis:1; + u64 ins0_64b:1; + u64 ins1_64b:1; + u64 reserved_44_45:2; + u64 ins0_enb:1; + u64 ins1_enb:1; + u64 reserved_48_49:2; + u64 out0_enb:1; + u64 out1_enb:1; + u64 reserved_52_53:2; + u64 dis_pniw:1; + u64 chip_rev:8; + u64 reserved_63_63:1; +#endif + } cn31xx; +}; + +union cvmx_npi_dbg_select { + u64 u64; + struct cvmx_npi_dbg_select_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dbg_sel:16; +#else + u64 dbg_sel:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npi_dma_control { + u64 u64; + struct cvmx_npi_dma_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 b0_lend:1; + u64 dwb_denb:1; + u64 dwb_ichk:9; + u64 fpa_que:3; + u64 o_add1:1; + u64 o_ro:1; + u64 o_ns:1; + u64 o_es:2; + u64 o_mode:1; + u64 hp_enb:1; + u64 lp_enb:1; + u64 csize:14; +#else + u64 csize:14; + u64 lp_enb:1; + u64 hp_enb:1; + u64 o_mode:1; + u64 o_es:2; + u64 o_ns:1; + u64 o_ro:1; + u64 o_add1:1; + u64 fpa_que:3; + u64 dwb_ichk:9; + u64 dwb_denb:1; + u64 b0_lend:1; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_npi_dma_highp_counts { + u64 u64; + struct cvmx_npi_dma_highp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 fcnt:7; + u64 dbell:32; +#else + u64 dbell:32; + u64 fcnt:7; + u64 reserved_39_63:25; +#endif + } s; +}; + +union cvmx_npi_dma_highp_naddr { + u64 u64; + struct cvmx_npi_dma_highp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 state:4; + u64 addr:36; +#else + u64 addr:36; + u64 state:4; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_npi_dma_lowp_counts { + u64 u64; + struct cvmx_npi_dma_lowp_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 fcnt:7; + u64 dbell:32; +#else + u64 dbell:32; + u64 fcnt:7; + u64 reserved_39_63:25; +#endif + } s; +}; + +union cvmx_npi_dma_lowp_naddr { + u64 u64; + struct cvmx_npi_dma_lowp_naddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 state:4; + u64 addr:36; +#else + u64 addr:36; + u64 state:4; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_npi_highp_dbell { + u64 u64; + struct cvmx_npi_highp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dbell:16; +#else + u64 dbell:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npi_highp_ibuff_saddr { + u64 u64; + struct cvmx_npi_highp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 saddr:36; +#else + u64 saddr:36; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_npi_input_control { + u64 u64; + struct cvmx_npi_input_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 pkt_rr:1; + u64 pbp_dhi:13; + u64 d_nsr:1; + u64 d_esr:2; + u64 d_ror:1; + u64 use_csr:1; + u64 nsr:1; + u64 esr:2; + u64 ror:1; +#else + u64 ror:1; + u64 esr:2; + u64 nsr:1; + u64 use_csr:1; + u64 d_ror:1; + u64 d_esr:2; + u64 d_nsr:1; + u64 pbp_dhi:13; + u64 pkt_rr:1; + u64 reserved_23_63:41; +#endif + } s; + struct cvmx_npi_input_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 pbp_dhi:13; + u64 d_nsr:1; + u64 d_esr:2; + u64 d_ror:1; + u64 use_csr:1; + u64 nsr:1; + u64 esr:2; + u64 ror:1; +#else + u64 ror:1; + u64 esr:2; + u64 nsr:1; + u64 use_csr:1; + u64 d_ror:1; + u64 d_esr:2; + u64 d_nsr:1; + u64 pbp_dhi:13; + u64 reserved_22_63:42; +#endif + } cn30xx; +}; + +union cvmx_npi_int_enb { + u64 u64; + struct cvmx_npi_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 i3_pperr:1; + u64 i2_pperr:1; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 p3_ptout:1; + u64 p2_ptout:1; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 p3_pperr:1; + u64 p2_pperr:1; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 g3_rtout:1; + u64 g2_rtout:1; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 p3_perr:1; + u64 p2_perr:1; + u64 p1_perr:1; + u64 p0_perr:1; + u64 p3_rtout:1; + u64 p2_rtout:1; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 i3_overf:1; + u64 i2_overf:1; + u64 i1_overf:1; + u64 i0_overf:1; + u64 i3_rtout:1; + u64 i2_rtout:1; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 po3_2sml:1; + u64 po2_2sml:1; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 po2_2sml:1; + u64 po3_2sml:1; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 i2_rtout:1; + u64 i3_rtout:1; + u64 i0_overf:1; + u64 i1_overf:1; + u64 i2_overf:1; + u64 i3_overf:1; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 p2_rtout:1; + u64 p3_rtout:1; + u64 p0_perr:1; + u64 p1_perr:1; + u64 p2_perr:1; + u64 p3_perr:1; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 g2_rtout:1; + u64 g3_rtout:1; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 p2_pperr:1; + u64 p3_pperr:1; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 p2_ptout:1; + u64 p3_ptout:1; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 i2_pperr:1; + u64 i3_pperr:1; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } s; + struct cvmx_npi_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 reserved_36_38:3; + u64 i0_pperr:1; + u64 reserved_32_34:3; + u64 p0_ptout:1; + u64 reserved_28_30:3; + u64 p0_pperr:1; + u64 reserved_24_26:3; + u64 g0_rtout:1; + u64 reserved_20_22:3; + u64 p0_perr:1; + u64 reserved_16_18:3; + u64 p0_rtout:1; + u64 reserved_12_14:3; + u64 i0_overf:1; + u64 reserved_8_10:3; + u64 i0_rtout:1; + u64 reserved_4_6:3; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 reserved_4_6:3; + u64 i0_rtout:1; + u64 reserved_8_10:3; + u64 i0_overf:1; + u64 reserved_12_14:3; + u64 p0_rtout:1; + u64 reserved_16_18:3; + u64 p0_perr:1; + u64 reserved_20_22:3; + u64 g0_rtout:1; + u64 reserved_24_26:3; + u64 p0_pperr:1; + u64 reserved_28_30:3; + u64 p0_ptout:1; + u64 reserved_32_34:3; + u64 i0_pperr:1; + u64 reserved_36_38:3; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } cn30xx; + struct cvmx_npi_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 reserved_37_38:2; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 reserved_33_34:2; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 reserved_29_30:2; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 reserved_25_26:2; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 reserved_21_22:2; + u64 p1_perr:1; + u64 p0_perr:1; + u64 reserved_17_18:2; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 reserved_13_14:2; + u64 i1_overf:1; + u64 i0_overf:1; + u64 reserved_9_10:2; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 reserved_5_6:2; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 reserved_5_6:2; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 reserved_9_10:2; + u64 i0_overf:1; + u64 i1_overf:1; + u64 reserved_13_14:2; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 reserved_17_18:2; + u64 p0_perr:1; + u64 p1_perr:1; + u64 reserved_21_22:2; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 reserved_25_26:2; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 reserved_29_30:2; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 reserved_33_34:2; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 reserved_37_38:2; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } cn31xx; + struct cvmx_npi_int_enb_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 i3_pperr:1; + u64 i2_pperr:1; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 p3_ptout:1; + u64 p2_ptout:1; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 p3_pperr:1; + u64 p2_pperr:1; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 g3_rtout:1; + u64 g2_rtout:1; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 p3_perr:1; + u64 p2_perr:1; + u64 p1_perr:1; + u64 p0_perr:1; + u64 p3_rtout:1; + u64 p2_rtout:1; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 i3_overf:1; + u64 i2_overf:1; + u64 i1_overf:1; + u64 i0_overf:1; + u64 i3_rtout:1; + u64 i2_rtout:1; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 po3_2sml:1; + u64 po2_2sml:1; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 po2_2sml:1; + u64 po3_2sml:1; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 i2_rtout:1; + u64 i3_rtout:1; + u64 i0_overf:1; + u64 i1_overf:1; + u64 i2_overf:1; + u64 i3_overf:1; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 p2_rtout:1; + u64 p3_rtout:1; + u64 p0_perr:1; + u64 p1_perr:1; + u64 p2_perr:1; + u64 p3_perr:1; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 g2_rtout:1; + u64 g3_rtout:1; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 p2_pperr:1; + u64 p3_pperr:1; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 p2_ptout:1; + u64 p3_ptout:1; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 i2_pperr:1; + u64 i3_pperr:1; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 reserved_42_63:22; +#endif + } cn38xxp2; +}; + +union cvmx_npi_int_sum { + u64 u64; + struct cvmx_npi_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 i3_pperr:1; + u64 i2_pperr:1; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 p3_ptout:1; + u64 p2_ptout:1; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 p3_pperr:1; + u64 p2_pperr:1; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 g3_rtout:1; + u64 g2_rtout:1; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 p3_perr:1; + u64 p2_perr:1; + u64 p1_perr:1; + u64 p0_perr:1; + u64 p3_rtout:1; + u64 p2_rtout:1; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 i3_overf:1; + u64 i2_overf:1; + u64 i1_overf:1; + u64 i0_overf:1; + u64 i3_rtout:1; + u64 i2_rtout:1; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 po3_2sml:1; + u64 po2_2sml:1; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 po2_2sml:1; + u64 po3_2sml:1; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 i2_rtout:1; + u64 i3_rtout:1; + u64 i0_overf:1; + u64 i1_overf:1; + u64 i2_overf:1; + u64 i3_overf:1; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 p2_rtout:1; + u64 p3_rtout:1; + u64 p0_perr:1; + u64 p1_perr:1; + u64 p2_perr:1; + u64 p3_perr:1; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 g2_rtout:1; + u64 g3_rtout:1; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 p2_pperr:1; + u64 p3_pperr:1; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 p2_ptout:1; + u64 p3_ptout:1; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 i2_pperr:1; + u64 i3_pperr:1; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } s; + struct cvmx_npi_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 reserved_36_38:3; + u64 i0_pperr:1; + u64 reserved_32_34:3; + u64 p0_ptout:1; + u64 reserved_28_30:3; + u64 p0_pperr:1; + u64 reserved_24_26:3; + u64 g0_rtout:1; + u64 reserved_20_22:3; + u64 p0_perr:1; + u64 reserved_16_18:3; + u64 p0_rtout:1; + u64 reserved_12_14:3; + u64 i0_overf:1; + u64 reserved_8_10:3; + u64 i0_rtout:1; + u64 reserved_4_6:3; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 reserved_4_6:3; + u64 i0_rtout:1; + u64 reserved_8_10:3; + u64 i0_overf:1; + u64 reserved_12_14:3; + u64 p0_rtout:1; + u64 reserved_16_18:3; + u64 p0_perr:1; + u64 reserved_20_22:3; + u64 g0_rtout:1; + u64 reserved_24_26:3; + u64 p0_pperr:1; + u64 reserved_28_30:3; + u64 p0_ptout:1; + u64 reserved_32_34:3; + u64 i0_pperr:1; + u64 reserved_36_38:3; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } cn30xx; + struct cvmx_npi_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 q1_a_f:1; + u64 q1_s_e:1; + u64 pdf_p_f:1; + u64 pdf_p_e:1; + u64 pcf_p_f:1; + u64 pcf_p_e:1; + u64 rdx_s_e:1; + u64 rwx_s_e:1; + u64 pnc_a_f:1; + u64 pnc_s_e:1; + u64 com_a_f:1; + u64 com_s_e:1; + u64 q3_a_f:1; + u64 q3_s_e:1; + u64 q2_a_f:1; + u64 q2_s_e:1; + u64 pcr_a_f:1; + u64 pcr_s_e:1; + u64 fcr_a_f:1; + u64 fcr_s_e:1; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 reserved_37_38:2; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 reserved_33_34:2; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 reserved_29_30:2; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 reserved_25_26:2; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 reserved_21_22:2; + u64 p1_perr:1; + u64 p0_perr:1; + u64 reserved_17_18:2; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 reserved_13_14:2; + u64 i1_overf:1; + u64 i0_overf:1; + u64 reserved_9_10:2; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 reserved_5_6:2; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 reserved_5_6:2; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 reserved_9_10:2; + u64 i0_overf:1; + u64 i1_overf:1; + u64 reserved_13_14:2; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 reserved_17_18:2; + u64 p0_perr:1; + u64 p1_perr:1; + u64 reserved_21_22:2; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 reserved_25_26:2; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 reserved_29_30:2; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 reserved_33_34:2; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 reserved_37_38:2; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 fcr_s_e:1; + u64 fcr_a_f:1; + u64 pcr_s_e:1; + u64 pcr_a_f:1; + u64 q2_s_e:1; + u64 q2_a_f:1; + u64 q3_s_e:1; + u64 q3_a_f:1; + u64 com_s_e:1; + u64 com_a_f:1; + u64 pnc_s_e:1; + u64 pnc_a_f:1; + u64 rwx_s_e:1; + u64 rdx_s_e:1; + u64 pcf_p_e:1; + u64 pcf_p_f:1; + u64 pdf_p_e:1; + u64 pdf_p_f:1; + u64 q1_s_e:1; + u64 q1_a_f:1; + u64 reserved_62_63:2; +#endif + } cn31xx; + struct cvmx_npi_int_sum_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 iobdma:1; + u64 p_dperr:1; + u64 win_rto:1; + u64 i3_pperr:1; + u64 i2_pperr:1; + u64 i1_pperr:1; + u64 i0_pperr:1; + u64 p3_ptout:1; + u64 p2_ptout:1; + u64 p1_ptout:1; + u64 p0_ptout:1; + u64 p3_pperr:1; + u64 p2_pperr:1; + u64 p1_pperr:1; + u64 p0_pperr:1; + u64 g3_rtout:1; + u64 g2_rtout:1; + u64 g1_rtout:1; + u64 g0_rtout:1; + u64 p3_perr:1; + u64 p2_perr:1; + u64 p1_perr:1; + u64 p0_perr:1; + u64 p3_rtout:1; + u64 p2_rtout:1; + u64 p1_rtout:1; + u64 p0_rtout:1; + u64 i3_overf:1; + u64 i2_overf:1; + u64 i1_overf:1; + u64 i0_overf:1; + u64 i3_rtout:1; + u64 i2_rtout:1; + u64 i1_rtout:1; + u64 i0_rtout:1; + u64 po3_2sml:1; + u64 po2_2sml:1; + u64 po1_2sml:1; + u64 po0_2sml:1; + u64 pci_rsl:1; + u64 rml_wto:1; + u64 rml_rto:1; +#else + u64 rml_rto:1; + u64 rml_wto:1; + u64 pci_rsl:1; + u64 po0_2sml:1; + u64 po1_2sml:1; + u64 po2_2sml:1; + u64 po3_2sml:1; + u64 i0_rtout:1; + u64 i1_rtout:1; + u64 i2_rtout:1; + u64 i3_rtout:1; + u64 i0_overf:1; + u64 i1_overf:1; + u64 i2_overf:1; + u64 i3_overf:1; + u64 p0_rtout:1; + u64 p1_rtout:1; + u64 p2_rtout:1; + u64 p3_rtout:1; + u64 p0_perr:1; + u64 p1_perr:1; + u64 p2_perr:1; + u64 p3_perr:1; + u64 g0_rtout:1; + u64 g1_rtout:1; + u64 g2_rtout:1; + u64 g3_rtout:1; + u64 p0_pperr:1; + u64 p1_pperr:1; + u64 p2_pperr:1; + u64 p3_pperr:1; + u64 p0_ptout:1; + u64 p1_ptout:1; + u64 p2_ptout:1; + u64 p3_ptout:1; + u64 i0_pperr:1; + u64 i1_pperr:1; + u64 i2_pperr:1; + u64 i3_pperr:1; + u64 win_rto:1; + u64 p_dperr:1; + u64 iobdma:1; + u64 reserved_42_63:22; +#endif + } cn38xxp2; +}; + +union cvmx_npi_lowp_dbell { + u64 u64; + struct cvmx_npi_lowp_dbell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dbell:16; +#else + u64 dbell:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_npi_lowp_ibuff_saddr { + u64 u64; + struct cvmx_npi_lowp_ibuff_saddr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 saddr:36; +#else + u64 saddr:36; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_npi_mem_access_subidx { + u64 u64; + struct cvmx_npi_mem_access_subidx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 shortl:1; + u64 nmerge:1; + u64 esr:2; + u64 esw:2; + u64 nsr:1; + u64 nsw:1; + u64 ror:1; + u64 row:1; + u64 ba:28; +#else + u64 ba:28; + u64 row:1; + u64 ror:1; + u64 nsw:1; + u64 nsr:1; + u64 esw:2; + u64 esr:2; + u64 nmerge:1; + u64 shortl:1; + u64 reserved_38_63:26; +#endif + } s; + struct cvmx_npi_mem_access_subidx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 esr:2; + u64 esw:2; + u64 nsr:1; + u64 nsw:1; + u64 ror:1; + u64 row:1; + u64 ba:28; +#else + u64 ba:28; + u64 row:1; + u64 ror:1; + u64 nsw:1; + u64 nsr:1; + u64 esw:2; + u64 esr:2; + u64 reserved_36_63:28; +#endif + } cn31xx; +}; + +union cvmx_npi_msi_rcv { + u64 u64; + struct cvmx_npi_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 int_vec:64; +#else + u64 int_vec:64; +#endif + } s; +}; + +union cvmx_npi_num_desc_outputx { + u64 u64; + struct cvmx_npi_num_desc_outputx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 size:32; +#else + u64 size:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npi_output_control { + u64 u64; + struct cvmx_npi_output_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 pkt_rr:1; + u64 p3_bmode:1; + u64 p2_bmode:1; + u64 p1_bmode:1; + u64 p0_bmode:1; + u64 o3_es:2; + u64 o3_ns:1; + u64 o3_ro:1; + u64 o2_es:2; + u64 o2_ns:1; + u64 o2_ro:1; + u64 o1_es:2; + u64 o1_ns:1; + u64 o1_ro:1; + u64 o0_es:2; + u64 o0_ns:1; + u64 o0_ro:1; + u64 o3_csrm:1; + u64 o2_csrm:1; + u64 o1_csrm:1; + u64 o0_csrm:1; + u64 reserved_20_23:4; + u64 iptr_o3:1; + u64 iptr_o2:1; + u64 iptr_o1:1; + u64 iptr_o0:1; + u64 esr_sl3:2; + u64 nsr_sl3:1; + u64 ror_sl3:1; + u64 esr_sl2:2; + u64 nsr_sl2:1; + u64 ror_sl2:1; + u64 esr_sl1:2; + u64 nsr_sl1:1; + u64 ror_sl1:1; + u64 esr_sl0:2; + u64 nsr_sl0:1; + u64 ror_sl0:1; +#else + u64 ror_sl0:1; + u64 nsr_sl0:1; + u64 esr_sl0:2; + u64 ror_sl1:1; + u64 nsr_sl1:1; + u64 esr_sl1:2; + u64 ror_sl2:1; + u64 nsr_sl2:1; + u64 esr_sl2:2; + u64 ror_sl3:1; + u64 nsr_sl3:1; + u64 esr_sl3:2; + u64 iptr_o0:1; + u64 iptr_o1:1; + u64 iptr_o2:1; + u64 iptr_o3:1; + u64 reserved_20_23:4; + u64 o0_csrm:1; + u64 o1_csrm:1; + u64 o2_csrm:1; + u64 o3_csrm:1; + u64 o0_ro:1; + u64 o0_ns:1; + u64 o0_es:2; + u64 o1_ro:1; + u64 o1_ns:1; + u64 o1_es:2; + u64 o2_ro:1; + u64 o2_ns:1; + u64 o2_es:2; + u64 o3_ro:1; + u64 o3_ns:1; + u64 o3_es:2; + u64 p0_bmode:1; + u64 p1_bmode:1; + u64 p2_bmode:1; + u64 p3_bmode:1; + u64 pkt_rr:1; + u64 reserved_49_63:15; +#endif + } s; + struct cvmx_npi_output_control_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 p0_bmode:1; + u64 reserved_32_43:12; + u64 o0_es:2; + u64 o0_ns:1; + u64 o0_ro:1; + u64 reserved_25_27:3; + u64 o0_csrm:1; + u64 reserved_17_23:7; + u64 iptr_o0:1; + u64 reserved_4_15:12; + u64 esr_sl0:2; + u64 nsr_sl0:1; + u64 ror_sl0:1; +#else + u64 ror_sl0:1; + u64 nsr_sl0:1; + u64 esr_sl0:2; + u64 reserved_4_15:12; + u64 iptr_o0:1; + u64 reserved_17_23:7; + u64 o0_csrm:1; + u64 reserved_25_27:3; + u64 o0_ro:1; + u64 o0_ns:1; + u64 o0_es:2; + u64 reserved_32_43:12; + u64 p0_bmode:1; + u64 reserved_45_63:19; +#endif + } cn30xx; + struct cvmx_npi_output_control_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 p1_bmode:1; + u64 p0_bmode:1; + u64 reserved_36_43:8; + u64 o1_es:2; + u64 o1_ns:1; + u64 o1_ro:1; + u64 o0_es:2; + u64 o0_ns:1; + u64 o0_ro:1; + u64 reserved_26_27:2; + u64 o1_csrm:1; + u64 o0_csrm:1; + u64 reserved_18_23:6; + u64 iptr_o1:1; + u64 iptr_o0:1; + u64 reserved_8_15:8; + u64 esr_sl1:2; + u64 nsr_sl1:1; + u64 ror_sl1:1; + u64 esr_sl0:2; + u64 nsr_sl0:1; + u64 ror_sl0:1; +#else + u64 ror_sl0:1; + u64 nsr_sl0:1; + u64 esr_sl0:2; + u64 ror_sl1:1; + u64 nsr_sl1:1; + u64 esr_sl1:2; + u64 reserved_8_15:8; + u64 iptr_o0:1; + u64 iptr_o1:1; + u64 reserved_18_23:6; + u64 o0_csrm:1; + u64 o1_csrm:1; + u64 reserved_26_27:2; + u64 o0_ro:1; + u64 o0_ns:1; + u64 o0_es:2; + u64 o1_ro:1; + u64 o1_ns:1; + u64 o1_es:2; + u64 reserved_36_43:8; + u64 p0_bmode:1; + u64 p1_bmode:1; + u64 reserved_46_63:18; +#endif + } cn31xx; + struct cvmx_npi_output_control_cn38xxp2 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 p3_bmode:1; + u64 p2_bmode:1; + u64 p1_bmode:1; + u64 p0_bmode:1; + u64 o3_es:2; + u64 o3_ns:1; + u64 o3_ro:1; + u64 o2_es:2; + u64 o2_ns:1; + u64 o2_ro:1; + u64 o1_es:2; + u64 o1_ns:1; + u64 o1_ro:1; + u64 o0_es:2; + u64 o0_ns:1; + u64 o0_ro:1; + u64 o3_csrm:1; + u64 o2_csrm:1; + u64 o1_csrm:1; + u64 o0_csrm:1; + u64 reserved_20_23:4; + u64 iptr_o3:1; + u64 iptr_o2:1; + u64 iptr_o1:1; + u64 iptr_o0:1; + u64 esr_sl3:2; + u64 nsr_sl3:1; + u64 ror_sl3:1; + u64 esr_sl2:2; + u64 nsr_sl2:1; + u64 ror_sl2:1; + u64 esr_sl1:2; + u64 nsr_sl1:1; + u64 ror_sl1:1; + u64 esr_sl0:2; + u64 nsr_sl0:1; + u64 ror_sl0:1; +#else + u64 ror_sl0:1; + u64 nsr_sl0:1; + u64 esr_sl0:2; + u64 ror_sl1:1; + u64 nsr_sl1:1; + u64 esr_sl1:2; + u64 ror_sl2:1; + u64 nsr_sl2:1; + u64 esr_sl2:2; + u64 ror_sl3:1; + u64 nsr_sl3:1; + u64 esr_sl3:2; + u64 iptr_o0:1; + u64 iptr_o1:1; + u64 iptr_o2:1; + u64 iptr_o3:1; + u64 reserved_20_23:4; + u64 o0_csrm:1; + u64 o1_csrm:1; + u64 o2_csrm:1; + u64 o3_csrm:1; + u64 o0_ro:1; + u64 o0_ns:1; + u64 o0_es:2; + u64 o1_ro:1; + u64 o1_ns:1; + u64 o1_es:2; + u64 o2_ro:1; + u64 o2_ns:1; + u64 o2_es:2; + u64 o3_ro:1; + u64 o3_ns:1; + u64 o3_es:2; + u64 p0_bmode:1; + u64 p1_bmode:1; + u64 p2_bmode:1; + u64 p3_bmode:1; + u64 reserved_48_63:16; +#endif + } cn38xxp2; + struct cvmx_npi_output_control_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 pkt_rr:1; + u64 reserved_46_47:2; + u64 p1_bmode:1; + u64 p0_bmode:1; + u64 reserved_36_43:8; + u64 o1_es:2; + u64 o1_ns:1; + u64 o1_ro:1; + u64 o0_es:2; + u64 o0_ns:1; + u64 o0_ro:1; + u64 reserved_26_27:2; + u64 o1_csrm:1; + u64 o0_csrm:1; + u64 reserved_18_23:6; + u64 iptr_o1:1; + u64 iptr_o0:1; + u64 reserved_8_15:8; + u64 esr_sl1:2; + u64 nsr_sl1:1; + u64 ror_sl1:1; + u64 esr_sl0:2; + u64 nsr_sl0:1; + u64 ror_sl0:1; +#else + u64 ror_sl0:1; + u64 nsr_sl0:1; + u64 esr_sl0:2; + u64 ror_sl1:1; + u64 nsr_sl1:1; + u64 esr_sl1:2; + u64 reserved_8_15:8; + u64 iptr_o0:1; + u64 iptr_o1:1; + u64 reserved_18_23:6; + u64 o0_csrm:1; + u64 o1_csrm:1; + u64 reserved_26_27:2; + u64 o0_ro:1; + u64 o0_ns:1; + u64 o0_es:2; + u64 o1_ro:1; + u64 o1_ns:1; + u64 o1_es:2; + u64 reserved_36_43:8; + u64 p0_bmode:1; + u64 p1_bmode:1; + u64 reserved_46_47:2; + u64 pkt_rr:1; + u64 reserved_49_63:15; +#endif + } cn50xx; +}; + +union cvmx_npi_px_dbpair_addr { + u64 u64; + struct cvmx_npi_px_dbpair_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 state:2; + u64 naddr:61; +#else + u64 naddr:61; + u64 state:2; + u64 reserved_63_63:1; +#endif + } s; +}; + +union cvmx_npi_px_instr_addr { + u64 u64; + struct cvmx_npi_px_instr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 state:3; + u64 naddr:61; +#else + u64 naddr:61; + u64 state:3; +#endif + } s; +}; + +union cvmx_npi_px_instr_cnts { + u64 u64; + struct cvmx_npi_px_instr_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 fcnt:6; + u64 avail:32; +#else + u64 avail:32; + u64 fcnt:6; + u64 reserved_38_63:26; +#endif + } s; +}; + +union cvmx_npi_px_pair_cnts { + u64 u64; + struct cvmx_npi_px_pair_cnts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 fcnt:5; + u64 avail:32; +#else + u64 avail:32; + u64 fcnt:5; + u64 reserved_37_63:27; +#endif + } s; +}; + +union cvmx_npi_pci_burst_size { + u64 u64; + struct cvmx_npi_pci_burst_size_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 wr_brst:7; + u64 rd_brst:7; +#else + u64 rd_brst:7; + u64 wr_brst:7; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_npi_pci_int_arb_cfg { + u64 u64; + struct cvmx_npi_pci_int_arb_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 hostmode:1; + u64 pci_ovr:4; + u64 reserved_5_7:3; + u64 en:1; + u64 park_mod:1; + u64 park_dev:3; +#else + u64 park_dev:3; + u64 park_mod:1; + u64 en:1; + u64 reserved_5_7:3; + u64 pci_ovr:4; + u64 hostmode:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_npi_pci_int_arb_cfg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 en:1; + u64 park_mod:1; + u64 park_dev:3; +#else + u64 park_dev:3; + u64 park_mod:1; + u64 en:1; + u64 reserved_5_63:59; +#endif + } cn30xx; +}; + +union cvmx_npi_pci_read_cmd { + u64 u64; + struct cvmx_npi_pci_read_cmd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 cmd_size:11; +#else + u64 cmd_size:11; + u64 reserved_11_63:53; +#endif + } s; +}; + +union cvmx_npi_port32_instr_hdr { + u64 u64; + struct cvmx_npi_port32_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 pbp:1; + u64 rsv_f:5; + u64 rparmode:2; + u64 rsv_e:1; + u64 rskp_len:7; + u64 rsv_d:6; + u64 use_ihdr:1; + u64 rsv_c:5; + u64 par_mode:2; + u64 rsv_b:1; + u64 skp_len:7; + u64 rsv_a:6; +#else + u64 rsv_a:6; + u64 skp_len:7; + u64 rsv_b:1; + u64 par_mode:2; + u64 rsv_c:5; + u64 use_ihdr:1; + u64 rsv_d:6; + u64 rskp_len:7; + u64 rsv_e:1; + u64 rparmode:2; + u64 rsv_f:5; + u64 pbp:1; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npi_port33_instr_hdr { + u64 u64; + struct cvmx_npi_port33_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 pbp:1; + u64 rsv_f:5; + u64 rparmode:2; + u64 rsv_e:1; + u64 rskp_len:7; + u64 rsv_d:6; + u64 use_ihdr:1; + u64 rsv_c:5; + u64 par_mode:2; + u64 rsv_b:1; + u64 skp_len:7; + u64 rsv_a:6; +#else + u64 rsv_a:6; + u64 skp_len:7; + u64 rsv_b:1; + u64 par_mode:2; + u64 rsv_c:5; + u64 use_ihdr:1; + u64 rsv_d:6; + u64 rskp_len:7; + u64 rsv_e:1; + u64 rparmode:2; + u64 rsv_f:5; + u64 pbp:1; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npi_port34_instr_hdr { + u64 u64; + struct cvmx_npi_port34_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 pbp:1; + u64 rsv_f:5; + u64 rparmode:2; + u64 rsv_e:1; + u64 rskp_len:7; + u64 rsv_d:6; + u64 use_ihdr:1; + u64 rsv_c:5; + u64 par_mode:2; + u64 rsv_b:1; + u64 skp_len:7; + u64 rsv_a:6; +#else + u64 rsv_a:6; + u64 skp_len:7; + u64 rsv_b:1; + u64 par_mode:2; + u64 rsv_c:5; + u64 use_ihdr:1; + u64 rsv_d:6; + u64 rskp_len:7; + u64 rsv_e:1; + u64 rparmode:2; + u64 rsv_f:5; + u64 pbp:1; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npi_port35_instr_hdr { + u64 u64; + struct cvmx_npi_port35_instr_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 pbp:1; + u64 rsv_f:5; + u64 rparmode:2; + u64 rsv_e:1; + u64 rskp_len:7; + u64 rsv_d:6; + u64 use_ihdr:1; + u64 rsv_c:5; + u64 par_mode:2; + u64 rsv_b:1; + u64 skp_len:7; + u64 rsv_a:6; +#else + u64 rsv_a:6; + u64 skp_len:7; + u64 rsv_b:1; + u64 par_mode:2; + u64 rsv_c:5; + u64 use_ihdr:1; + u64 rsv_d:6; + u64 rskp_len:7; + u64 rsv_e:1; + u64 rparmode:2; + u64 rsv_f:5; + u64 pbp:1; + u64 reserved_44_63:20; +#endif + } s; +}; + +union cvmx_npi_port_bp_control { + u64 u64; + struct cvmx_npi_port_bp_control_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 bp_on:4; + u64 enb:4; +#else + u64 enb:4; + u64 bp_on:4; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_npi_rsl_int_blocks { + u64 u64; + struct cvmx_npi_rsl_int_blocks_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rint_31:1; + u64 iob:1; + u64 reserved_28_29:2; + u64 rint_27:1; + u64 rint_26:1; + u64 rint_25:1; + u64 rint_24:1; + u64 asx1:1; + u64 asx0:1; + u64 rint_21:1; + u64 pip:1; + u64 spx1:1; + u64 spx0:1; + u64 lmc:1; + u64 l2c:1; + u64 rint_15:1; + u64 reserved_13_14:2; + u64 pow:1; + u64 tim:1; + u64 pko:1; + u64 ipd:1; + u64 rint_8:1; + u64 zip:1; + u64 dfa:1; + u64 fpa:1; + u64 key:1; + u64 npi:1; + u64 gmx1:1; + u64 gmx0:1; + u64 mio:1; +#else + u64 mio:1; + u64 gmx0:1; + u64 gmx1:1; + u64 npi:1; + u64 key:1; + u64 fpa:1; + u64 dfa:1; + u64 zip:1; + u64 rint_8:1; + u64 ipd:1; + u64 pko:1; + u64 tim:1; + u64 pow:1; + u64 reserved_13_14:2; + u64 rint_15:1; + u64 l2c:1; + u64 lmc:1; + u64 spx0:1; + u64 spx1:1; + u64 pip:1; + u64 rint_21:1; + u64 asx0:1; + u64 asx1:1; + u64 rint_24:1; + u64 rint_25:1; + u64 rint_26:1; + u64 rint_27:1; + u64 reserved_28_29:2; + u64 iob:1; + u64 rint_31:1; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_npi_rsl_int_blocks_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rint_31:1; + u64 iob:1; + u64 rint_29:1; + u64 rint_28:1; + u64 rint_27:1; + u64 rint_26:1; + u64 rint_25:1; + u64 rint_24:1; + u64 asx1:1; + u64 asx0:1; + u64 rint_21:1; + u64 pip:1; + u64 spx1:1; + u64 spx0:1; + u64 lmc:1; + u64 l2c:1; + u64 rint_15:1; + u64 rint_14:1; + u64 usb:1; + u64 pow:1; + u64 tim:1; + u64 pko:1; + u64 ipd:1; + u64 rint_8:1; + u64 zip:1; + u64 dfa:1; + u64 fpa:1; + u64 key:1; + u64 npi:1; + u64 gmx1:1; + u64 gmx0:1; + u64 mio:1; +#else + u64 mio:1; + u64 gmx0:1; + u64 gmx1:1; + u64 npi:1; + u64 key:1; + u64 fpa:1; + u64 dfa:1; + u64 zip:1; + u64 rint_8:1; + u64 ipd:1; + u64 pko:1; + u64 tim:1; + u64 pow:1; + u64 usb:1; + u64 rint_14:1; + u64 rint_15:1; + u64 l2c:1; + u64 lmc:1; + u64 spx0:1; + u64 spx1:1; + u64 pip:1; + u64 rint_21:1; + u64 asx0:1; + u64 asx1:1; + u64 rint_24:1; + u64 rint_25:1; + u64 rint_26:1; + u64 rint_27:1; + u64 rint_28:1; + u64 rint_29:1; + u64 iob:1; + u64 rint_31:1; + u64 reserved_32_63:32; +#endif + } cn30xx; + struct cvmx_npi_rsl_int_blocks_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rint_31:1; + u64 iob:1; + u64 rint_29:1; + u64 rint_28:1; + u64 rint_27:1; + u64 rint_26:1; + u64 rint_25:1; + u64 rint_24:1; + u64 asx1:1; + u64 asx0:1; + u64 rint_21:1; + u64 pip:1; + u64 spx1:1; + u64 spx0:1; + u64 lmc:1; + u64 l2c:1; + u64 rint_15:1; + u64 rint_14:1; + u64 rint_13:1; + u64 pow:1; + u64 tim:1; + u64 pko:1; + u64 ipd:1; + u64 rint_8:1; + u64 zip:1; + u64 dfa:1; + u64 fpa:1; + u64 key:1; + u64 npi:1; + u64 gmx1:1; + u64 gmx0:1; + u64 mio:1; +#else + u64 mio:1; + u64 gmx0:1; + u64 gmx1:1; + u64 npi:1; + u64 key:1; + u64 fpa:1; + u64 dfa:1; + u64 zip:1; + u64 rint_8:1; + u64 ipd:1; + u64 pko:1; + u64 tim:1; + u64 pow:1; + u64 rint_13:1; + u64 rint_14:1; + u64 rint_15:1; + u64 l2c:1; + u64 lmc:1; + u64 spx0:1; + u64 spx1:1; + u64 pip:1; + u64 rint_21:1; + u64 asx0:1; + u64 asx1:1; + u64 rint_24:1; + u64 rint_25:1; + u64 rint_26:1; + u64 rint_27:1; + u64 rint_28:1; + u64 rint_29:1; + u64 iob:1; + u64 rint_31:1; + u64 reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_npi_rsl_int_blocks_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 iob:1; + u64 lmc1:1; + u64 agl:1; + u64 reserved_24_27:4; + u64 asx1:1; + u64 asx0:1; + u64 reserved_21_21:1; + u64 pip:1; + u64 spx1:1; + u64 spx0:1; + u64 lmc:1; + u64 l2c:1; + u64 reserved_15_15:1; + u64 rad:1; + u64 usb:1; + u64 pow:1; + u64 tim:1; + u64 pko:1; + u64 ipd:1; + u64 reserved_8_8:1; + u64 zip:1; + u64 dfa:1; + u64 fpa:1; + u64 key:1; + u64 npi:1; + u64 gmx1:1; + u64 gmx0:1; + u64 mio:1; +#else + u64 mio:1; + u64 gmx0:1; + u64 gmx1:1; + u64 npi:1; + u64 key:1; + u64 fpa:1; + u64 dfa:1; + u64 zip:1; + u64 reserved_8_8:1; + u64 ipd:1; + u64 pko:1; + u64 tim:1; + u64 pow:1; + u64 usb:1; + u64 rad:1; + u64 reserved_15_15:1; + u64 l2c:1; + u64 lmc:1; + u64 spx0:1; + u64 spx1:1; + u64 pip:1; + u64 reserved_21_21:1; + u64 asx0:1; + u64 asx1:1; + u64 reserved_24_27:4; + u64 agl:1; + u64 lmc1:1; + u64 iob:1; + u64 reserved_31_63:33; +#endif + } cn50xx; +}; + +union cvmx_npi_size_inputx { + u64 u64; + struct cvmx_npi_size_inputx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 size:32; +#else + u64 size:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_npi_win_read_to { + u64 u64; + struct cvmx_npi_win_read_to_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 time:32; +#else + u64 time:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h new file mode 100644 index 000000000000..602ddf84f958 --- /dev/null +++ b/drivers/staging/octeon/cvmx-packet.h @@ -0,0 +1,68 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Packet buffer defines. + */ + +#ifndef __CVMX_PACKET_H__ +#define __CVMX_PACKET_H__ + +/** + * This structure defines a buffer pointer on Octeon + */ +union cvmx_buf_ptr { + void *ptr; + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* if set, invert the "free" pick of the overall + * packet. HW always sets this bit to 0 on inbound + * packet */ + u64 i:1; + + /* Indicates the amount to back up to get to the + * buffer start in cache lines. In most cases this is + * less than one complete cache line, so the value is + * zero */ + u64 back:4; + /* The pool that the buffer came from / goes to */ + u64 pool:3; + /* The size of the segment pointed to by addr (in bytes) */ + u64 size:16; + /* Pointer to the first byte of the data, NOT buffer */ + u64 addr:40; +#else + u64 addr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } s; +}; + +#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-pci-defs.h b/drivers/staging/octeon/cvmx-pci-defs.h new file mode 100644 index 000000000000..7d2bd6d8b9c5 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pci-defs.h @@ -0,0 +1,2036 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCI_DEFS_H__ +#define __CVMX_PCI_DEFS_H__ + +#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) +#define CVMX_PCI_BIST_REG (0x00000000000001C0ull) +#define CVMX_PCI_CFG00 (0x0000000000000000ull) +#define CVMX_PCI_CFG01 (0x0000000000000004ull) +#define CVMX_PCI_CFG02 (0x0000000000000008ull) +#define CVMX_PCI_CFG03 (0x000000000000000Cull) +#define CVMX_PCI_CFG04 (0x0000000000000010ull) +#define CVMX_PCI_CFG05 (0x0000000000000014ull) +#define CVMX_PCI_CFG06 (0x0000000000000018ull) +#define CVMX_PCI_CFG07 (0x000000000000001Cull) +#define CVMX_PCI_CFG08 (0x0000000000000020ull) +#define CVMX_PCI_CFG09 (0x0000000000000024ull) +#define CVMX_PCI_CFG10 (0x0000000000000028ull) +#define CVMX_PCI_CFG11 (0x000000000000002Cull) +#define CVMX_PCI_CFG12 (0x0000000000000030ull) +#define CVMX_PCI_CFG13 (0x0000000000000034ull) +#define CVMX_PCI_CFG15 (0x000000000000003Cull) +#define CVMX_PCI_CFG16 (0x0000000000000040ull) +#define CVMX_PCI_CFG17 (0x0000000000000044ull) +#define CVMX_PCI_CFG18 (0x0000000000000048ull) +#define CVMX_PCI_CFG19 (0x000000000000004Cull) +#define CVMX_PCI_CFG20 (0x0000000000000050ull) +#define CVMX_PCI_CFG21 (0x0000000000000054ull) +#define CVMX_PCI_CFG22 (0x0000000000000058ull) +#define CVMX_PCI_CFG56 (0x00000000000000E0ull) +#define CVMX_PCI_CFG57 (0x00000000000000E4ull) +#define CVMX_PCI_CFG58 (0x00000000000000E8ull) +#define CVMX_PCI_CFG59 (0x00000000000000ECull) +#define CVMX_PCI_CFG60 (0x00000000000000F0ull) +#define CVMX_PCI_CFG61 (0x00000000000000F4ull) +#define CVMX_PCI_CFG62 (0x00000000000000F8ull) +#define CVMX_PCI_CFG63 (0x00000000000000FCull) +#define CVMX_PCI_CNT_REG (0x00000000000001B8ull) +#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) +#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) +#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) +#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) +#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) +#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) +#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) +#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) +#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) +#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) +#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) +#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) +#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) +#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) +#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) +#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) +#define CVMX_PCI_INT_ENB (0x0000000000000038ull) +#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) +#define CVMX_PCI_INT_SUM (0x0000000000000030ull) +#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) +#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) +#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) +#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) +#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) +#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) +#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) +#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) +#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) +#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) +#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) +#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) +#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) +#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) +#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) +#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) +#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) +#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) +#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) +#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) +#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) +#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) +#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) +#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) +#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) +#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) +#define CVMX_PCI_SCM_REG (0x00000000000001A8ull) +#define CVMX_PCI_TSR_REG (0x00000000000001B0ull) +#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) +#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) +#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) +#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) +#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) + +union cvmx_pci_bar1_indexx { + u32 u32; + struct cvmx_pci_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_18_31:14; + u32 addr_idx:14; + u32 ca:1; + u32 end_swp:2; + u32 addr_v:1; +#else + u32 addr_v:1; + u32 end_swp:2; + u32 ca:1; + u32 addr_idx:14; + u32 reserved_18_31:14; +#endif + } s; +}; + +union cvmx_pci_bist_reg { + u64 u64; + struct cvmx_pci_bist_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 rsp_bs:1; + u64 dma0_bs:1; + u64 cmd0_bs:1; + u64 cmd_bs:1; + u64 csr2p_bs:1; + u64 csrr_bs:1; + u64 rsp2p_bs:1; + u64 csr2n_bs:1; + u64 dat2n_bs:1; + u64 dbg2n_bs:1; +#else + u64 dbg2n_bs:1; + u64 dat2n_bs:1; + u64 csr2n_bs:1; + u64 rsp2p_bs:1; + u64 csrr_bs:1; + u64 csr2p_bs:1; + u64 cmd_bs:1; + u64 cmd0_bs:1; + u64 dma0_bs:1; + u64 rsp_bs:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_pci_cfg00 { + u32 u32; + struct cvmx_pci_cfg00_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 devid:16; + u32 vendid:16; +#else + u32 vendid:16; + u32 devid:16; +#endif + } s; +}; + +union cvmx_pci_cfg01 { + u32 u32; + struct cvmx_pci_cfg01_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 dpe:1; + u32 sse:1; + u32 rma:1; + u32 rta:1; + u32 sta:1; + u32 devt:2; + u32 mdpe:1; + u32 fbb:1; + u32 reserved_22_22:1; + u32 m66:1; + u32 cle:1; + u32 i_stat:1; + u32 reserved_11_18:8; + u32 i_dis:1; + u32 fbbe:1; + u32 see:1; + u32 ads:1; + u32 pee:1; + u32 vps:1; + u32 mwice:1; + u32 scse:1; + u32 me:1; + u32 msae:1; + u32 isae:1; +#else + u32 isae:1; + u32 msae:1; + u32 me:1; + u32 scse:1; + u32 mwice:1; + u32 vps:1; + u32 pee:1; + u32 ads:1; + u32 see:1; + u32 fbbe:1; + u32 i_dis:1; + u32 reserved_11_18:8; + u32 i_stat:1; + u32 cle:1; + u32 m66:1; + u32 reserved_22_22:1; + u32 fbb:1; + u32 mdpe:1; + u32 devt:2; + u32 sta:1; + u32 rta:1; + u32 rma:1; + u32 sse:1; + u32 dpe:1; +#endif + } s; +}; + +union cvmx_pci_cfg02 { + u32 u32; + struct cvmx_pci_cfg02_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 cc:24; + u32 rid:8; +#else + u32 rid:8; + u32 cc:24; +#endif + } s; +}; + +union cvmx_pci_cfg03 { + u32 u32; + struct cvmx_pci_cfg03_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 bcap:1; + u32 brb:1; + u32 reserved_28_29:2; + u32 bcod:4; + u32 ht:8; + u32 lt:8; + u32 cls:8; +#else + u32 cls:8; + u32 lt:8; + u32 ht:8; + u32 bcod:4; + u32 reserved_28_29:2; + u32 brb:1; + u32 bcap:1; +#endif + } s; +}; + +union cvmx_pci_cfg04 { + u32 u32; + struct cvmx_pci_cfg04_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 lbase:20; + u32 lbasez:8; + u32 pf:1; + u32 typ:2; + u32 mspc:1; +#else + u32 mspc:1; + u32 typ:2; + u32 pf:1; + u32 lbasez:8; + u32 lbase:20; +#endif + } s; +}; + +union cvmx_pci_cfg05 { + u32 u32; + struct cvmx_pci_cfg05_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 hbase:32; +#else + u32 hbase:32; +#endif + } s; +}; + +union cvmx_pci_cfg06 { + u32 u32; + struct cvmx_pci_cfg06_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 lbase:5; + u32 lbasez:23; + u32 pf:1; + u32 typ:2; + u32 mspc:1; +#else + u32 mspc:1; + u32 typ:2; + u32 pf:1; + u32 lbasez:23; + u32 lbase:5; +#endif + } s; +}; + +union cvmx_pci_cfg07 { + u32 u32; + struct cvmx_pci_cfg07_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 hbase:32; +#else + u32 hbase:32; +#endif + } s; +}; + +union cvmx_pci_cfg08 { + u32 u32; + struct cvmx_pci_cfg08_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 lbasez:28; + u32 pf:1; + u32 typ:2; + u32 mspc:1; +#else + u32 mspc:1; + u32 typ:2; + u32 pf:1; + u32 lbasez:28; +#endif + } s; +}; + +union cvmx_pci_cfg09 { + u32 u32; + struct cvmx_pci_cfg09_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 hbase:25; + u32 hbasez:7; +#else + u32 hbasez:7; + u32 hbase:25; +#endif + } s; +}; + +union cvmx_pci_cfg10 { + u32 u32; + struct cvmx_pci_cfg10_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 cisp:32; +#else + u32 cisp:32; +#endif + } s; +}; + +union cvmx_pci_cfg11 { + u32 u32; + struct cvmx_pci_cfg11_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 ssid:16; + u32 ssvid:16; +#else + u32 ssvid:16; + u32 ssid:16; +#endif + } s; +}; + +union cvmx_pci_cfg12 { + u32 u32; + struct cvmx_pci_cfg12_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 erbar:16; + u32 erbarz:5; + u32 reserved_1_10:10; + u32 erbar_en:1; +#else + u32 erbar_en:1; + u32 reserved_1_10:10; + u32 erbarz:5; + u32 erbar:16; +#endif + } s; +}; + +union cvmx_pci_cfg13 { + u32 u32; + struct cvmx_pci_cfg13_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_8_31:24; + u32 cp:8; +#else + u32 cp:8; + u32 reserved_8_31:24; +#endif + } s; +}; + +union cvmx_pci_cfg15 { + u32 u32; + struct cvmx_pci_cfg15_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 ml:8; + u32 mg:8; + u32 inta:8; + u32 il:8; +#else + u32 il:8; + u32 inta:8; + u32 mg:8; + u32 ml:8; +#endif + } s; +}; + +union cvmx_pci_cfg16 { + u32 u32; + struct cvmx_pci_cfg16_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 trdnpr:1; + u32 trdard:1; + u32 rdsati:1; + u32 trdrs:1; + u32 trtae:1; + u32 twsei:1; + u32 twsen:1; + u32 twtae:1; + u32 tmae:1; + u32 tslte:3; + u32 tilt:4; + u32 pbe:12; + u32 dppmr:1; + u32 reserved_2_2:1; + u32 tswc:1; + u32 mltd:1; +#else + u32 mltd:1; + u32 tswc:1; + u32 reserved_2_2:1; + u32 dppmr:1; + u32 pbe:12; + u32 tilt:4; + u32 tslte:3; + u32 tmae:1; + u32 twtae:1; + u32 twsen:1; + u32 twsei:1; + u32 trtae:1; + u32 trdrs:1; + u32 rdsati:1; + u32 trdard:1; + u32 trdnpr:1; +#endif + } s; +}; + +union cvmx_pci_cfg17 { + u32 u32; + struct cvmx_pci_cfg17_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 tscme:32; +#else + u32 tscme:32; +#endif + } s; +}; + +union cvmx_pci_cfg18 { + u32 u32; + struct cvmx_pci_cfg18_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 tdsrps:32; +#else + u32 tdsrps:32; +#endif + } s; +}; + +union cvmx_pci_cfg19 { + u32 u32; + struct cvmx_pci_cfg19_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 mrbcm:1; + u32 mrbci:1; + u32 mdwe:1; + u32 mdre:1; + u32 mdrimc:1; + u32 mdrrmc:3; + u32 tmes:8; + u32 teci:1; + u32 tmei:1; + u32 tmse:1; + u32 tmdpes:1; + u32 tmapes:1; + u32 reserved_9_10:2; + u32 tibcd:1; + u32 tibde:1; + u32 reserved_6_6:1; + u32 tidomc:1; + u32 tdomc:5; +#else + u32 tdomc:5; + u32 tidomc:1; + u32 reserved_6_6:1; + u32 tibde:1; + u32 tibcd:1; + u32 reserved_9_10:2; + u32 tmapes:1; + u32 tmdpes:1; + u32 tmse:1; + u32 tmei:1; + u32 teci:1; + u32 tmes:8; + u32 mdrrmc:3; + u32 mdrimc:1; + u32 mdre:1; + u32 mdwe:1; + u32 mrbci:1; + u32 mrbcm:1; +#endif + } s; +}; + +union cvmx_pci_cfg20 { + u32 u32; + struct cvmx_pci_cfg20_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 mdsp:32; +#else + u32 mdsp:32; +#endif + } s; +}; + +union cvmx_pci_cfg21 { + u32 u32; + struct cvmx_pci_cfg21_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 scmre:32; +#else + u32 scmre:32; +#endif + } s; +}; + +union cvmx_pci_cfg22 { + u32 u32; + struct cvmx_pci_cfg22_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 mac:7; + u32 reserved_19_24:6; + u32 flush:1; + u32 mra:1; + u32 mtta:1; + u32 mrv:8; + u32 mttv:8; +#else + u32 mttv:8; + u32 mrv:8; + u32 mtta:1; + u32 mra:1; + u32 flush:1; + u32 reserved_19_24:6; + u32 mac:7; +#endif + } s; +}; + +union cvmx_pci_cfg56 { + u32 u32; + struct cvmx_pci_cfg56_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_23_31:9; + u32 most:3; + u32 mmbc:2; + u32 roe:1; + u32 dpere:1; + u32 ncp:8; + u32 pxcid:8; +#else + u32 pxcid:8; + u32 ncp:8; + u32 dpere:1; + u32 roe:1; + u32 mmbc:2; + u32 most:3; + u32 reserved_23_31:9; +#endif + } s; +}; + +union cvmx_pci_cfg57 { + u32 u32; + struct cvmx_pci_cfg57_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_30_31:2; + u32 scemr:1; + u32 mcrsd:3; + u32 mostd:3; + u32 mmrbcd:2; + u32 dc:1; + u32 usc:1; + u32 scd:1; + u32 m133:1; + u32 w64:1; + u32 bn:8; + u32 dn:5; + u32 fn:3; +#else + u32 fn:3; + u32 dn:5; + u32 bn:8; + u32 w64:1; + u32 m133:1; + u32 scd:1; + u32 usc:1; + u32 dc:1; + u32 mmrbcd:2; + u32 mostd:3; + u32 mcrsd:3; + u32 scemr:1; + u32 reserved_30_31:2; +#endif + } s; +}; + +union cvmx_pci_cfg58 { + u32 u32; + struct cvmx_pci_cfg58_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pmes:5; + u32 d2s:1; + u32 d1s:1; + u32 auxc:3; + u32 dsi:1; + u32 reserved_20_20:1; + u32 pmec:1; + u32 pcimiv:3; + u32 ncp:8; + u32 pmcid:8; +#else + u32 pmcid:8; + u32 ncp:8; + u32 pcimiv:3; + u32 pmec:1; + u32 reserved_20_20:1; + u32 dsi:1; + u32 auxc:3; + u32 d1s:1; + u32 d2s:1; + u32 pmes:5; +#endif + } s; +}; + +union cvmx_pci_cfg59 { + u32 u32; + struct cvmx_pci_cfg59_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pmdia:8; + u32 bpccen:1; + u32 bd3h:1; + u32 reserved_16_21:6; + u32 pmess:1; + u32 pmedsia:2; + u32 pmds:4; + u32 pmeens:1; + u32 reserved_2_7:6; + u32 ps:2; +#else + u32 ps:2; + u32 reserved_2_7:6; + u32 pmeens:1; + u32 pmds:4; + u32 pmedsia:2; + u32 pmess:1; + u32 reserved_16_21:6; + u32 bd3h:1; + u32 bpccen:1; + u32 pmdia:8; +#endif + } s; +}; + +union cvmx_pci_cfg60 { + u32 u32; + struct cvmx_pci_cfg60_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_24_31:8; + u32 m64:1; + u32 mme:3; + u32 mmc:3; + u32 msien:1; + u32 ncp:8; + u32 msicid:8; +#else + u32 msicid:8; + u32 ncp:8; + u32 msien:1; + u32 mmc:3; + u32 mme:3; + u32 m64:1; + u32 reserved_24_31:8; +#endif + } s; +}; + +union cvmx_pci_cfg61 { + u32 u32; + struct cvmx_pci_cfg61_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 msi31t2:30; + u32 reserved_0_1:2; +#else + u32 reserved_0_1:2; + u32 msi31t2:30; +#endif + } s; +}; + +union cvmx_pci_cfg62 { + u32 u32; + struct cvmx_pci_cfg62_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 msi:32; +#else + u32 msi:32; +#endif + } s; +}; + +union cvmx_pci_cfg63 { + u32 u32; + struct cvmx_pci_cfg63_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_16_31:16; + u32 msimd:16; +#else + u32 msimd:16; + u32 reserved_16_31:16; +#endif + } s; +}; + +union cvmx_pci_cnt_reg { + u64 u64; + struct cvmx_pci_cnt_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 hm_pcix:1; + u64 hm_speed:2; + u64 ap_pcix:1; + u64 ap_speed:2; + u64 pcicnt:32; +#else + u64 pcicnt:32; + u64 ap_speed:2; + u64 ap_pcix:1; + u64 hm_speed:2; + u64 hm_pcix:1; + u64 reserved_38_63:26; +#endif + } s; +}; + +union cvmx_pci_ctl_status_2 { + u32 u32; + struct cvmx_pci_ctl_status_2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_29_31:3; + u32 bb1_hole:3; + u32 bb1_siz:1; + u32 bb_ca:1; + u32 bb_es:2; + u32 bb1:1; + u32 bb0:1; + u32 erst_n:1; + u32 bar2pres:1; + u32 scmtyp:1; + u32 scm:1; + u32 en_wfilt:1; + u32 reserved_14_14:1; + u32 ap_pcix:1; + u32 ap_64ad:1; + u32 b12_bist:1; + u32 pmo_amod:1; + u32 pmo_fpc:3; + u32 tsr_hwm:3; + u32 bar2_enb:1; + u32 bar2_esx:2; + u32 bar2_cax:1; +#else + u32 bar2_cax:1; + u32 bar2_esx:2; + u32 bar2_enb:1; + u32 tsr_hwm:3; + u32 pmo_fpc:3; + u32 pmo_amod:1; + u32 b12_bist:1; + u32 ap_64ad:1; + u32 ap_pcix:1; + u32 reserved_14_14:1; + u32 en_wfilt:1; + u32 scm:1; + u32 scmtyp:1; + u32 bar2pres:1; + u32 erst_n:1; + u32 bb0:1; + u32 bb1:1; + u32 bb_es:2; + u32 bb_ca:1; + u32 bb1_siz:1; + u32 bb1_hole:3; + u32 reserved_29_31:3; +#endif + } s; + struct cvmx_pci_ctl_status_2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_20_31:12; + u32 erst_n:1; + u32 bar2pres:1; + u32 scmtyp:1; + u32 scm:1; + u32 en_wfilt:1; + u32 reserved_14_14:1; + u32 ap_pcix:1; + u32 ap_64ad:1; + u32 b12_bist:1; + u32 pmo_amod:1; + u32 pmo_fpc:3; + u32 tsr_hwm:3; + u32 bar2_enb:1; + u32 bar2_esx:2; + u32 bar2_cax:1; +#else + u32 bar2_cax:1; + u32 bar2_esx:2; + u32 bar2_enb:1; + u32 tsr_hwm:3; + u32 pmo_fpc:3; + u32 pmo_amod:1; + u32 b12_bist:1; + u32 ap_64ad:1; + u32 ap_pcix:1; + u32 reserved_14_14:1; + u32 en_wfilt:1; + u32 scm:1; + u32 scmtyp:1; + u32 bar2pres:1; + u32 erst_n:1; + u32 reserved_20_31:12; +#endif + } cn31xx; +}; + +union cvmx_pci_dbellx { + u32 u32; + struct cvmx_pci_dbellx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_16_31:16; + u32 inc_val:16; +#else + u32 inc_val:16; + u32 reserved_16_31:16; +#endif + } s; +}; + +union cvmx_pci_dma_cntx { + u32 u32; + struct cvmx_pci_dma_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 dma_cnt:32; +#else + u32 dma_cnt:32; +#endif + } s; +}; + +union cvmx_pci_dma_int_levx { + u32 u32; + struct cvmx_pci_dma_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pkt_cnt:32; +#else + u32 pkt_cnt:32; +#endif + } s; +}; + +union cvmx_pci_dma_timex { + u32 u32; + struct cvmx_pci_dma_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 dma_time:32; +#else + u32 dma_time:32; +#endif + } s; +}; + +union cvmx_pci_instr_countx { + u32 u32; + struct cvmx_pci_instr_countx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 icnt:32; +#else + u32 icnt:32; +#endif + } s; +}; + +union cvmx_pci_int_enb { + u64 u64; + struct cvmx_pci_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 idtime1:1; + u64 idtime0:1; + u64 idcnt1:1; + u64 idcnt0:1; + u64 iptime3:1; + u64 iptime2:1; + u64 iptime1:1; + u64 iptime0:1; + u64 ipcnt3:1; + u64 ipcnt2:1; + u64 ipcnt1:1; + u64 ipcnt0:1; + u64 irsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 idperr:1; + u64 iaperr:1; + u64 iserr:1; + u64 itsr_abt:1; + u64 imsc_msg:1; + u64 imsi_mabt:1; + u64 imsi_tabt:1; + u64 imsi_per:1; + u64 imr_tto:1; + u64 imr_abt:1; + u64 itr_abt:1; + u64 imr_wtto:1; + u64 imr_wabt:1; + u64 itr_wabt:1; +#else + u64 itr_wabt:1; + u64 imr_wabt:1; + u64 imr_wtto:1; + u64 itr_abt:1; + u64 imr_abt:1; + u64 imr_tto:1; + u64 imsi_per:1; + u64 imsi_tabt:1; + u64 imsi_mabt:1; + u64 imsc_msg:1; + u64 itsr_abt:1; + u64 iserr:1; + u64 iaperr:1; + u64 idperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 irsl_int:1; + u64 ipcnt0:1; + u64 ipcnt1:1; + u64 ipcnt2:1; + u64 ipcnt3:1; + u64 iptime0:1; + u64 iptime1:1; + u64 iptime2:1; + u64 iptime3:1; + u64 idcnt0:1; + u64 idcnt1:1; + u64 idtime0:1; + u64 idtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } s; + struct cvmx_pci_int_enb_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 idtime1:1; + u64 idtime0:1; + u64 idcnt1:1; + u64 idcnt0:1; + u64 reserved_22_24:3; + u64 iptime0:1; + u64 reserved_18_20:3; + u64 ipcnt0:1; + u64 irsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 idperr:1; + u64 iaperr:1; + u64 iserr:1; + u64 itsr_abt:1; + u64 imsc_msg:1; + u64 imsi_mabt:1; + u64 imsi_tabt:1; + u64 imsi_per:1; + u64 imr_tto:1; + u64 imr_abt:1; + u64 itr_abt:1; + u64 imr_wtto:1; + u64 imr_wabt:1; + u64 itr_wabt:1; +#else + u64 itr_wabt:1; + u64 imr_wabt:1; + u64 imr_wtto:1; + u64 itr_abt:1; + u64 imr_abt:1; + u64 imr_tto:1; + u64 imsi_per:1; + u64 imsi_tabt:1; + u64 imsi_mabt:1; + u64 imsc_msg:1; + u64 itsr_abt:1; + u64 iserr:1; + u64 iaperr:1; + u64 idperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 irsl_int:1; + u64 ipcnt0:1; + u64 reserved_18_20:3; + u64 iptime0:1; + u64 reserved_22_24:3; + u64 idcnt0:1; + u64 idcnt1:1; + u64 idtime0:1; + u64 idtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn30xx; + struct cvmx_pci_int_enb_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 idtime1:1; + u64 idtime0:1; + u64 idcnt1:1; + u64 idcnt0:1; + u64 reserved_23_24:2; + u64 iptime1:1; + u64 iptime0:1; + u64 reserved_19_20:2; + u64 ipcnt1:1; + u64 ipcnt0:1; + u64 irsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 idperr:1; + u64 iaperr:1; + u64 iserr:1; + u64 itsr_abt:1; + u64 imsc_msg:1; + u64 imsi_mabt:1; + u64 imsi_tabt:1; + u64 imsi_per:1; + u64 imr_tto:1; + u64 imr_abt:1; + u64 itr_abt:1; + u64 imr_wtto:1; + u64 imr_wabt:1; + u64 itr_wabt:1; +#else + u64 itr_wabt:1; + u64 imr_wabt:1; + u64 imr_wtto:1; + u64 itr_abt:1; + u64 imr_abt:1; + u64 imr_tto:1; + u64 imsi_per:1; + u64 imsi_tabt:1; + u64 imsi_mabt:1; + u64 imsc_msg:1; + u64 itsr_abt:1; + u64 iserr:1; + u64 iaperr:1; + u64 idperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 irsl_int:1; + u64 ipcnt0:1; + u64 ipcnt1:1; + u64 reserved_19_20:2; + u64 iptime0:1; + u64 iptime1:1; + u64 reserved_23_24:2; + u64 idcnt0:1; + u64 idcnt1:1; + u64 idtime0:1; + u64 idtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn31xx; +}; + +union cvmx_pci_int_enb2 { + u64 u64; + struct cvmx_pci_int_enb2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 rdtime1:1; + u64 rdtime0:1; + u64 rdcnt1:1; + u64 rdcnt0:1; + u64 rptime3:1; + u64 rptime2:1; + u64 rptime1:1; + u64 rptime0:1; + u64 rpcnt3:1; + u64 rpcnt2:1; + u64 rpcnt1:1; + u64 rpcnt0:1; + u64 rrsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 rdperr:1; + u64 raperr:1; + u64 rserr:1; + u64 rtsr_abt:1; + u64 rmsc_msg:1; + u64 rmsi_mabt:1; + u64 rmsi_tabt:1; + u64 rmsi_per:1; + u64 rmr_tto:1; + u64 rmr_abt:1; + u64 rtr_abt:1; + u64 rmr_wtto:1; + u64 rmr_wabt:1; + u64 rtr_wabt:1; +#else + u64 rtr_wabt:1; + u64 rmr_wabt:1; + u64 rmr_wtto:1; + u64 rtr_abt:1; + u64 rmr_abt:1; + u64 rmr_tto:1; + u64 rmsi_per:1; + u64 rmsi_tabt:1; + u64 rmsi_mabt:1; + u64 rmsc_msg:1; + u64 rtsr_abt:1; + u64 rserr:1; + u64 raperr:1; + u64 rdperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rrsl_int:1; + u64 rpcnt0:1; + u64 rpcnt1:1; + u64 rpcnt2:1; + u64 rpcnt3:1; + u64 rptime0:1; + u64 rptime1:1; + u64 rptime2:1; + u64 rptime3:1; + u64 rdcnt0:1; + u64 rdcnt1:1; + u64 rdtime0:1; + u64 rdtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } s; + struct cvmx_pci_int_enb2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 rdtime1:1; + u64 rdtime0:1; + u64 rdcnt1:1; + u64 rdcnt0:1; + u64 reserved_22_24:3; + u64 rptime0:1; + u64 reserved_18_20:3; + u64 rpcnt0:1; + u64 rrsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 rdperr:1; + u64 raperr:1; + u64 rserr:1; + u64 rtsr_abt:1; + u64 rmsc_msg:1; + u64 rmsi_mabt:1; + u64 rmsi_tabt:1; + u64 rmsi_per:1; + u64 rmr_tto:1; + u64 rmr_abt:1; + u64 rtr_abt:1; + u64 rmr_wtto:1; + u64 rmr_wabt:1; + u64 rtr_wabt:1; +#else + u64 rtr_wabt:1; + u64 rmr_wabt:1; + u64 rmr_wtto:1; + u64 rtr_abt:1; + u64 rmr_abt:1; + u64 rmr_tto:1; + u64 rmsi_per:1; + u64 rmsi_tabt:1; + u64 rmsi_mabt:1; + u64 rmsc_msg:1; + u64 rtsr_abt:1; + u64 rserr:1; + u64 raperr:1; + u64 rdperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rrsl_int:1; + u64 rpcnt0:1; + u64 reserved_18_20:3; + u64 rptime0:1; + u64 reserved_22_24:3; + u64 rdcnt0:1; + u64 rdcnt1:1; + u64 rdtime0:1; + u64 rdtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn30xx; + struct cvmx_pci_int_enb2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 rdtime1:1; + u64 rdtime0:1; + u64 rdcnt1:1; + u64 rdcnt0:1; + u64 reserved_23_24:2; + u64 rptime1:1; + u64 rptime0:1; + u64 reserved_19_20:2; + u64 rpcnt1:1; + u64 rpcnt0:1; + u64 rrsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 rdperr:1; + u64 raperr:1; + u64 rserr:1; + u64 rtsr_abt:1; + u64 rmsc_msg:1; + u64 rmsi_mabt:1; + u64 rmsi_tabt:1; + u64 rmsi_per:1; + u64 rmr_tto:1; + u64 rmr_abt:1; + u64 rtr_abt:1; + u64 rmr_wtto:1; + u64 rmr_wabt:1; + u64 rtr_wabt:1; +#else + u64 rtr_wabt:1; + u64 rmr_wabt:1; + u64 rmr_wtto:1; + u64 rtr_abt:1; + u64 rmr_abt:1; + u64 rmr_tto:1; + u64 rmsi_per:1; + u64 rmsi_tabt:1; + u64 rmsi_mabt:1; + u64 rmsc_msg:1; + u64 rtsr_abt:1; + u64 rserr:1; + u64 raperr:1; + u64 rdperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rrsl_int:1; + u64 rpcnt0:1; + u64 rpcnt1:1; + u64 reserved_19_20:2; + u64 rptime0:1; + u64 rptime1:1; + u64 reserved_23_24:2; + u64 rdcnt0:1; + u64 rdcnt1:1; + u64 rdtime0:1; + u64 rdtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn31xx; +}; + +union cvmx_pci_int_sum { + u64 u64; + struct cvmx_pci_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 ptime3:1; + u64 ptime2:1; + u64 ptime1:1; + u64 ptime0:1; + u64 pcnt3:1; + u64 pcnt2:1; + u64 pcnt1:1; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 pcnt1:1; + u64 pcnt2:1; + u64 pcnt3:1; + u64 ptime0:1; + u64 ptime1:1; + u64 ptime2:1; + u64 ptime3:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } s; + struct cvmx_pci_int_sum_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 reserved_22_24:3; + u64 ptime0:1; + u64 reserved_18_20:3; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 reserved_18_20:3; + u64 ptime0:1; + u64 reserved_22_24:3; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn30xx; + struct cvmx_pci_int_sum_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 reserved_23_24:2; + u64 ptime1:1; + u64 ptime0:1; + u64 reserved_19_20:2; + u64 pcnt1:1; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 pcnt1:1; + u64 reserved_19_20:2; + u64 ptime0:1; + u64 ptime1:1; + u64 reserved_23_24:2; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn31xx; +}; + +union cvmx_pci_int_sum2 { + u64 u64; + struct cvmx_pci_int_sum2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 ptime3:1; + u64 ptime2:1; + u64 ptime1:1; + u64 ptime0:1; + u64 pcnt3:1; + u64 pcnt2:1; + u64 pcnt1:1; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 pcnt1:1; + u64 pcnt2:1; + u64 pcnt3:1; + u64 ptime0:1; + u64 ptime1:1; + u64 ptime2:1; + u64 ptime3:1; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } s; + struct cvmx_pci_int_sum2_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 reserved_22_24:3; + u64 ptime0:1; + u64 reserved_18_20:3; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 reserved_18_20:3; + u64 ptime0:1; + u64 reserved_22_24:3; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn30xx; + struct cvmx_pci_int_sum2_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_34_63:30; + u64 ill_rd:1; + u64 ill_wr:1; + u64 win_wr:1; + u64 dma1_fi:1; + u64 dma0_fi:1; + u64 dtime1:1; + u64 dtime0:1; + u64 dcnt1:1; + u64 dcnt0:1; + u64 reserved_23_24:2; + u64 ptime1:1; + u64 ptime0:1; + u64 reserved_19_20:2; + u64 pcnt1:1; + u64 pcnt0:1; + u64 rsl_int:1; + u64 ill_rrd:1; + u64 ill_rwr:1; + u64 dperr:1; + u64 aperr:1; + u64 serr:1; + u64 tsr_abt:1; + u64 msc_msg:1; + u64 msi_mabt:1; + u64 msi_tabt:1; + u64 msi_per:1; + u64 mr_tto:1; + u64 mr_abt:1; + u64 tr_abt:1; + u64 mr_wtto:1; + u64 mr_wabt:1; + u64 tr_wabt:1; +#else + u64 tr_wabt:1; + u64 mr_wabt:1; + u64 mr_wtto:1; + u64 tr_abt:1; + u64 mr_abt:1; + u64 mr_tto:1; + u64 msi_per:1; + u64 msi_tabt:1; + u64 msi_mabt:1; + u64 msc_msg:1; + u64 tsr_abt:1; + u64 serr:1; + u64 aperr:1; + u64 dperr:1; + u64 ill_rwr:1; + u64 ill_rrd:1; + u64 rsl_int:1; + u64 pcnt0:1; + u64 pcnt1:1; + u64 reserved_19_20:2; + u64 ptime0:1; + u64 ptime1:1; + u64 reserved_23_24:2; + u64 dcnt0:1; + u64 dcnt1:1; + u64 dtime0:1; + u64 dtime1:1; + u64 dma0_fi:1; + u64 dma1_fi:1; + u64 win_wr:1; + u64 ill_wr:1; + u64 ill_rd:1; + u64 reserved_34_63:30; +#endif + } cn31xx; +}; + +union cvmx_pci_msi_rcv { + u32 u32; + struct cvmx_pci_msi_rcv_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_6_31:26; + u32 intr:6; +#else + u32 intr:6; + u32 reserved_6_31:26; +#endif + } s; +}; + +union cvmx_pci_pkt_creditsx { + u32 u32; + struct cvmx_pci_pkt_creditsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pkt_cnt:16; + u32 ptr_cnt:16; +#else + u32 ptr_cnt:16; + u32 pkt_cnt:16; +#endif + } s; +}; + +union cvmx_pci_pkts_sentx { + u32 u32; + struct cvmx_pci_pkts_sentx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pkt_cnt:32; +#else + u32 pkt_cnt:32; +#endif + } s; +}; + +union cvmx_pci_pkts_sent_int_levx { + u32 u32; + struct cvmx_pci_pkts_sent_int_levx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pkt_cnt:32; +#else + u32 pkt_cnt:32; +#endif + } s; +}; + +union cvmx_pci_pkts_sent_timex { + u32 u32; + struct cvmx_pci_pkts_sent_timex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 pkt_time:32; +#else + u32 pkt_time:32; +#endif + } s; +}; + +union cvmx_pci_read_cmd_6 { + u32 u32; + struct cvmx_pci_read_cmd_6_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_9_31:23; + u32 min_data:6; + u32 prefetch:3; +#else + u32 prefetch:3; + u32 min_data:6; + u32 reserved_9_31:23; +#endif + } s; +}; + +union cvmx_pci_read_cmd_c { + u32 u32; + struct cvmx_pci_read_cmd_c_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_9_31:23; + u32 min_data:6; + u32 prefetch:3; +#else + u32 prefetch:3; + u32 min_data:6; + u32 reserved_9_31:23; +#endif + } s; +}; + +union cvmx_pci_read_cmd_e { + u32 u32; + struct cvmx_pci_read_cmd_e_s { +#ifdef __BIG_ENDIAN_BITFIELD + u32 reserved_9_31:23; + u32 min_data:6; + u32 prefetch:3; +#else + u32 prefetch:3; + u32 min_data:6; + u32 reserved_9_31:23; +#endif + } s; +}; + +union cvmx_pci_read_timeout { + u64 u64; + struct cvmx_pci_read_timeout_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enb:1; + u64 cnt:31; +#else + u64 cnt:31; + u64 enb:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pci_scm_reg { + u64 u64; + struct cvmx_pci_scm_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 scm:32; +#else + u64 scm:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pci_tsr_reg { + u64 u64; + struct cvmx_pci_tsr_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 tsr:36; +#else + u64 tsr:36; + u64 reserved_36_63:28; +#endif + } s; +}; + +union cvmx_pci_win_rd_addr { + u64 u64; + struct cvmx_pci_win_rd_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 iobit:1; + u64 reserved_0_47:48; +#else + u64 reserved_0_47:48; + u64 iobit:1; + u64 reserved_49_63:15; +#endif + } s; + struct cvmx_pci_win_rd_addr_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 iobit:1; + u64 rd_addr:46; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 rd_addr:46; + u64 iobit:1; + u64 reserved_49_63:15; +#endif + } cn30xx; + struct cvmx_pci_win_rd_addr_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 iobit:1; + u64 rd_addr:45; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 rd_addr:45; + u64 iobit:1; + u64 reserved_49_63:15; +#endif + } cn38xx; +}; + +union cvmx_pci_win_rd_data { + u64 u64; + struct cvmx_pci_win_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rd_data:64; +#else + u64 rd_data:64; +#endif + } s; +}; + +union cvmx_pci_win_wr_addr { + u64 u64; + struct cvmx_pci_win_wr_addr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 iobit:1; + u64 wr_addr:45; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 wr_addr:45; + u64 iobit:1; + u64 reserved_49_63:15; +#endif + } s; +}; + +union cvmx_pci_win_wr_data { + u64 u64; + struct cvmx_pci_win_wr_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wr_data:64; +#else + u64 wr_data:64; +#endif + } s; +}; + +union cvmx_pci_win_wr_mask { + u64 u64; + struct cvmx_pci_win_wr_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 wr_mask:8; +#else + u64 wr_mask:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pciercx-defs.h b/drivers/staging/octeon/cvmx-pciercx-defs.h new file mode 100644 index 000000000000..429f8787d707 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pciercx-defs.h @@ -0,0 +1,367 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCIERCX_DEFS_H__ +#define __CVMX_PCIERCX_DEFS_H__ + +#include + +#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) +#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) +#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) +#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) +#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) +#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) +#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) +#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) +#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) +#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) +#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) +#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) +#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) +#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) +#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) +#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) +#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) +#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) +#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) +#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) + +union cvmx_pciercx_cfg001 { + u32 u32; + struct cvmx_pciercx_cfg001_s { + __BITFIELD_FIELD(u32 dpe:1, + __BITFIELD_FIELD(u32 sse:1, + __BITFIELD_FIELD(u32 rma:1, + __BITFIELD_FIELD(u32 rta:1, + __BITFIELD_FIELD(u32 sta:1, + __BITFIELD_FIELD(u32 devt:2, + __BITFIELD_FIELD(u32 mdpe:1, + __BITFIELD_FIELD(u32 fbb:1, + __BITFIELD_FIELD(u32 reserved_22_22:1, + __BITFIELD_FIELD(u32 m66:1, + __BITFIELD_FIELD(u32 cl:1, + __BITFIELD_FIELD(u32 i_stat:1, + __BITFIELD_FIELD(u32 reserved_11_18:8, + __BITFIELD_FIELD(u32 i_dis:1, + __BITFIELD_FIELD(u32 fbbe:1, + __BITFIELD_FIELD(u32 see:1, + __BITFIELD_FIELD(u32 ids_wcc:1, + __BITFIELD_FIELD(u32 per:1, + __BITFIELD_FIELD(u32 vps:1, + __BITFIELD_FIELD(u32 mwice:1, + __BITFIELD_FIELD(u32 scse:1, + __BITFIELD_FIELD(u32 me:1, + __BITFIELD_FIELD(u32 msae:1, + __BITFIELD_FIELD(u32 isae:1, + ;)))))))))))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg006 { + u32 u32; + struct cvmx_pciercx_cfg006_s { + __BITFIELD_FIELD(u32 slt:8, + __BITFIELD_FIELD(u32 subbnum:8, + __BITFIELD_FIELD(u32 sbnum:8, + __BITFIELD_FIELD(u32 pbnum:8, + ;)))) + } s; +}; + +union cvmx_pciercx_cfg008 { + u32 u32; + struct cvmx_pciercx_cfg008_s { + __BITFIELD_FIELD(u32 ml_addr:12, + __BITFIELD_FIELD(u32 reserved_16_19:4, + __BITFIELD_FIELD(u32 mb_addr:12, + __BITFIELD_FIELD(u32 reserved_0_3:4, + ;)))) + } s; +}; + +union cvmx_pciercx_cfg009 { + u32 u32; + struct cvmx_pciercx_cfg009_s { + __BITFIELD_FIELD(u32 lmem_limit:12, + __BITFIELD_FIELD(u32 reserved_17_19:3, + __BITFIELD_FIELD(u32 mem64b:1, + __BITFIELD_FIELD(u32 lmem_base:12, + __BITFIELD_FIELD(u32 reserved_1_3:3, + __BITFIELD_FIELD(u32 mem64a:1, + ;)))))) + } s; +}; + +union cvmx_pciercx_cfg010 { + u32 u32; + struct cvmx_pciercx_cfg010_s { + u32 umem_base; + } s; +}; + +union cvmx_pciercx_cfg011 { + u32 u32; + struct cvmx_pciercx_cfg011_s { + u32 umem_limit; + } s; +}; + +union cvmx_pciercx_cfg030 { + u32 u32; + struct cvmx_pciercx_cfg030_s { + __BITFIELD_FIELD(u32 reserved_22_31:10, + __BITFIELD_FIELD(u32 tp:1, + __BITFIELD_FIELD(u32 ap_d:1, + __BITFIELD_FIELD(u32 ur_d:1, + __BITFIELD_FIELD(u32 fe_d:1, + __BITFIELD_FIELD(u32 nfe_d:1, + __BITFIELD_FIELD(u32 ce_d:1, + __BITFIELD_FIELD(u32 reserved_15_15:1, + __BITFIELD_FIELD(u32 mrrs:3, + __BITFIELD_FIELD(u32 ns_en:1, + __BITFIELD_FIELD(u32 ap_en:1, + __BITFIELD_FIELD(u32 pf_en:1, + __BITFIELD_FIELD(u32 etf_en:1, + __BITFIELD_FIELD(u32 mps:3, + __BITFIELD_FIELD(u32 ro_en:1, + __BITFIELD_FIELD(u32 ur_en:1, + __BITFIELD_FIELD(u32 fe_en:1, + __BITFIELD_FIELD(u32 nfe_en:1, + __BITFIELD_FIELD(u32 ce_en:1, + ;))))))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg031 { + u32 u32; + struct cvmx_pciercx_cfg031_s { + __BITFIELD_FIELD(u32 pnum:8, + __BITFIELD_FIELD(u32 reserved_23_23:1, + __BITFIELD_FIELD(u32 aspm:1, + __BITFIELD_FIELD(u32 lbnc:1, + __BITFIELD_FIELD(u32 dllarc:1, + __BITFIELD_FIELD(u32 sderc:1, + __BITFIELD_FIELD(u32 cpm:1, + __BITFIELD_FIELD(u32 l1el:3, + __BITFIELD_FIELD(u32 l0el:3, + __BITFIELD_FIELD(u32 aslpms:2, + __BITFIELD_FIELD(u32 mlw:6, + __BITFIELD_FIELD(u32 mls:4, + ;)))))))))))) + } s; +}; + +union cvmx_pciercx_cfg032 { + u32 u32; + struct cvmx_pciercx_cfg032_s { + __BITFIELD_FIELD(u32 lab:1, + __BITFIELD_FIELD(u32 lbm:1, + __BITFIELD_FIELD(u32 dlla:1, + __BITFIELD_FIELD(u32 scc:1, + __BITFIELD_FIELD(u32 lt:1, + __BITFIELD_FIELD(u32 reserved_26_26:1, + __BITFIELD_FIELD(u32 nlw:6, + __BITFIELD_FIELD(u32 ls:4, + __BITFIELD_FIELD(u32 reserved_12_15:4, + __BITFIELD_FIELD(u32 lab_int_enb:1, + __BITFIELD_FIELD(u32 lbm_int_enb:1, + __BITFIELD_FIELD(u32 hawd:1, + __BITFIELD_FIELD(u32 ecpm:1, + __BITFIELD_FIELD(u32 es:1, + __BITFIELD_FIELD(u32 ccc:1, + __BITFIELD_FIELD(u32 rl:1, + __BITFIELD_FIELD(u32 ld:1, + __BITFIELD_FIELD(u32 rcb:1, + __BITFIELD_FIELD(u32 reserved_2_2:1, + __BITFIELD_FIELD(u32 aslpc:2, + ;)))))))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg034 { + u32 u32; + struct cvmx_pciercx_cfg034_s { + __BITFIELD_FIELD(u32 reserved_25_31:7, + __BITFIELD_FIELD(u32 dlls_c:1, + __BITFIELD_FIELD(u32 emis:1, + __BITFIELD_FIELD(u32 pds:1, + __BITFIELD_FIELD(u32 mrlss:1, + __BITFIELD_FIELD(u32 ccint_d:1, + __BITFIELD_FIELD(u32 pd_c:1, + __BITFIELD_FIELD(u32 mrls_c:1, + __BITFIELD_FIELD(u32 pf_d:1, + __BITFIELD_FIELD(u32 abp_d:1, + __BITFIELD_FIELD(u32 reserved_13_15:3, + __BITFIELD_FIELD(u32 dlls_en:1, + __BITFIELD_FIELD(u32 emic:1, + __BITFIELD_FIELD(u32 pcc:1, + __BITFIELD_FIELD(u32 pic:1, + __BITFIELD_FIELD(u32 aic:1, + __BITFIELD_FIELD(u32 hpint_en:1, + __BITFIELD_FIELD(u32 ccint_en:1, + __BITFIELD_FIELD(u32 pd_en:1, + __BITFIELD_FIELD(u32 mrls_en:1, + __BITFIELD_FIELD(u32 pf_en:1, + __BITFIELD_FIELD(u32 abp_en:1, + ;)))))))))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg035 { + u32 u32; + struct cvmx_pciercx_cfg035_s { + __BITFIELD_FIELD(u32 reserved_17_31:15, + __BITFIELD_FIELD(u32 crssv:1, + __BITFIELD_FIELD(u32 reserved_5_15:11, + __BITFIELD_FIELD(u32 crssve:1, + __BITFIELD_FIELD(u32 pmeie:1, + __BITFIELD_FIELD(u32 sefee:1, + __BITFIELD_FIELD(u32 senfee:1, + __BITFIELD_FIELD(u32 secee:1, + ;)))))))) + } s; +}; + +union cvmx_pciercx_cfg040 { + u32 u32; + struct cvmx_pciercx_cfg040_s { + __BITFIELD_FIELD(u32 reserved_22_31:10, + __BITFIELD_FIELD(u32 ler:1, + __BITFIELD_FIELD(u32 ep3s:1, + __BITFIELD_FIELD(u32 ep2s:1, + __BITFIELD_FIELD(u32 ep1s:1, + __BITFIELD_FIELD(u32 eqc:1, + __BITFIELD_FIELD(u32 cdl:1, + __BITFIELD_FIELD(u32 cde:4, + __BITFIELD_FIELD(u32 csos:1, + __BITFIELD_FIELD(u32 emc:1, + __BITFIELD_FIELD(u32 tm:3, + __BITFIELD_FIELD(u32 sde:1, + __BITFIELD_FIELD(u32 hasd:1, + __BITFIELD_FIELD(u32 ec:1, + __BITFIELD_FIELD(u32 tls:4, + ;))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg070 { + u32 u32; + struct cvmx_pciercx_cfg070_s { + __BITFIELD_FIELD(u32 reserved_12_31:20, + __BITFIELD_FIELD(u32 tplp:1, + __BITFIELD_FIELD(u32 reserved_9_10:2, + __BITFIELD_FIELD(u32 ce:1, + __BITFIELD_FIELD(u32 cc:1, + __BITFIELD_FIELD(u32 ge:1, + __BITFIELD_FIELD(u32 gc:1, + __BITFIELD_FIELD(u32 fep:5, + ;)))))))) + } s; +}; + +union cvmx_pciercx_cfg075 { + u32 u32; + struct cvmx_pciercx_cfg075_s { + __BITFIELD_FIELD(u32 reserved_3_31:29, + __BITFIELD_FIELD(u32 fere:1, + __BITFIELD_FIELD(u32 nfere:1, + __BITFIELD_FIELD(u32 cere:1, + ;)))) + } s; +}; + +union cvmx_pciercx_cfg448 { + u32 u32; + struct cvmx_pciercx_cfg448_s { + __BITFIELD_FIELD(u32 rtl:16, + __BITFIELD_FIELD(u32 rtltl:16, + ;)) + } s; +}; + +union cvmx_pciercx_cfg452 { + u32 u32; + struct cvmx_pciercx_cfg452_s { + __BITFIELD_FIELD(u32 reserved_26_31:6, + __BITFIELD_FIELD(u32 eccrc:1, + __BITFIELD_FIELD(u32 reserved_22_24:3, + __BITFIELD_FIELD(u32 lme:6, + __BITFIELD_FIELD(u32 reserved_12_15:4, + __BITFIELD_FIELD(u32 link_rate:4, + __BITFIELD_FIELD(u32 flm:1, + __BITFIELD_FIELD(u32 reserved_6_6:1, + __BITFIELD_FIELD(u32 dllle:1, + __BITFIELD_FIELD(u32 reserved_4_4:1, + __BITFIELD_FIELD(u32 ra:1, + __BITFIELD_FIELD(u32 le:1, + __BITFIELD_FIELD(u32 sd:1, + __BITFIELD_FIELD(u32 omr:1, + ;)))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg455 { + u32 u32; + struct cvmx_pciercx_cfg455_s { + __BITFIELD_FIELD(u32 m_cfg0_filt:1, + __BITFIELD_FIELD(u32 m_io_filt:1, + __BITFIELD_FIELD(u32 msg_ctrl:1, + __BITFIELD_FIELD(u32 m_cpl_ecrc_filt:1, + __BITFIELD_FIELD(u32 m_ecrc_filt:1, + __BITFIELD_FIELD(u32 m_cpl_len_err:1, + __BITFIELD_FIELD(u32 m_cpl_attr_err:1, + __BITFIELD_FIELD(u32 m_cpl_tc_err:1, + __BITFIELD_FIELD(u32 m_cpl_fun_err:1, + __BITFIELD_FIELD(u32 m_cpl_rid_err:1, + __BITFIELD_FIELD(u32 m_cpl_tag_err:1, + __BITFIELD_FIELD(u32 m_lk_filt:1, + __BITFIELD_FIELD(u32 m_cfg1_filt:1, + __BITFIELD_FIELD(u32 m_bar_match:1, + __BITFIELD_FIELD(u32 m_pois_filt:1, + __BITFIELD_FIELD(u32 m_fun:1, + __BITFIELD_FIELD(u32 dfcwt:1, + __BITFIELD_FIELD(u32 reserved_11_14:4, + __BITFIELD_FIELD(u32 skpiv:11, + ;))))))))))))))))))) + } s; +}; + +union cvmx_pciercx_cfg515 { + u32 u32; + struct cvmx_pciercx_cfg515_s { + __BITFIELD_FIELD(u32 reserved_21_31:11, + __BITFIELD_FIELD(u32 s_d_e:1, + __BITFIELD_FIELD(u32 ctcrb:1, + __BITFIELD_FIELD(u32 cpyts:1, + __BITFIELD_FIELD(u32 dsc:1, + __BITFIELD_FIELD(u32 le:9, + __BITFIELD_FIELD(u32 n_fts:8, + ;))))))) + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/drivers/staging/octeon/cvmx-pcsx-defs.h new file mode 100644 index 000000000000..b5721ab16f08 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsx-defs.h @@ -0,0 +1,825 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSX_DEFS_H__ +#define __CVMX_PCSX_DEFS_H__ + +static inline u64 CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +static inline u64 CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024; + } + return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024; +} + +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); + +union cvmx_pcsx_anx_adv_reg { + u64 u64; + struct cvmx_pcsx_anx_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 np:1; + u64 reserved_14_14:1; + u64 rem_flt:2; + u64 reserved_9_11:3; + u64 pause:2; + u64 hfd:1; + u64 fd:1; + u64 reserved_0_4:5; +#else + u64 reserved_0_4:5; + u64 fd:1; + u64 hfd:1; + u64 pause:2; + u64 reserved_9_11:3; + u64 rem_flt:2; + u64 reserved_14_14:1; + u64 np:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_anx_ext_st_reg { + u64 u64; + struct cvmx_pcsx_anx_ext_st_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 thou_xfd:1; + u64 thou_xhd:1; + u64 thou_tfd:1; + u64 thou_thd:1; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 thou_thd:1; + u64 thou_tfd:1; + u64 thou_xhd:1; + u64 thou_xfd:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_anx_lp_abil_reg { + u64 u64; + struct cvmx_pcsx_anx_lp_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 np:1; + u64 ack:1; + u64 rem_flt:2; + u64 reserved_9_11:3; + u64 pause:2; + u64 hfd:1; + u64 fd:1; + u64 reserved_0_4:5; +#else + u64 reserved_0_4:5; + u64 fd:1; + u64 hfd:1; + u64 pause:2; + u64 reserved_9_11:3; + u64 rem_flt:2; + u64 ack:1; + u64 np:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_anx_results_reg { + u64 u64; + struct cvmx_pcsx_anx_results_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 pause:2; + u64 spd:2; + u64 an_cpt:1; + u64 dup:1; + u64 link_ok:1; +#else + u64 link_ok:1; + u64 dup:1; + u64 an_cpt:1; + u64 spd:2; + u64 pause:2; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_pcsx_intx_en_reg { + u64 u64; + struct cvmx_pcsx_intx_en_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 dbg_sync_en:1; + u64 dup:1; + u64 sync_bad_en:1; + u64 an_bad_en:1; + u64 rxlock_en:1; + u64 rxbad_en:1; + u64 rxerr_en:1; + u64 txbad_en:1; + u64 txfifo_en:1; + u64 txfifu_en:1; + u64 an_err_en:1; + u64 xmit_en:1; + u64 lnkspd_en:1; +#else + u64 lnkspd_en:1; + u64 xmit_en:1; + u64 an_err_en:1; + u64 txfifu_en:1; + u64 txfifo_en:1; + u64 txbad_en:1; + u64 rxerr_en:1; + u64 rxbad_en:1; + u64 rxlock_en:1; + u64 an_bad_en:1; + u64 sync_bad_en:1; + u64 dup:1; + u64 dbg_sync_en:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_pcsx_intx_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 dup:1; + u64 sync_bad_en:1; + u64 an_bad_en:1; + u64 rxlock_en:1; + u64 rxbad_en:1; + u64 rxerr_en:1; + u64 txbad_en:1; + u64 txfifo_en:1; + u64 txfifu_en:1; + u64 an_err_en:1; + u64 xmit_en:1; + u64 lnkspd_en:1; +#else + u64 lnkspd_en:1; + u64 xmit_en:1; + u64 an_err_en:1; + u64 txfifu_en:1; + u64 txfifo_en:1; + u64 txbad_en:1; + u64 rxerr_en:1; + u64 rxbad_en:1; + u64 rxlock_en:1; + u64 an_bad_en:1; + u64 sync_bad_en:1; + u64 dup:1; + u64 reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_pcsx_intx_reg { + u64 u64; + struct cvmx_pcsx_intx_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 dbg_sync:1; + u64 dup:1; + u64 sync_bad:1; + u64 an_bad:1; + u64 rxlock:1; + u64 rxbad:1; + u64 rxerr:1; + u64 txbad:1; + u64 txfifo:1; + u64 txfifu:1; + u64 an_err:1; + u64 xmit:1; + u64 lnkspd:1; +#else + u64 lnkspd:1; + u64 xmit:1; + u64 an_err:1; + u64 txfifu:1; + u64 txfifo:1; + u64 txbad:1; + u64 rxerr:1; + u64 rxbad:1; + u64 rxlock:1; + u64 an_bad:1; + u64 sync_bad:1; + u64 dup:1; + u64 dbg_sync:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_pcsx_intx_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 dup:1; + u64 sync_bad:1; + u64 an_bad:1; + u64 rxlock:1; + u64 rxbad:1; + u64 rxerr:1; + u64 txbad:1; + u64 txfifo:1; + u64 txfifu:1; + u64 an_err:1; + u64 xmit:1; + u64 lnkspd:1; +#else + u64 lnkspd:1; + u64 xmit:1; + u64 an_err:1; + u64 txfifu:1; + u64 txfifo:1; + u64 txbad:1; + u64 rxerr:1; + u64 rxbad:1; + u64 rxlock:1; + u64 an_bad:1; + u64 sync_bad:1; + u64 dup:1; + u64 reserved_12_63:52; +#endif + } cn52xx; +}; + +union cvmx_pcsx_linkx_timer_count_reg { + u64 u64; + struct cvmx_pcsx_linkx_timer_count_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 count:16; +#else + u64 count:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_log_anlx_reg { + u64 u64; + struct cvmx_pcsx_log_anlx_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 lafifovfl:1; + u64 la_en:1; + u64 pkt_sz:2; +#else + u64 pkt_sz:2; + u64 la_en:1; + u64 lafifovfl:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_pcsx_miscx_ctl_reg { + u64 u64; + struct cvmx_pcsx_miscx_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 sgmii:1; + u64 gmxeno:1; + u64 loopbck2:1; + u64 mac_phy:1; + u64 mode:1; + u64 an_ovrd:1; + u64 samp_pt:7; +#else + u64 samp_pt:7; + u64 an_ovrd:1; + u64 mode:1; + u64 mac_phy:1; + u64 loopbck2:1; + u64 gmxeno:1; + u64 sgmii:1; + u64 reserved_13_63:51; +#endif + } s; +}; + +union cvmx_pcsx_mrx_control_reg { + u64 u64; + struct cvmx_pcsx_mrx_control_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 reset:1; + u64 loopbck1:1; + u64 spdlsb:1; + u64 an_en:1; + u64 pwr_dn:1; + u64 reserved_10_10:1; + u64 rst_an:1; + u64 dup:1; + u64 coltst:1; + u64 spdmsb:1; + u64 uni:1; + u64 reserved_0_4:5; +#else + u64 reserved_0_4:5; + u64 uni:1; + u64 spdmsb:1; + u64 coltst:1; + u64 dup:1; + u64 rst_an:1; + u64 reserved_10_10:1; + u64 pwr_dn:1; + u64 an_en:1; + u64 spdlsb:1; + u64 loopbck1:1; + u64 reset:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_mrx_status_reg { + u64 u64; + struct cvmx_pcsx_mrx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 hun_t4:1; + u64 hun_xfd:1; + u64 hun_xhd:1; + u64 ten_fd:1; + u64 ten_hd:1; + u64 hun_t2fd:1; + u64 hun_t2hd:1; + u64 ext_st:1; + u64 reserved_7_7:1; + u64 prb_sup:1; + u64 an_cpt:1; + u64 rm_flt:1; + u64 an_abil:1; + u64 lnk_st:1; + u64 reserved_1_1:1; + u64 extnd:1; +#else + u64 extnd:1; + u64 reserved_1_1:1; + u64 lnk_st:1; + u64 an_abil:1; + u64 rm_flt:1; + u64 an_cpt:1; + u64 prb_sup:1; + u64 reserved_7_7:1; + u64 ext_st:1; + u64 hun_t2hd:1; + u64 hun_t2fd:1; + u64 ten_hd:1; + u64 ten_fd:1; + u64 hun_xhd:1; + u64 hun_xfd:1; + u64 hun_t4:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_rxx_states_reg { + u64 u64; + struct cvmx_pcsx_rxx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 rx_bad:1; + u64 rx_st:5; + u64 sync_bad:1; + u64 sync:4; + u64 an_bad:1; + u64 an_st:4; +#else + u64 an_st:4; + u64 an_bad:1; + u64 sync:4; + u64 sync_bad:1; + u64 rx_st:5; + u64 rx_bad:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_rxx_sync_reg { + u64 u64; + struct cvmx_pcsx_rxx_sync_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 sync:1; + u64 bit_lock:1; +#else + u64 bit_lock:1; + u64 sync:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pcsx_sgmx_an_adv_reg { + u64 u64; + struct cvmx_pcsx_sgmx_an_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 link:1; + u64 ack:1; + u64 reserved_13_13:1; + u64 dup:1; + u64 speed:2; + u64 reserved_1_9:9; + u64 one:1; +#else + u64 one:1; + u64 reserved_1_9:9; + u64 speed:2; + u64 dup:1; + u64 reserved_13_13:1; + u64 ack:1; + u64 link:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_sgmx_lp_adv_reg { + u64 u64; + struct cvmx_pcsx_sgmx_lp_adv_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 link:1; + u64 reserved_13_14:2; + u64 dup:1; + u64 speed:2; + u64 reserved_1_9:9; + u64 one:1; +#else + u64 one:1; + u64 reserved_1_9:9; + u64 speed:2; + u64 dup:1; + u64 reserved_13_14:2; + u64 link:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsx_txx_states_reg { + u64 u64; + struct cvmx_pcsx_txx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 xmit:2; + u64 tx_bad:1; + u64 ord_st:4; +#else + u64 ord_st:4; + u64 tx_bad:1; + u64 xmit:2; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_pcsx_tx_rxx_polarity_reg { + u64 u64; + struct cvmx_pcsx_tx_rxx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 rxovrd:1; + u64 autorxpl:1; + u64 rxplrt:1; + u64 txplrt:1; +#else + u64 txplrt:1; + u64 rxplrt:1; + u64 autorxpl:1; + u64 rxovrd:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h new file mode 100644 index 000000000000..c40970842abc --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsxx-defs.h @@ -0,0 +1,663 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSXX_DEFS_H__ +#define __CVMX_PCSXX_DEFS_H__ + +static inline u64 CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_INT_EN_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_INT_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_STATUS1_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_STATUS2_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; +} + +static inline u64 CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CN56XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN52XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; + } + return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; +} + +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +union cvmx_pcsxx_10gbx_status_reg { + u64 u64; + struct cvmx_pcsxx_10gbx_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 alignd:1; + u64 pattst:1; + u64 reserved_4_10:7; + u64 l3sync:1; + u64 l2sync:1; + u64 l1sync:1; + u64 l0sync:1; +#else + u64 l0sync:1; + u64 l1sync:1; + u64 l2sync:1; + u64 l3sync:1; + u64 reserved_4_10:7; + u64 pattst:1; + u64 alignd:1; + u64 reserved_13_63:51; +#endif + } s; +}; + +union cvmx_pcsxx_bist_status_reg { + u64 u64; + struct cvmx_pcsxx_bist_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 bist_status:1; +#else + u64 bist_status:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_pcsxx_bit_lock_status_reg { + u64 u64; + struct cvmx_pcsxx_bit_lock_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 bitlck3:1; + u64 bitlck2:1; + u64 bitlck1:1; + u64 bitlck0:1; +#else + u64 bitlck0:1; + u64 bitlck1:1; + u64 bitlck2:1; + u64 bitlck3:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_pcsxx_control1_reg { + u64 u64; + struct cvmx_pcsxx_control1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 reset:1; + u64 loopbck1:1; + u64 spdsel1:1; + u64 reserved_12_12:1; + u64 lo_pwr:1; + u64 reserved_7_10:4; + u64 spdsel0:1; + u64 spd:4; + u64 reserved_0_1:2; +#else + u64 reserved_0_1:2; + u64 spd:4; + u64 spdsel0:1; + u64 reserved_7_10:4; + u64 lo_pwr:1; + u64 reserved_12_12:1; + u64 spdsel1:1; + u64 loopbck1:1; + u64 reset:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsxx_control2_reg { + u64 u64; + struct cvmx_pcsxx_control2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 type:2; +#else + u64 type:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pcsxx_int_en_reg { + u64 u64; + struct cvmx_pcsxx_int_en_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 dbg_sync_en:1; + u64 algnlos_en:1; + u64 synlos_en:1; + u64 bitlckls_en:1; + u64 rxsynbad_en:1; + u64 rxbad_en:1; + u64 txflt_en:1; +#else + u64 txflt_en:1; + u64 rxbad_en:1; + u64 rxsynbad_en:1; + u64 bitlckls_en:1; + u64 synlos_en:1; + u64 algnlos_en:1; + u64 dbg_sync_en:1; + u64 reserved_7_63:57; +#endif + } s; + struct cvmx_pcsxx_int_en_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 algnlos_en:1; + u64 synlos_en:1; + u64 bitlckls_en:1; + u64 rxsynbad_en:1; + u64 rxbad_en:1; + u64 txflt_en:1; +#else + u64 txflt_en:1; + u64 rxbad_en:1; + u64 rxsynbad_en:1; + u64 bitlckls_en:1; + u64 synlos_en:1; + u64 algnlos_en:1; + u64 reserved_6_63:58; +#endif + } cn52xx; +}; + +union cvmx_pcsxx_int_reg { + u64 u64; + struct cvmx_pcsxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 dbg_sync:1; + u64 algnlos:1; + u64 synlos:1; + u64 bitlckls:1; + u64 rxsynbad:1; + u64 rxbad:1; + u64 txflt:1; +#else + u64 txflt:1; + u64 rxbad:1; + u64 rxsynbad:1; + u64 bitlckls:1; + u64 synlos:1; + u64 algnlos:1; + u64 dbg_sync:1; + u64 reserved_7_63:57; +#endif + } s; + struct cvmx_pcsxx_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 algnlos:1; + u64 synlos:1; + u64 bitlckls:1; + u64 rxsynbad:1; + u64 rxbad:1; + u64 txflt:1; +#else + u64 txflt:1; + u64 rxbad:1; + u64 rxsynbad:1; + u64 bitlckls:1; + u64 synlos:1; + u64 algnlos:1; + u64 reserved_6_63:58; +#endif + } cn52xx; +}; + +union cvmx_pcsxx_log_anl_reg { + u64 u64; + struct cvmx_pcsxx_log_anl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 enc_mode:1; + u64 drop_ln:2; + u64 lafifovfl:1; + u64 la_en:1; + u64 pkt_sz:2; +#else + u64 pkt_sz:2; + u64 la_en:1; + u64 lafifovfl:1; + u64 drop_ln:2; + u64 enc_mode:1; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_pcsxx_misc_ctl_reg { + u64 u64; + struct cvmx_pcsxx_misc_ctl_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 tx_swap:1; + u64 rx_swap:1; + u64 xaui:1; + u64 gmxeno:1; +#else + u64 gmxeno:1; + u64 xaui:1; + u64 rx_swap:1; + u64 tx_swap:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_pcsxx_rx_sync_states_reg { + u64 u64; + struct cvmx_pcsxx_rx_sync_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 sync3st:4; + u64 sync2st:4; + u64 sync1st:4; + u64 sync0st:4; +#else + u64 sync0st:4; + u64 sync1st:4; + u64 sync2st:4; + u64 sync3st:4; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsxx_spd_abil_reg { + u64 u64; + struct cvmx_pcsxx_spd_abil_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 tenpasst:1; + u64 tengb:1; +#else + u64 tengb:1; + u64 tenpasst:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pcsxx_status1_reg { + u64 u64; + struct cvmx_pcsxx_status1_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 flt:1; + u64 reserved_3_6:4; + u64 rcv_lnk:1; + u64 lpable:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 lpable:1; + u64 rcv_lnk:1; + u64 reserved_3_6:4; + u64 flt:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pcsxx_status2_reg { + u64 u64; + struct cvmx_pcsxx_status2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 dev:2; + u64 reserved_12_13:2; + u64 xmtflt:1; + u64 rcvflt:1; + u64 reserved_3_9:7; + u64 tengb_w:1; + u64 tengb_x:1; + u64 tengb_r:1; +#else + u64 tengb_r:1; + u64 tengb_x:1; + u64 tengb_w:1; + u64 reserved_3_9:7; + u64 rcvflt:1; + u64 xmtflt:1; + u64 reserved_12_13:2; + u64 dev:2; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pcsxx_tx_rx_polarity_reg { + u64 u64; + struct cvmx_pcsxx_tx_rx_polarity_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 xor_rxplrt:4; + u64 xor_txplrt:4; + u64 rxplrt:1; + u64 txplrt:1; +#else + u64 txplrt:1; + u64 rxplrt:1; + u64 xor_txplrt:4; + u64 xor_rxplrt:4; + u64 reserved_10_63:54; +#endif + } s; + struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 rxplrt:1; + u64 txplrt:1; +#else + u64 txplrt:1; + u64 rxplrt:1; + u64 reserved_2_63:62; +#endif + } cn52xxp1; +}; + +union cvmx_pcsxx_tx_rx_states_reg { + u64 u64; + struct cvmx_pcsxx_tx_rx_states_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 term_err:1; + u64 syn3bad:1; + u64 syn2bad:1; + u64 syn1bad:1; + u64 syn0bad:1; + u64 rxbad:1; + u64 algn_st:3; + u64 rx_st:2; + u64 tx_st:3; +#else + u64 tx_st:3; + u64 rx_st:2; + u64 algn_st:3; + u64 rxbad:1; + u64 syn0bad:1; + u64 syn1bad:1; + u64 syn2bad:1; + u64 syn3bad:1; + u64 term_err:1; + u64 reserved_14_63:50; +#endif + } s; + struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 syn3bad:1; + u64 syn2bad:1; + u64 syn1bad:1; + u64 syn0bad:1; + u64 rxbad:1; + u64 algn_st:3; + u64 rx_st:2; + u64 tx_st:3; +#else + u64 tx_st:3; + u64 rx_st:2; + u64 algn_st:3; + u64 rxbad:1; + u64 syn0bad:1; + u64 syn1bad:1; + u64 syn2bad:1; + u64 syn3bad:1; + u64 reserved_13_63:51; +#endif + } cn52xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pemx-defs.h b/drivers/staging/octeon/cvmx-pemx-defs.h new file mode 100644 index 000000000000..fe70b4371dd2 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pemx-defs.h @@ -0,0 +1,650 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PEMX_DEFS_H__ +#define __CVMX_PEMX_DEFS_H__ + +#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) +#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull) +#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) +#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) +#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull) + +union cvmx_pemx_bar1_indexx { + u64 u64; + struct cvmx_pemx_bar1_indexx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 addr_idx:16; + u64 ca:1; + u64 end_swp:2; + u64 addr_v:1; +#else + u64 addr_v:1; + u64 end_swp:2; + u64 ca:1; + u64 addr_idx:16; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_pemx_bar2_mask { + u64 u64; + struct cvmx_pemx_bar2_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 mask:35; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 mask:35; + u64 reserved_38_63:26; +#endif + } s; +}; + +union cvmx_pemx_bar_ctl { + u64 u64; + struct cvmx_pemx_bar_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 bar1_siz:3; + u64 bar2_enb:1; + u64 bar2_esx:2; + u64 bar2_cax:1; +#else + u64 bar2_cax:1; + u64 bar2_esx:2; + u64 bar2_enb:1; + u64 bar1_siz:3; + u64 reserved_7_63:57; +#endif + } s; +}; + +union cvmx_pemx_bist_status { + u64 u64; + struct cvmx_pemx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 retry:1; + u64 rqdata0:1; + u64 rqdata1:1; + u64 rqdata2:1; + u64 rqdata3:1; + u64 rqhdr1:1; + u64 rqhdr0:1; + u64 sot:1; +#else + u64 sot:1; + u64 rqhdr0:1; + u64 rqhdr1:1; + u64 rqdata3:1; + u64 rqdata2:1; + u64 rqdata1:1; + u64 rqdata0:1; + u64 retry:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pemx_bist_status2 { + u64 u64; + struct cvmx_pemx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 e2p_cpl:1; + u64 e2p_n:1; + u64 e2p_p:1; + u64 peai_p2e:1; + u64 pef_tpf1:1; + u64 pef_tpf0:1; + u64 pef_tnf:1; + u64 pef_tcf1:1; + u64 pef_tc0:1; + u64 ppf:1; +#else + u64 ppf:1; + u64 pef_tc0:1; + u64 pef_tcf1:1; + u64 pef_tnf:1; + u64 pef_tpf0:1; + u64 pef_tpf1:1; + u64 peai_p2e:1; + u64 e2p_p:1; + u64 e2p_n:1; + u64 e2p_cpl:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_pemx_cfg_rd { + u64 u64; + struct cvmx_pemx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:32; + u64 addr:32; +#else + u64 addr:32; + u64 data:32; +#endif + } s; +}; + +union cvmx_pemx_cfg_wr { + u64 u64; + struct cvmx_pemx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:32; + u64 addr:32; +#else + u64 addr:32; + u64 data:32; +#endif + } s; +}; + +union cvmx_pemx_cpl_lut_valid { + u64 u64; + struct cvmx_pemx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 tag:32; +#else + u64 tag:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pemx_ctl_status { + u64 u64; + struct cvmx_pemx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 auto_sd:1; + u64 dnum:5; + u64 pbus:8; + u64 reserved_32_33:2; + u64 cfg_rtry:16; + u64 reserved_12_15:4; + u64 pm_xtoff:1; + u64 pm_xpme:1; + u64 ob_p_cmd:1; + u64 reserved_7_8:2; + u64 nf_ecrc:1; + u64 dly_one:1; + u64 lnk_enb:1; + u64 ro_ctlp:1; + u64 fast_lm:1; + u64 inv_ecrc:1; + u64 inv_lcrc:1; +#else + u64 inv_lcrc:1; + u64 inv_ecrc:1; + u64 fast_lm:1; + u64 ro_ctlp:1; + u64 lnk_enb:1; + u64 dly_one:1; + u64 nf_ecrc:1; + u64 reserved_7_8:2; + u64 ob_p_cmd:1; + u64 pm_xpme:1; + u64 pm_xtoff:1; + u64 reserved_12_15:4; + u64 cfg_rtry:16; + u64 reserved_32_33:2; + u64 pbus:8; + u64 dnum:5; + u64 auto_sd:1; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pemx_dbg_info { + u64 u64; + struct cvmx_pemx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 ecrc_e:1; + u64 rawwpp:1; + u64 racpp:1; + u64 ramtlp:1; + u64 rarwdns:1; + u64 caar:1; + u64 racca:1; + u64 racur:1; + u64 rauc:1; + u64 rqo:1; + u64 fcuv:1; + u64 rpe:1; + u64 fcpvwt:1; + u64 dpeoosd:1; + u64 rtwdle:1; + u64 rdwdle:1; + u64 mre:1; + u64 rte:1; + u64 acto:1; + u64 rvdm:1; + u64 rumep:1; + u64 rptamrc:1; + u64 rpmerc:1; + u64 rfemrc:1; + u64 rnfemrc:1; + u64 rcemrc:1; + u64 rpoison:1; + u64 recrce:1; + u64 rtlplle:1; + u64 rtlpmal:1; + u64 spoison:1; +#else + u64 spoison:1; + u64 rtlpmal:1; + u64 rtlplle:1; + u64 recrce:1; + u64 rpoison:1; + u64 rcemrc:1; + u64 rnfemrc:1; + u64 rfemrc:1; + u64 rpmerc:1; + u64 rptamrc:1; + u64 rumep:1; + u64 rvdm:1; + u64 acto:1; + u64 rte:1; + u64 mre:1; + u64 rdwdle:1; + u64 rtwdle:1; + u64 dpeoosd:1; + u64 fcpvwt:1; + u64 rpe:1; + u64 fcuv:1; + u64 rqo:1; + u64 rauc:1; + u64 racur:1; + u64 racca:1; + u64 caar:1; + u64 rarwdns:1; + u64 ramtlp:1; + u64 racpp:1; + u64 rawwpp:1; + u64 ecrc_e:1; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_pemx_dbg_info_en { + u64 u64; + struct cvmx_pemx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 ecrc_e:1; + u64 rawwpp:1; + u64 racpp:1; + u64 ramtlp:1; + u64 rarwdns:1; + u64 caar:1; + u64 racca:1; + u64 racur:1; + u64 rauc:1; + u64 rqo:1; + u64 fcuv:1; + u64 rpe:1; + u64 fcpvwt:1; + u64 dpeoosd:1; + u64 rtwdle:1; + u64 rdwdle:1; + u64 mre:1; + u64 rte:1; + u64 acto:1; + u64 rvdm:1; + u64 rumep:1; + u64 rptamrc:1; + u64 rpmerc:1; + u64 rfemrc:1; + u64 rnfemrc:1; + u64 rcemrc:1; + u64 rpoison:1; + u64 recrce:1; + u64 rtlplle:1; + u64 rtlpmal:1; + u64 spoison:1; +#else + u64 spoison:1; + u64 rtlpmal:1; + u64 rtlplle:1; + u64 recrce:1; + u64 rpoison:1; + u64 rcemrc:1; + u64 rnfemrc:1; + u64 rfemrc:1; + u64 rpmerc:1; + u64 rptamrc:1; + u64 rumep:1; + u64 rvdm:1; + u64 acto:1; + u64 rte:1; + u64 mre:1; + u64 rdwdle:1; + u64 rtwdle:1; + u64 dpeoosd:1; + u64 fcpvwt:1; + u64 rpe:1; + u64 fcuv:1; + u64 rqo:1; + u64 rauc:1; + u64 racur:1; + u64 racca:1; + u64 caar:1; + u64 rarwdns:1; + u64 ramtlp:1; + u64 racpp:1; + u64 rawwpp:1; + u64 ecrc_e:1; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_pemx_diag_status { + u64 u64; + struct cvmx_pemx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 pm_dst:1; + u64 pm_stat:1; + u64 pm_en:1; + u64 aux_en:1; +#else + u64 aux_en:1; + u64 pm_en:1; + u64 pm_stat:1; + u64 pm_dst:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_pemx_inb_read_credits { + u64 u64; + struct cvmx_pemx_inb_read_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 num:6; +#else + u64 num:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_pemx_int_enb { + u64 u64; + struct cvmx_pemx_int_enb_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 crs_dr:1; + u64 crs_er:1; + u64 rdlk:1; + u64 exc:1; + u64 un_bx:1; + u64 un_b2:1; + u64 un_b1:1; + u64 up_bx:1; + u64 up_b2:1; + u64 up_b1:1; + u64 pmem:1; + u64 pmei:1; + u64 se:1; + u64 aeri:1; +#else + u64 aeri:1; + u64 se:1; + u64 pmei:1; + u64 pmem:1; + u64 up_b1:1; + u64 up_b2:1; + u64 up_bx:1; + u64 un_b1:1; + u64 un_b2:1; + u64 un_bx:1; + u64 exc:1; + u64 rdlk:1; + u64 crs_er:1; + u64 crs_dr:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_pemx_int_enb_int { + u64 u64; + struct cvmx_pemx_int_enb_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 crs_dr:1; + u64 crs_er:1; + u64 rdlk:1; + u64 exc:1; + u64 un_bx:1; + u64 un_b2:1; + u64 un_b1:1; + u64 up_bx:1; + u64 up_b2:1; + u64 up_b1:1; + u64 pmem:1; + u64 pmei:1; + u64 se:1; + u64 aeri:1; +#else + u64 aeri:1; + u64 se:1; + u64 pmei:1; + u64 pmem:1; + u64 up_b1:1; + u64 up_b2:1; + u64 up_bx:1; + u64 un_b1:1; + u64 un_b2:1; + u64 un_bx:1; + u64 exc:1; + u64 rdlk:1; + u64 crs_er:1; + u64 crs_dr:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_pemx_int_sum { + u64 u64; + struct cvmx_pemx_int_sum_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 crs_dr:1; + u64 crs_er:1; + u64 rdlk:1; + u64 exc:1; + u64 un_bx:1; + u64 un_b2:1; + u64 un_b1:1; + u64 up_bx:1; + u64 up_b2:1; + u64 up_b1:1; + u64 pmem:1; + u64 pmei:1; + u64 se:1; + u64 aeri:1; +#else + u64 aeri:1; + u64 se:1; + u64 pmei:1; + u64 pmem:1; + u64 up_b1:1; + u64 up_b2:1; + u64 up_bx:1; + u64 un_b1:1; + u64 un_b2:1; + u64 un_bx:1; + u64 exc:1; + u64 rdlk:1; + u64 crs_er:1; + u64 crs_dr:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_pemx_p2n_bar0_start { + u64 u64; + struct cvmx_pemx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:50; + u64 reserved_0_13:14; +#else + u64 reserved_0_13:14; + u64 addr:50; +#endif + } s; +}; + +union cvmx_pemx_p2n_bar1_start { + u64 u64; + struct cvmx_pemx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:38; + u64 reserved_0_25:26; +#else + u64 reserved_0_25:26; + u64 addr:38; +#endif + } s; +}; + +union cvmx_pemx_p2n_bar2_start { + u64 u64; + struct cvmx_pemx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:23; + u64 reserved_0_40:41; +#else + u64 reserved_0_40:41; + u64 addr:23; +#endif + } s; +}; + +union cvmx_pemx_p2p_barx_end { + u64 u64; + struct cvmx_pemx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:52; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 addr:52; +#endif + } s; +}; + +union cvmx_pemx_p2p_barx_start { + u64 u64; + struct cvmx_pemx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:52; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 addr:52; +#endif + } s; +}; + +union cvmx_pemx_tlp_credits { + u64 u64; + struct cvmx_pemx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 peai_ppf:8; + u64 pem_cpl:8; + u64 pem_np:8; + u64 pem_p:8; + u64 sli_cpl:8; + u64 sli_np:8; + u64 sli_p:8; +#else + u64 sli_p:8; + u64 sli_np:8; + u64 sli_cpl:8; + u64 pem_p:8; + u64 pem_np:8; + u64 pem_cpl:8; + u64 peai_ppf:8; + u64 reserved_56_63:8; +#endif + } s; + struct cvmx_pemx_tlp_credits_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 peai_ppf:8; + u64 reserved_24_47:24; + u64 sli_cpl:8; + u64 sli_np:8; + u64 sli_p:8; +#else + u64 sli_p:8; + u64 sli_np:8; + u64 sli_cpl:8; + u64 reserved_24_47:24; + u64 peai_ppf:8; + u64 reserved_56_63:8; +#endif + } cn61xx; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pescx-defs.h b/drivers/staging/octeon/cvmx-pescx-defs.h new file mode 100644 index 000000000000..0e07a90b35d5 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pescx-defs.h @@ -0,0 +1,578 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PESCX_DEFS_H__ +#define __CVMX_PESCX_DEFS_H__ + +#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) +#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) +#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) + +union cvmx_pescx_bist_status { + u64 u64; + struct cvmx_pescx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 rqdata5:1; + u64 ctlp_or:1; + u64 ntlp_or:1; + u64 ptlp_or:1; + u64 retry:1; + u64 rqdata0:1; + u64 rqdata1:1; + u64 rqdata2:1; + u64 rqdata3:1; + u64 rqdata4:1; + u64 rqhdr1:1; + u64 rqhdr0:1; + u64 sot:1; +#else + u64 sot:1; + u64 rqhdr0:1; + u64 rqhdr1:1; + u64 rqdata4:1; + u64 rqdata3:1; + u64 rqdata2:1; + u64 rqdata1:1; + u64 rqdata0:1; + u64 retry:1; + u64 ptlp_or:1; + u64 ntlp_or:1; + u64 ctlp_or:1; + u64 rqdata5:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_pescx_bist_status_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 ctlp_or:1; + u64 ntlp_or:1; + u64 ptlp_or:1; + u64 retry:1; + u64 rqdata0:1; + u64 rqdata1:1; + u64 rqdata2:1; + u64 rqdata3:1; + u64 rqdata4:1; + u64 rqhdr1:1; + u64 rqhdr0:1; + u64 sot:1; +#else + u64 sot:1; + u64 rqhdr0:1; + u64 rqhdr1:1; + u64 rqdata4:1; + u64 rqdata3:1; + u64 rqdata2:1; + u64 rqdata1:1; + u64 rqdata0:1; + u64 retry:1; + u64 ptlp_or:1; + u64 ntlp_or:1; + u64 ctlp_or:1; + u64 reserved_12_63:52; +#endif + } cn52xxp1; +}; + +union cvmx_pescx_bist_status2 { + u64 u64; + struct cvmx_pescx_bist_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 cto_p2e:1; + u64 e2p_cpl:1; + u64 e2p_n:1; + u64 e2p_p:1; + u64 e2p_rsl:1; + u64 dbg_p2e:1; + u64 peai_p2e:1; + u64 rsl_p2e:1; + u64 pef_tpf1:1; + u64 pef_tpf0:1; + u64 pef_tnf:1; + u64 pef_tcf1:1; + u64 pef_tc0:1; + u64 ppf:1; +#else + u64 ppf:1; + u64 pef_tc0:1; + u64 pef_tcf1:1; + u64 pef_tnf:1; + u64 pef_tpf0:1; + u64 pef_tpf1:1; + u64 rsl_p2e:1; + u64 peai_p2e:1; + u64 dbg_p2e:1; + u64 e2p_rsl:1; + u64 e2p_p:1; + u64 e2p_n:1; + u64 e2p_cpl:1; + u64 cto_p2e:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_pescx_cfg_rd { + u64 u64; + struct cvmx_pescx_cfg_rd_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:32; + u64 addr:32; +#else + u64 addr:32; + u64 data:32; +#endif + } s; +}; + +union cvmx_pescx_cfg_wr { + u64 u64; + struct cvmx_pescx_cfg_wr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:32; + u64 addr:32; +#else + u64 addr:32; + u64 data:32; +#endif + } s; +}; + +union cvmx_pescx_cpl_lut_valid { + u64 u64; + struct cvmx_pescx_cpl_lut_valid_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 tag:32; +#else + u64 tag:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pescx_ctl_status { + u64 u64; + struct cvmx_pescx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 dnum:5; + u64 pbus:8; + u64 qlm_cfg:2; + u64 lane_swp:1; + u64 pm_xtoff:1; + u64 pm_xpme:1; + u64 ob_p_cmd:1; + u64 reserved_7_8:2; + u64 nf_ecrc:1; + u64 dly_one:1; + u64 lnk_enb:1; + u64 ro_ctlp:1; + u64 reserved_2_2:1; + u64 inv_ecrc:1; + u64 inv_lcrc:1; +#else + u64 inv_lcrc:1; + u64 inv_ecrc:1; + u64 reserved_2_2:1; + u64 ro_ctlp:1; + u64 lnk_enb:1; + u64 dly_one:1; + u64 nf_ecrc:1; + u64 reserved_7_8:2; + u64 ob_p_cmd:1; + u64 pm_xpme:1; + u64 pm_xtoff:1; + u64 lane_swp:1; + u64 qlm_cfg:2; + u64 pbus:8; + u64 dnum:5; + u64 reserved_28_63:36; +#endif + } s; + struct cvmx_pescx_ctl_status_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 dnum:5; + u64 pbus:8; + u64 qlm_cfg:2; + u64 reserved_12_12:1; + u64 pm_xtoff:1; + u64 pm_xpme:1; + u64 ob_p_cmd:1; + u64 reserved_7_8:2; + u64 nf_ecrc:1; + u64 dly_one:1; + u64 lnk_enb:1; + u64 ro_ctlp:1; + u64 reserved_2_2:1; + u64 inv_ecrc:1; + u64 inv_lcrc:1; +#else + u64 inv_lcrc:1; + u64 inv_ecrc:1; + u64 reserved_2_2:1; + u64 ro_ctlp:1; + u64 lnk_enb:1; + u64 dly_one:1; + u64 nf_ecrc:1; + u64 reserved_7_8:2; + u64 ob_p_cmd:1; + u64 pm_xpme:1; + u64 pm_xtoff:1; + u64 reserved_12_12:1; + u64 qlm_cfg:2; + u64 pbus:8; + u64 dnum:5; + u64 reserved_28_63:36; +#endif + } cn56xx; +}; + +union cvmx_pescx_ctl_status2 { + u64 u64; + struct cvmx_pescx_ctl_status2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 pclk_run:1; + u64 pcierst:1; +#else + u64 pcierst:1; + u64 pclk_run:1; + u64 reserved_2_63:62; +#endif + } s; + struct cvmx_pescx_ctl_status2_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 pcierst:1; +#else + u64 pcierst:1; + u64 reserved_1_63:63; +#endif + } cn52xxp1; +}; + +union cvmx_pescx_dbg_info { + u64 u64; + struct cvmx_pescx_dbg_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 ecrc_e:1; + u64 rawwpp:1; + u64 racpp:1; + u64 ramtlp:1; + u64 rarwdns:1; + u64 caar:1; + u64 racca:1; + u64 racur:1; + u64 rauc:1; + u64 rqo:1; + u64 fcuv:1; + u64 rpe:1; + u64 fcpvwt:1; + u64 dpeoosd:1; + u64 rtwdle:1; + u64 rdwdle:1; + u64 mre:1; + u64 rte:1; + u64 acto:1; + u64 rvdm:1; + u64 rumep:1; + u64 rptamrc:1; + u64 rpmerc:1; + u64 rfemrc:1; + u64 rnfemrc:1; + u64 rcemrc:1; + u64 rpoison:1; + u64 recrce:1; + u64 rtlplle:1; + u64 rtlpmal:1; + u64 spoison:1; +#else + u64 spoison:1; + u64 rtlpmal:1; + u64 rtlplle:1; + u64 recrce:1; + u64 rpoison:1; + u64 rcemrc:1; + u64 rnfemrc:1; + u64 rfemrc:1; + u64 rpmerc:1; + u64 rptamrc:1; + u64 rumep:1; + u64 rvdm:1; + u64 acto:1; + u64 rte:1; + u64 mre:1; + u64 rdwdle:1; + u64 rtwdle:1; + u64 dpeoosd:1; + u64 fcpvwt:1; + u64 rpe:1; + u64 fcuv:1; + u64 rqo:1; + u64 rauc:1; + u64 racur:1; + u64 racca:1; + u64 caar:1; + u64 rarwdns:1; + u64 ramtlp:1; + u64 racpp:1; + u64 rawwpp:1; + u64 ecrc_e:1; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_pescx_dbg_info_en { + u64 u64; + struct cvmx_pescx_dbg_info_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_31_63:33; + u64 ecrc_e:1; + u64 rawwpp:1; + u64 racpp:1; + u64 ramtlp:1; + u64 rarwdns:1; + u64 caar:1; + u64 racca:1; + u64 racur:1; + u64 rauc:1; + u64 rqo:1; + u64 fcuv:1; + u64 rpe:1; + u64 fcpvwt:1; + u64 dpeoosd:1; + u64 rtwdle:1; + u64 rdwdle:1; + u64 mre:1; + u64 rte:1; + u64 acto:1; + u64 rvdm:1; + u64 rumep:1; + u64 rptamrc:1; + u64 rpmerc:1; + u64 rfemrc:1; + u64 rnfemrc:1; + u64 rcemrc:1; + u64 rpoison:1; + u64 recrce:1; + u64 rtlplle:1; + u64 rtlpmal:1; + u64 spoison:1; +#else + u64 spoison:1; + u64 rtlpmal:1; + u64 rtlplle:1; + u64 recrce:1; + u64 rpoison:1; + u64 rcemrc:1; + u64 rnfemrc:1; + u64 rfemrc:1; + u64 rpmerc:1; + u64 rptamrc:1; + u64 rumep:1; + u64 rvdm:1; + u64 acto:1; + u64 rte:1; + u64 mre:1; + u64 rdwdle:1; + u64 rtwdle:1; + u64 dpeoosd:1; + u64 fcpvwt:1; + u64 rpe:1; + u64 fcuv:1; + u64 rqo:1; + u64 rauc:1; + u64 racur:1; + u64 racca:1; + u64 caar:1; + u64 rarwdns:1; + u64 ramtlp:1; + u64 racpp:1; + u64 rawwpp:1; + u64 ecrc_e:1; + u64 reserved_31_63:33; +#endif + } s; +}; + +union cvmx_pescx_diag_status { + u64 u64; + struct cvmx_pescx_diag_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 pm_dst:1; + u64 pm_stat:1; + u64 pm_en:1; + u64 aux_en:1; +#else + u64 aux_en:1; + u64 pm_en:1; + u64 pm_stat:1; + u64 pm_dst:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_pescx_p2n_bar0_start { + u64 u64; + struct cvmx_pescx_p2n_bar0_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:50; + u64 reserved_0_13:14; +#else + u64 reserved_0_13:14; + u64 addr:50; +#endif + } s; +}; + +union cvmx_pescx_p2n_bar1_start { + u64 u64; + struct cvmx_pescx_p2n_bar1_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:38; + u64 reserved_0_25:26; +#else + u64 reserved_0_25:26; + u64 addr:38; +#endif + } s; +}; + +union cvmx_pescx_p2n_bar2_start { + u64 u64; + struct cvmx_pescx_p2n_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:25; + u64 reserved_0_38:39; +#else + u64 reserved_0_38:39; + u64 addr:25; +#endif + } s; +}; + +union cvmx_pescx_p2p_barx_end { + u64 u64; + struct cvmx_pescx_p2p_barx_end_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:52; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 addr:52; +#endif + } s; +}; + +union cvmx_pescx_p2p_barx_start { + u64 u64; + struct cvmx_pescx_p2p_barx_start_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 addr:52; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 addr:52; +#endif + } s; +}; + +union cvmx_pescx_tlp_credits { + u64 u64; + struct cvmx_pescx_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pescx_tlp_credits_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 peai_ppf:8; + u64 pesc_cpl:8; + u64 pesc_np:8; + u64 pesc_p:8; + u64 npei_cpl:8; + u64 npei_np:8; + u64 npei_p:8; +#else + u64 npei_p:8; + u64 npei_np:8; + u64 npei_cpl:8; + u64 pesc_p:8; + u64 pesc_np:8; + u64 pesc_cpl:8; + u64 peai_ppf:8; + u64 reserved_56_63:8; +#endif + } cn52xx; + struct cvmx_pescx_tlp_credits_cn52xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_38_63:26; + u64 peai_ppf:8; + u64 pesc_cpl:5; + u64 pesc_np:5; + u64 pesc_p:5; + u64 npei_cpl:5; + u64 npei_np:5; + u64 npei_p:5; +#else + u64 npei_p:5; + u64 npei_np:5; + u64 npei_cpl:5; + u64 pesc_p:5; + u64 pesc_np:5; + u64 pesc_cpl:5; + u64 peai_ppf:8; + u64 reserved_38_63:26; +#endif + } cn52xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pexp-defs.h b/drivers/staging/octeon/cvmx-pexp-defs.h new file mode 100644 index 000000000000..8ce61646c114 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pexp-defs.h @@ -0,0 +1,223 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PEXP_DEFS_H__ +#define __CVMX_PEXP_DEFS_H__ + +#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull)) +#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) +#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull)) +#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull)) +#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull)) +#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull)) +#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull)) +#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull)) +#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull)) +#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull)) +#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull)) +#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull)) +#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull)) +#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull)) +#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) +#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) +#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull)) +#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) +#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) +#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) +#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) +#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull)) +#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)) +#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull)) +#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull)) +#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)) +#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull)) +#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull)) +#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)) +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull)) +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull)) +#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull)) +#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16 * 12) +#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull)) +#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull)) +#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull)) +#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull)) +#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull)) +#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull)) +#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull)) +#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull)) +#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull)) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull)) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull)) +#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull)) +#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull)) +#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull)) +#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull)) +#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull)) +#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull)) +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)) +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull)) +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull)) +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull)) +#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull)) +#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull)) +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull)) +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull)) +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull)) +#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull)) +#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull)) +#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull)) +#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull)) +#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull)) +#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull)) +#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) +#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) +#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull)) +#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull)) +#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull)) +#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull)) +#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull)) +#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull)) +#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) +#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull)) +#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull)) +#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull)) +#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull)) +#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull)) +#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull)) +#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull)) +#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull)) +#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull)) +#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull)) +#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) +#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) +#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) +#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16) +#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) +#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) +#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) +#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull)) +#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull)) +#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16) +#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull)) +#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull)) +#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) +#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull)) +#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) +#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16 * 12) +#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) +#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull)) +#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull)) +#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull)) +#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull)) +#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull)) +#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull)) +#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull)) +#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull)) +#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull)) +#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull)) +#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull)) +#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull)) +#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull)) +#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull)) +#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull)) +#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull)) +#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull)) +#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull)) +#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull)) +#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull)) +#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull)) +#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull)) +#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull)) +#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull)) +#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull)) +#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull)) +#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull)) +#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull)) +#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull)) +#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull)) +#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull)) +#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull)) +#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull)) +#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull)) +#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull)) +#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull)) +#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) +#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) +#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) +#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull)) +#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) +#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) +#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) +#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull)) +#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull)) +#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) +#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) +#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) +#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16) +#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16) +#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) +#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) +#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) +#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) +#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) +#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull)) +#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) + +#endif diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/drivers/staging/octeon/cvmx-pip-defs.h new file mode 100644 index 000000000000..e5b3c5fa8d69 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pip-defs.h @@ -0,0 +1,2733 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PIP_DEFS_H__ +#define __CVMX_PIP_DEFS_H__ + +/* + * Enumeration representing the amount of packet processing + * and validation performed by the input hardware. + */ +enum cvmx_pip_port_parse_mode { + /* + * Packet input doesn't perform any processing of the input + * packet. + */ + CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, + /* + * Full packet processing is performed with pointer starting + * at the L2 (ethernet MAC) header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, + /* + * Input packets are assumed to be IP. Results from non IP + * packets is undefined. Pointers reference the beginning of + * the IP header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull +}; + +#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) +#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) +#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) +#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) +#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) +#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) +#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) +#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) +#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) +#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) +#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) +#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) +#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) +#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) +#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) +#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) +#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) +#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) +#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) +#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) +#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) +#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) +#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) +#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) +#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) +#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) +#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) +#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) +#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) +#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) +#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) +#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) +#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) +#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) +#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16 * 40) +#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16 * 40) +#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80 * 40) +#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80 * 40) + +union cvmx_pip_alt_skip_cfgx { + u64 u64; + struct cvmx_pip_alt_skip_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_57_63:7; + u64 len:1; + u64 reserved_46_55:10; + u64 bit1:6; + u64 reserved_38_39:2; + u64 bit0:6; + u64 reserved_23_31:9; + u64 skip3:7; + u64 reserved_15_15:1; + u64 skip2:7; + u64 reserved_7_7:1; + u64 skip1:7; +#else + u64 skip1:7; + u64 reserved_7_7:1; + u64 skip2:7; + u64 reserved_15_15:1; + u64 skip3:7; + u64 reserved_23_31:9; + u64 bit0:6; + u64 reserved_38_39:2; + u64 bit1:6; + u64 reserved_46_55:10; + u64 len:1; + u64 reserved_57_63:7; +#endif + } s; +}; + +union cvmx_pip_bck_prs { + u64 u64; + struct cvmx_pip_bck_prs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bckprs:1; + u64 reserved_13_62:50; + u64 hiwater:5; + u64 reserved_5_7:3; + u64 lowater:5; +#else + u64 lowater:5; + u64 reserved_5_7:3; + u64 hiwater:5; + u64 reserved_13_62:50; + u64 bckprs:1; +#endif + } s; +}; + +union cvmx_pip_bist_status { + u64 u64; + struct cvmx_pip_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 bist:22; +#else + u64 bist:22; + u64 reserved_22_63:42; +#endif + } s; + struct cvmx_pip_bist_status_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 bist:18; +#else + u64 bist:18; + u64 reserved_18_63:46; +#endif + } cn30xx; + struct cvmx_pip_bist_status_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 bist:17; +#else + u64 bist:17; + u64 reserved_17_63:47; +#endif + } cn50xx; + struct cvmx_pip_bist_status_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 bist:20; +#else + u64 bist:20; + u64 reserved_20_63:44; +#endif + } cn61xx; +}; + +union cvmx_pip_bsel_ext_cfgx { + u64 u64; + struct cvmx_pip_bsel_ext_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 upper_tag:16; + u64 tag:8; + u64 reserved_25_31:7; + u64 offset:9; + u64 reserved_7_15:9; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_15:9; + u64 offset:9; + u64 reserved_25_31:7; + u64 tag:8; + u64 upper_tag:16; + u64 reserved_56_63:8; +#endif + } s; +}; + +union cvmx_pip_bsel_ext_posx { + u64 u64; + struct cvmx_pip_bsel_ext_posx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pos7_val:1; + u64 pos7:7; + u64 pos6_val:1; + u64 pos6:7; + u64 pos5_val:1; + u64 pos5:7; + u64 pos4_val:1; + u64 pos4:7; + u64 pos3_val:1; + u64 pos3:7; + u64 pos2_val:1; + u64 pos2:7; + u64 pos1_val:1; + u64 pos1:7; + u64 pos0_val:1; + u64 pos0:7; +#else + u64 pos0:7; + u64 pos0_val:1; + u64 pos1:7; + u64 pos1_val:1; + u64 pos2:7; + u64 pos2_val:1; + u64 pos3:7; + u64 pos3_val:1; + u64 pos4:7; + u64 pos4_val:1; + u64 pos5:7; + u64 pos5_val:1; + u64 pos6:7; + u64 pos6_val:1; + u64 pos7:7; + u64 pos7_val:1; +#endif + } s; +}; + +union cvmx_pip_bsel_tbl_entx { + u64 u64; + struct cvmx_pip_bsel_tbl_entx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 tag_en:1; + u64 grp_en:1; + u64 tt_en:1; + u64 qos_en:1; + u64 reserved_40_59:20; + u64 tag:8; + u64 reserved_22_31:10; + u64 grp:6; + u64 reserved_10_15:6; + u64 tt:2; + u64 reserved_3_7:5; + u64 qos:3; +#else + u64 qos:3; + u64 reserved_3_7:5; + u64 tt:2; + u64 reserved_10_15:6; + u64 grp:6; + u64 reserved_22_31:10; + u64 tag:8; + u64 reserved_40_59:20; + u64 qos_en:1; + u64 tt_en:1; + u64 grp_en:1; + u64 tag_en:1; +#endif + } s; + struct cvmx_pip_bsel_tbl_entx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 tag_en:1; + u64 grp_en:1; + u64 tt_en:1; + u64 qos_en:1; + u64 reserved_40_59:20; + u64 tag:8; + u64 reserved_20_31:12; + u64 grp:4; + u64 reserved_10_15:6; + u64 tt:2; + u64 reserved_3_7:5; + u64 qos:3; +#else + u64 qos:3; + u64 reserved_3_7:5; + u64 tt:2; + u64 reserved_10_15:6; + u64 grp:4; + u64 reserved_20_31:12; + u64 tag:8; + u64 reserved_40_59:20; + u64 qos_en:1; + u64 tt_en:1; + u64 grp_en:1; + u64 tag_en:1; +#endif + } cn61xx; +}; + +union cvmx_pip_clken { + u64 u64; + struct cvmx_pip_clken_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 clken:1; +#else + u64 clken:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_pip_crc_ctlx { + u64 u64; + struct cvmx_pip_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 invres:1; + u64 reflect:1; +#else + u64 reflect:1; + u64 invres:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pip_crc_ivx { + u64 u64; + struct cvmx_pip_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iv:32; +#else + u64 iv:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pip_dec_ipsecx { + u64 u64; + struct cvmx_pip_dec_ipsecx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 tcp:1; + u64 udp:1; + u64 dprt:16; +#else + u64 dprt:16; + u64 udp:1; + u64 tcp:1; + u64 reserved_18_63:46; +#endif + } s; +}; + +union cvmx_pip_dsa_src_grp { + u64 u64; + struct cvmx_pip_dsa_src_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 map15:4; + u64 map14:4; + u64 map13:4; + u64 map12:4; + u64 map11:4; + u64 map10:4; + u64 map9:4; + u64 map8:4; + u64 map7:4; + u64 map6:4; + u64 map5:4; + u64 map4:4; + u64 map3:4; + u64 map2:4; + u64 map1:4; + u64 map0:4; +#else + u64 map0:4; + u64 map1:4; + u64 map2:4; + u64 map3:4; + u64 map4:4; + u64 map5:4; + u64 map6:4; + u64 map7:4; + u64 map8:4; + u64 map9:4; + u64 map10:4; + u64 map11:4; + u64 map12:4; + u64 map13:4; + u64 map14:4; + u64 map15:4; +#endif + } s; +}; + +union cvmx_pip_dsa_vid_grp { + u64 u64; + struct cvmx_pip_dsa_vid_grp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 map15:4; + u64 map14:4; + u64 map13:4; + u64 map12:4; + u64 map11:4; + u64 map10:4; + u64 map9:4; + u64 map8:4; + u64 map7:4; + u64 map6:4; + u64 map5:4; + u64 map4:4; + u64 map3:4; + u64 map2:4; + u64 map1:4; + u64 map0:4; +#else + u64 map0:4; + u64 map1:4; + u64 map2:4; + u64 map3:4; + u64 map4:4; + u64 map5:4; + u64 map6:4; + u64 map7:4; + u64 map8:4; + u64 map9:4; + u64 map10:4; + u64 map11:4; + u64 map12:4; + u64 map13:4; + u64 map14:4; + u64 map15:4; +#endif + } s; +}; + +union cvmx_pip_frm_len_chkx { + u64 u64; + struct cvmx_pip_frm_len_chkx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 maxlen:16; + u64 minlen:16; +#else + u64 minlen:16; + u64 maxlen:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pip_gbl_cfg { + u64 u64; + struct cvmx_pip_gbl_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 tag_syn:1; + u64 ip6_udp:1; + u64 max_l2:1; + u64 reserved_11_15:5; + u64 raw_shf:3; + u64 reserved_3_7:5; + u64 nip_shf:3; +#else + u64 nip_shf:3; + u64 reserved_3_7:5; + u64 raw_shf:3; + u64 reserved_11_15:5; + u64 max_l2:1; + u64 ip6_udp:1; + u64 tag_syn:1; + u64 reserved_19_63:45; +#endif + } s; +}; + +union cvmx_pip_gbl_ctl { + u64 u64; + struct cvmx_pip_gbl_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 egrp_dis:1; + u64 ihmsk_dis:1; + u64 dsa_grp_tvid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_sid:1; + u64 reserved_21_23:3; + u64 ring_en:1; + u64 reserved_17_19:3; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_19:3; + u64 ring_en:1; + u64 reserved_21_23:3; + u64 dsa_grp_sid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_tvid:1; + u64 ihmsk_dis:1; + u64 egrp_dis:1; + u64 reserved_29_63:35; +#endif + } s; + struct cvmx_pip_gbl_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_63:47; +#endif + } cn30xx; + struct cvmx_pip_gbl_ctl_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 dsa_grp_tvid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_sid:1; + u64 reserved_21_23:3; + u64 ring_en:1; + u64 reserved_17_19:3; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_19:3; + u64 ring_en:1; + u64 reserved_21_23:3; + u64 dsa_grp_sid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_tvid:1; + u64 reserved_27_63:37; +#endif + } cn52xx; + struct cvmx_pip_gbl_ctl_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_21_63:43; + u64 ring_en:1; + u64 reserved_17_19:3; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_19:3; + u64 ring_en:1; + u64 reserved_21_63:43; +#endif + } cn56xxp1; + struct cvmx_pip_gbl_ctl_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 ihmsk_dis:1; + u64 dsa_grp_tvid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_sid:1; + u64 reserved_21_23:3; + u64 ring_en:1; + u64 reserved_17_19:3; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_19:3; + u64 ring_en:1; + u64 reserved_21_23:3; + u64 dsa_grp_sid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_tvid:1; + u64 ihmsk_dis:1; + u64 reserved_28_63:36; +#endif + } cn61xx; + struct cvmx_pip_gbl_ctl_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 egrp_dis:1; + u64 ihmsk_dis:1; + u64 dsa_grp_tvid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_sid:1; + u64 reserved_17_23:7; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_23:7; + u64 dsa_grp_sid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_tvid:1; + u64 ihmsk_dis:1; + u64 egrp_dis:1; + u64 reserved_29_63:35; +#endif + } cn68xx; + struct cvmx_pip_gbl_ctl_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 ihmsk_dis:1; + u64 dsa_grp_tvid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_sid:1; + u64 reserved_17_23:7; + u64 ignrs:1; + u64 vs_wqe:1; + u64 vs_qos:1; + u64 l2_mal:1; + u64 tcp_flag:1; + u64 l4_len:1; + u64 l4_chk:1; + u64 l4_prt:1; + u64 l4_mal:1; + u64 reserved_6_7:2; + u64 ip6_eext:2; + u64 ip4_opts:1; + u64 ip_hop:1; + u64 ip_mal:1; + u64 ip_chk:1; +#else + u64 ip_chk:1; + u64 ip_mal:1; + u64 ip_hop:1; + u64 ip4_opts:1; + u64 ip6_eext:2; + u64 reserved_6_7:2; + u64 l4_mal:1; + u64 l4_prt:1; + u64 l4_chk:1; + u64 l4_len:1; + u64 tcp_flag:1; + u64 l2_mal:1; + u64 vs_qos:1; + u64 vs_wqe:1; + u64 ignrs:1; + u64 reserved_17_23:7; + u64 dsa_grp_sid:1; + u64 dsa_grp_scmd:1; + u64 dsa_grp_tvid:1; + u64 ihmsk_dis:1; + u64 reserved_28_63:36; +#endif + } cn68xxp1; +}; + +union cvmx_pip_hg_pri_qos { + u64 u64; + struct cvmx_pip_hg_pri_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 up_qos:1; + u64 reserved_11_11:1; + u64 qos:3; + u64 reserved_6_7:2; + u64 pri:6; +#else + u64 pri:6; + u64 reserved_6_7:2; + u64 qos:3; + u64 reserved_11_11:1; + u64 up_qos:1; + u64 reserved_13_63:51; +#endif + } s; +}; + +union cvmx_pip_int_en { + u64 u64; + struct cvmx_pip_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_pip_int_en_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_pip_int_en_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 reserved_1_1:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 reserved_1_1:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 reserved_12_63:52; +#endif + } cn50xx; + struct cvmx_pip_int_en_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 reserved_1_1:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 reserved_1_1:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } cn52xx; + struct cvmx_pip_int_en_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 reserved_12_63:52; +#endif + } cn56xxp1; + struct cvmx_pip_int_en_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 reserved_9_11:3; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 reserved_9_11:3; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } cn58xx; +}; + +union cvmx_pip_int_reg { + u64 u64; + struct cvmx_pip_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } s; + struct cvmx_pip_int_reg_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 reserved_9_63:55; +#endif + } cn30xx; + struct cvmx_pip_int_reg_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 reserved_1_1:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 reserved_1_1:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 reserved_12_63:52; +#endif + } cn50xx; + struct cvmx_pip_int_reg_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 reserved_1_1:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 reserved_1_1:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } cn52xx; + struct cvmx_pip_int_reg_cn56xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 lenerr:1; + u64 maxerr:1; + u64 minerr:1; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 minerr:1; + u64 maxerr:1; + u64 lenerr:1; + u64 reserved_12_63:52; +#endif + } cn56xxp1; + struct cvmx_pip_int_reg_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 punyerr:1; + u64 reserved_9_11:3; + u64 beperr:1; + u64 feperr:1; + u64 todoovr:1; + u64 skprunt:1; + u64 badtag:1; + u64 prtnxa:1; + u64 bckprs:1; + u64 crcerr:1; + u64 pktdrp:1; +#else + u64 pktdrp:1; + u64 crcerr:1; + u64 bckprs:1; + u64 prtnxa:1; + u64 badtag:1; + u64 skprunt:1; + u64 todoovr:1; + u64 feperr:1; + u64 beperr:1; + u64 reserved_9_11:3; + u64 punyerr:1; + u64 reserved_13_63:51; +#endif + } cn58xx; +}; + +union cvmx_pip_ip_offset { + u64 u64; + struct cvmx_pip_ip_offset_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 offset:3; +#else + u64 offset:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_pip_pri_tblx { + u64 u64; + struct cvmx_pip_pri_tblx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 diff2_padd:8; + u64 hg2_padd:8; + u64 vlan2_padd:8; + u64 reserved_38_39:2; + u64 diff2_bpid:6; + u64 reserved_30_31:2; + u64 hg2_bpid:6; + u64 reserved_22_23:2; + u64 vlan2_bpid:6; + u64 reserved_11_15:5; + u64 diff2_qos:3; + u64 reserved_7_7:1; + u64 hg2_qos:3; + u64 reserved_3_3:1; + u64 vlan2_qos:3; +#else + u64 vlan2_qos:3; + u64 reserved_3_3:1; + u64 hg2_qos:3; + u64 reserved_7_7:1; + u64 diff2_qos:3; + u64 reserved_11_15:5; + u64 vlan2_bpid:6; + u64 reserved_22_23:2; + u64 hg2_bpid:6; + u64 reserved_30_31:2; + u64 diff2_bpid:6; + u64 reserved_38_39:2; + u64 vlan2_padd:8; + u64 hg2_padd:8; + u64 diff2_padd:8; +#endif + } s; +}; + +union cvmx_pip_prt_cfgx { + u64 u64; + struct cvmx_pip_prt_cfgx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_55_63:9; + u64 ih_pri:1; + u64 len_chk_sel:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 lenerr_en:1; + u64 maxerr_en:1; + u64 minerr_en:1; + u64 grp_wat_47:4; + u64 qos_wat_47:4; + u64 reserved_37_39:3; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 hg_qos:1; + u64 qos:3; + u64 qos_wat:4; + u64 qos_vsel:1; + u64 qos_vod:1; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 higig_en:1; + u64 dsa_en:1; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 dsa_en:1; + u64 higig_en:1; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 qos_vod:1; + u64 qos_vsel:1; + u64 qos_wat:4; + u64 qos:3; + u64 hg_qos:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_39:3; + u64 qos_wat_47:4; + u64 grp_wat_47:4; + u64 minerr_en:1; + u64 maxerr_en:1; + u64 lenerr_en:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 len_chk_sel:1; + u64 ih_pri:1; + u64 reserved_55_63:9; +#endif + } s; + struct cvmx_pip_prt_cfgx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 reserved_27_27:1; + u64 qos:3; + u64 qos_wat:4; + u64 reserved_18_19:2; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_10_15:6; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 reserved_10_15:6; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 reserved_18_19:2; + u64 qos_wat:4; + u64 qos:3; + u64 reserved_27_27:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_63:27; +#endif + } cn30xx; + struct cvmx_pip_prt_cfgx_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 reserved_27_27:1; + u64 qos:3; + u64 qos_wat:4; + u64 reserved_18_19:2; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 reserved_10_11:2; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 reserved_10_11:2; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 reserved_18_19:2; + u64 qos_wat:4; + u64 qos:3; + u64 reserved_27_27:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_63:27; +#endif + } cn38xx; + struct cvmx_pip_prt_cfgx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_53_63:11; + u64 pad_len:1; + u64 vlan_len:1; + u64 lenerr_en:1; + u64 maxerr_en:1; + u64 minerr_en:1; + u64 grp_wat_47:4; + u64 qos_wat_47:4; + u64 reserved_37_39:3; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 reserved_27_27:1; + u64 qos:3; + u64 qos_wat:4; + u64 reserved_19_19:1; + u64 qos_vod:1; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 reserved_10_11:2; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 reserved_10_11:2; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 qos_vod:1; + u64 reserved_19_19:1; + u64 qos_wat:4; + u64 qos:3; + u64 reserved_27_27:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_39:3; + u64 qos_wat_47:4; + u64 grp_wat_47:4; + u64 minerr_en:1; + u64 maxerr_en:1; + u64 lenerr_en:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 reserved_53_63:11; +#endif + } cn50xx; + struct cvmx_pip_prt_cfgx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_53_63:11; + u64 pad_len:1; + u64 vlan_len:1; + u64 lenerr_en:1; + u64 maxerr_en:1; + u64 minerr_en:1; + u64 grp_wat_47:4; + u64 qos_wat_47:4; + u64 reserved_37_39:3; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 hg_qos:1; + u64 qos:3; + u64 qos_wat:4; + u64 qos_vsel:1; + u64 qos_vod:1; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 higig_en:1; + u64 dsa_en:1; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 dsa_en:1; + u64 higig_en:1; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 qos_vod:1; + u64 qos_vsel:1; + u64 qos_wat:4; + u64 qos:3; + u64 hg_qos:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_39:3; + u64 qos_wat_47:4; + u64 grp_wat_47:4; + u64 minerr_en:1; + u64 maxerr_en:1; + u64 lenerr_en:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 reserved_53_63:11; +#endif + } cn52xx; + struct cvmx_pip_prt_cfgx_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 reserved_27_27:1; + u64 qos:3; + u64 qos_wat:4; + u64 reserved_19_19:1; + u64 qos_vod:1; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 reserved_10_11:2; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 reserved_10_11:2; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 qos_vod:1; + u64 reserved_19_19:1; + u64 qos_wat:4; + u64 qos:3; + u64 reserved_27_27:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_63:27; +#endif + } cn58xx; + struct cvmx_pip_prt_cfgx_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_55_63:9; + u64 ih_pri:1; + u64 len_chk_sel:1; + u64 pad_len:1; + u64 vlan_len:1; + u64 lenerr_en:1; + u64 maxerr_en:1; + u64 minerr_en:1; + u64 grp_wat_47:4; + u64 qos_wat_47:4; + u64 reserved_37_39:3; + u64 rawdrp:1; + u64 tag_inc:2; + u64 dyn_rs:1; + u64 inst_hdr:1; + u64 grp_wat:4; + u64 hg_qos:1; + u64 qos:3; + u64 qos_wat:4; + u64 reserved_19_19:1; + u64 qos_vod:1; + u64 qos_diff:1; + u64 qos_vlan:1; + u64 reserved_13_15:3; + u64 crc_en:1; + u64 higig_en:1; + u64 dsa_en:1; + u64 mode:2; + u64 reserved_7_7:1; + u64 skip:7; +#else + u64 skip:7; + u64 reserved_7_7:1; + u64 mode:2; + u64 dsa_en:1; + u64 higig_en:1; + u64 crc_en:1; + u64 reserved_13_15:3; + u64 qos_vlan:1; + u64 qos_diff:1; + u64 qos_vod:1; + u64 reserved_19_19:1; + u64 qos_wat:4; + u64 qos:3; + u64 hg_qos:1; + u64 grp_wat:4; + u64 inst_hdr:1; + u64 dyn_rs:1; + u64 tag_inc:2; + u64 rawdrp:1; + u64 reserved_37_39:3; + u64 qos_wat_47:4; + u64 grp_wat_47:4; + u64 minerr_en:1; + u64 maxerr_en:1; + u64 lenerr_en:1; + u64 vlan_len:1; + u64 pad_len:1; + u64 len_chk_sel:1; + u64 ih_pri:1; + u64 reserved_55_63:9; +#endif + } cn68xx; +}; + +union cvmx_pip_prt_cfgbx { + u64 u64; + struct cvmx_pip_prt_cfgbx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 alt_skp_sel:2; + u64 alt_skp_en:1; + u64 reserved_35_35:1; + u64 bsel_num:2; + u64 bsel_en:1; + u64 reserved_24_31:8; + u64 base:8; + u64 reserved_6_15:10; + u64 bpid:6; +#else + u64 bpid:6; + u64 reserved_6_15:10; + u64 base:8; + u64 reserved_24_31:8; + u64 bsel_en:1; + u64 bsel_num:2; + u64 reserved_35_35:1; + u64 alt_skp_en:1; + u64 alt_skp_sel:2; + u64 reserved_39_63:25; +#endif + } s; + struct cvmx_pip_prt_cfgbx_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 alt_skp_sel:2; + u64 alt_skp_en:1; + u64 reserved_35_35:1; + u64 bsel_num:2; + u64 bsel_en:1; + u64 reserved_0_31:32; +#else + u64 reserved_0_31:32; + u64 bsel_en:1; + u64 bsel_num:2; + u64 reserved_35_35:1; + u64 alt_skp_en:1; + u64 alt_skp_sel:2; + u64 reserved_39_63:25; +#endif + } cn61xx; + struct cvmx_pip_prt_cfgbx_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + u64 alt_skp_sel:2; + u64 alt_skp_en:1; + u64 reserved_0_35:36; +#else + u64 reserved_0_35:36; + u64 alt_skp_en:1; + u64 alt_skp_sel:2; + u64 reserved_39_63:25; +#endif + } cn66xx; + struct cvmx_pip_prt_cfgbx_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 base:8; + u64 reserved_6_15:10; + u64 bpid:6; +#else + u64 bpid:6; + u64 reserved_6_15:10; + u64 base:8; + u64 reserved_24_63:40; +#endif + } cn68xxp1; +}; + +union cvmx_pip_prt_tagx { + u64 u64; + struct cvmx_pip_prt_tagx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 portadd_en:1; + u64 inc_hwchk:1; + u64 reserved_50_51:2; + u64 grptagbase_msb:2; + u64 reserved_46_47:2; + u64 grptagmask_msb:2; + u64 reserved_42_43:2; + u64 grp_msb:2; + u64 grptagbase:4; + u64 grptagmask:4; + u64 grptag:1; + u64 grptag_mskip:1; + u64 tag_mode:2; + u64 inc_vs:2; + u64 inc_vlan:1; + u64 inc_prt_flag:1; + u64 ip6_dprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_src_flag:1; + u64 ip4_src_flag:1; + u64 tcp6_tag_type:2; + u64 tcp4_tag_type:2; + u64 ip6_tag_type:2; + u64 ip4_tag_type:2; + u64 non_tag_type:2; + u64 grp:4; +#else + u64 grp:4; + u64 non_tag_type:2; + u64 ip4_tag_type:2; + u64 ip6_tag_type:2; + u64 tcp4_tag_type:2; + u64 tcp6_tag_type:2; + u64 ip4_src_flag:1; + u64 ip6_src_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_dprt_flag:1; + u64 inc_prt_flag:1; + u64 inc_vlan:1; + u64 inc_vs:2; + u64 tag_mode:2; + u64 grptag_mskip:1; + u64 grptag:1; + u64 grptagmask:4; + u64 grptagbase:4; + u64 grp_msb:2; + u64 reserved_42_43:2; + u64 grptagmask_msb:2; + u64 reserved_46_47:2; + u64 grptagbase_msb:2; + u64 reserved_50_51:2; + u64 inc_hwchk:1; + u64 portadd_en:1; + u64 reserved_54_63:10; +#endif + } s; + struct cvmx_pip_prt_tagx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 grptagbase:4; + u64 grptagmask:4; + u64 grptag:1; + u64 reserved_30_30:1; + u64 tag_mode:2; + u64 inc_vs:2; + u64 inc_vlan:1; + u64 inc_prt_flag:1; + u64 ip6_dprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_src_flag:1; + u64 ip4_src_flag:1; + u64 tcp6_tag_type:2; + u64 tcp4_tag_type:2; + u64 ip6_tag_type:2; + u64 ip4_tag_type:2; + u64 non_tag_type:2; + u64 grp:4; +#else + u64 grp:4; + u64 non_tag_type:2; + u64 ip4_tag_type:2; + u64 ip6_tag_type:2; + u64 tcp4_tag_type:2; + u64 tcp6_tag_type:2; + u64 ip4_src_flag:1; + u64 ip6_src_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_dprt_flag:1; + u64 inc_prt_flag:1; + u64 inc_vlan:1; + u64 inc_vs:2; + u64 tag_mode:2; + u64 reserved_30_30:1; + u64 grptag:1; + u64 grptagmask:4; + u64 grptagbase:4; + u64 reserved_40_63:24; +#endif + } cn30xx; + struct cvmx_pip_prt_tagx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 grptagbase:4; + u64 grptagmask:4; + u64 grptag:1; + u64 grptag_mskip:1; + u64 tag_mode:2; + u64 inc_vs:2; + u64 inc_vlan:1; + u64 inc_prt_flag:1; + u64 ip6_dprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_src_flag:1; + u64 ip4_src_flag:1; + u64 tcp6_tag_type:2; + u64 tcp4_tag_type:2; + u64 ip6_tag_type:2; + u64 ip4_tag_type:2; + u64 non_tag_type:2; + u64 grp:4; +#else + u64 grp:4; + u64 non_tag_type:2; + u64 ip4_tag_type:2; + u64 ip6_tag_type:2; + u64 tcp4_tag_type:2; + u64 tcp6_tag_type:2; + u64 ip4_src_flag:1; + u64 ip6_src_flag:1; + u64 ip4_dst_flag:1; + u64 ip6_dst_flag:1; + u64 ip4_pctl_flag:1; + u64 ip6_nxth_flag:1; + u64 ip4_sprt_flag:1; + u64 ip6_sprt_flag:1; + u64 ip4_dprt_flag:1; + u64 ip6_dprt_flag:1; + u64 inc_prt_flag:1; + u64 inc_vlan:1; + u64 inc_vs:2; + u64 tag_mode:2; + u64 grptag_mskip:1; + u64 grptag:1; + u64 grptagmask:4; + u64 grptagbase:4; + u64 reserved_40_63:24; +#endif + } cn50xx; +}; + +union cvmx_pip_qos_diffx { + u64 u64; + struct cvmx_pip_qos_diffx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 qos:3; +#else + u64 qos:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_pip_qos_vlanx { + u64 u64; + struct cvmx_pip_qos_vlanx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 qos1:3; + u64 reserved_3_3:1; + u64 qos:3; +#else + u64 qos:3; + u64 reserved_3_3:1; + u64 qos1:3; + u64 reserved_7_63:57; +#endif + } s; + struct cvmx_pip_qos_vlanx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 qos:3; +#else + u64 qos:3; + u64 reserved_3_63:61; +#endif + } cn30xx; +}; + +union cvmx_pip_qos_watchx { + u64 u64; + struct cvmx_pip_qos_watchx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 mask:16; + u64 reserved_30_31:2; + u64 grp:6; + u64 reserved_23_23:1; + u64 qos:3; + u64 reserved_19_19:1; + u64 match_type:3; + u64 match_value:16; +#else + u64 match_value:16; + u64 match_type:3; + u64 reserved_19_19:1; + u64 qos:3; + u64 reserved_23_23:1; + u64 grp:6; + u64 reserved_30_31:2; + u64 mask:16; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_pip_qos_watchx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 mask:16; + u64 reserved_28_31:4; + u64 grp:4; + u64 reserved_23_23:1; + u64 qos:3; + u64 reserved_18_19:2; + u64 match_type:2; + u64 match_value:16; +#else + u64 match_value:16; + u64 match_type:2; + u64 reserved_18_19:2; + u64 qos:3; + u64 reserved_23_23:1; + u64 grp:4; + u64 reserved_28_31:4; + u64 mask:16; + u64 reserved_48_63:16; +#endif + } cn30xx; + struct cvmx_pip_qos_watchx_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 mask:16; + u64 reserved_28_31:4; + u64 grp:4; + u64 reserved_23_23:1; + u64 qos:3; + u64 reserved_19_19:1; + u64 match_type:3; + u64 match_value:16; +#else + u64 match_value:16; + u64 match_type:3; + u64 reserved_19_19:1; + u64 qos:3; + u64 reserved_23_23:1; + u64 grp:4; + u64 reserved_28_31:4; + u64 mask:16; + u64 reserved_48_63:16; +#endif + } cn50xx; +}; + +union cvmx_pip_raw_word { + u64 u64; + struct cvmx_pip_raw_word_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 word:56; +#else + u64 word:56; + u64 reserved_56_63:8; +#endif + } s; +}; + +union cvmx_pip_sft_rst { + u64 u64; + struct cvmx_pip_sft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 rst:1; +#else + u64 rst:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_pip_stat0_x { + u64 u64; + struct cvmx_pip_stat0_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 drp_pkts:32; + u64 drp_octs:32; +#else + u64 drp_octs:32; + u64 drp_pkts:32; +#endif + } s; +}; + +union cvmx_pip_stat0_prtx { + u64 u64; + struct cvmx_pip_stat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 drp_pkts:32; + u64 drp_octs:32; +#else + u64 drp_octs:32; + u64 drp_pkts:32; +#endif + } s; +}; + +union cvmx_pip_stat10_x { + u64 u64; + struct cvmx_pip_stat10_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_stat10_prtx { + u64 u64; + struct cvmx_pip_stat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_stat11_x { + u64 u64; + struct cvmx_pip_stat11_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_stat11_prtx { + u64 u64; + struct cvmx_pip_stat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_stat1_x { + u64 u64; + struct cvmx_pip_stat1_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pip_stat1_prtx { + u64 u64; + struct cvmx_pip_stat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pip_stat2_x { + u64 u64; + struct cvmx_pip_stat2_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pkts:32; + u64 raw:32; +#else + u64 raw:32; + u64 pkts:32; +#endif + } s; +}; + +union cvmx_pip_stat2_prtx { + u64 u64; + struct cvmx_pip_stat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pkts:32; + u64 raw:32; +#else + u64 raw:32; + u64 pkts:32; +#endif + } s; +}; + +union cvmx_pip_stat3_x { + u64 u64; + struct cvmx_pip_stat3_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcst:32; + u64 mcst:32; +#else + u64 mcst:32; + u64 bcst:32; +#endif + } s; +}; + +union cvmx_pip_stat3_prtx { + u64 u64; + struct cvmx_pip_stat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcst:32; + u64 mcst:32; +#else + u64 mcst:32; + u64 bcst:32; +#endif + } s; +}; + +union cvmx_pip_stat4_x { + u64 u64; + struct cvmx_pip_stat4_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h65to127:32; + u64 h64:32; +#else + u64 h64:32; + u64 h65to127:32; +#endif + } s; +}; + +union cvmx_pip_stat4_prtx { + u64 u64; + struct cvmx_pip_stat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h65to127:32; + u64 h64:32; +#else + u64 h64:32; + u64 h65to127:32; +#endif + } s; +}; + +union cvmx_pip_stat5_x { + u64 u64; + struct cvmx_pip_stat5_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h256to511:32; + u64 h128to255:32; +#else + u64 h128to255:32; + u64 h256to511:32; +#endif + } s; +}; + +union cvmx_pip_stat5_prtx { + u64 u64; + struct cvmx_pip_stat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h256to511:32; + u64 h128to255:32; +#else + u64 h128to255:32; + u64 h256to511:32; +#endif + } s; +}; + +union cvmx_pip_stat6_x { + u64 u64; + struct cvmx_pip_stat6_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h1024to1518:32; + u64 h512to1023:32; +#else + u64 h512to1023:32; + u64 h1024to1518:32; +#endif + } s; +}; + +union cvmx_pip_stat6_prtx { + u64 u64; + struct cvmx_pip_stat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h1024to1518:32; + u64 h512to1023:32; +#else + u64 h512to1023:32; + u64 h1024to1518:32; +#endif + } s; +}; + +union cvmx_pip_stat7_x { + u64 u64; + struct cvmx_pip_stat7_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fcs:32; + u64 h1519:32; +#else + u64 h1519:32; + u64 fcs:32; +#endif + } s; +}; + +union cvmx_pip_stat7_prtx { + u64 u64; + struct cvmx_pip_stat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fcs:32; + u64 h1519:32; +#else + u64 h1519:32; + u64 fcs:32; +#endif + } s; +}; + +union cvmx_pip_stat8_x { + u64 u64; + struct cvmx_pip_stat8_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 frag:32; + u64 undersz:32; +#else + u64 undersz:32; + u64 frag:32; +#endif + } s; +}; + +union cvmx_pip_stat8_prtx { + u64 u64; + struct cvmx_pip_stat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 frag:32; + u64 undersz:32; +#else + u64 undersz:32; + u64 frag:32; +#endif + } s; +}; + +union cvmx_pip_stat9_x { + u64 u64; + struct cvmx_pip_stat9_x_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 jabber:32; + u64 oversz:32; +#else + u64 oversz:32; + u64 jabber:32; +#endif + } s; +}; + +union cvmx_pip_stat9_prtx { + u64 u64; + struct cvmx_pip_stat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 jabber:32; + u64 oversz:32; +#else + u64 oversz:32; + u64 jabber:32; +#endif + } s; +}; + +union cvmx_pip_stat_ctl { + u64 u64; + struct cvmx_pip_stat_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 mode:1; + u64 reserved_1_7:7; + u64 rdclr:1; +#else + u64 rdclr:1; + u64 reserved_1_7:7; + u64 mode:1; + u64 reserved_9_63:55; +#endif + } s; + struct cvmx_pip_stat_ctl_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 rdclr:1; +#else + u64 rdclr:1; + u64 reserved_1_63:63; +#endif + } cn30xx; +}; + +union cvmx_pip_stat_inb_errsx { + u64 u64; + struct cvmx_pip_stat_inb_errsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 errs:16; +#else + u64 errs:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pip_stat_inb_errs_pkndx { + u64 u64; + struct cvmx_pip_stat_inb_errs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 errs:16; +#else + u64 errs:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pip_stat_inb_octsx { + u64 u64; + struct cvmx_pip_stat_inb_octsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pip_stat_inb_octs_pkndx { + u64 u64; + struct cvmx_pip_stat_inb_octs_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pip_stat_inb_pktsx { + u64 u64; + struct cvmx_pip_stat_inb_pktsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pkts:32; +#else + u64 pkts:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pip_stat_inb_pkts_pkndx { + u64 u64; + struct cvmx_pip_stat_inb_pkts_pkndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pkts:32; +#else + u64 pkts:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pip_sub_pkind_fcsx { + u64 u64; + struct cvmx_pip_sub_pkind_fcsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 port_bit:64; +#else + u64 port_bit:64; +#endif + } s; +}; + +union cvmx_pip_tag_incx { + u64 u64; + struct cvmx_pip_tag_incx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 en:8; +#else + u64 en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pip_tag_mask { + u64 u64; + struct cvmx_pip_tag_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 mask:16; +#else + u64 mask:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pip_tag_secret { + u64 u64; + struct cvmx_pip_tag_secret_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 dst:16; + u64 src:16; +#else + u64 src:16; + u64 dst:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pip_todo_entry { + u64 u64; + struct cvmx_pip_todo_entry_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 val:1; + u64 reserved_62_62:1; + u64 entry:62; +#else + u64 entry:62; + u64 reserved_62_62:1; + u64 val:1; +#endif + } s; +}; + +union cvmx_pip_vlan_etypesx { + u64 u64; + struct cvmx_pip_vlan_etypesx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 type3:16; + u64 type2:16; + u64 type1:16; + u64 type0:16; +#else + u64 type0:16; + u64 type1:16; + u64 type2:16; + u64 type3:16; +#endif + } s; +}; + +union cvmx_pip_xstat0_prtx { + u64 u64; + struct cvmx_pip_xstat0_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 drp_pkts:32; + u64 drp_octs:32; +#else + u64 drp_octs:32; + u64 drp_pkts:32; +#endif + } s; +}; + +union cvmx_pip_xstat10_prtx { + u64 u64; + struct cvmx_pip_xstat10_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_xstat11_prtx { + u64 u64; + struct cvmx_pip_xstat11_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcast:32; + u64 mcast:32; +#else + u64 mcast:32; + u64 bcast:32; +#endif + } s; +}; + +union cvmx_pip_xstat1_prtx { + u64 u64; + struct cvmx_pip_xstat1_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 octs:48; +#else + u64 octs:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pip_xstat2_prtx { + u64 u64; + struct cvmx_pip_xstat2_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 pkts:32; + u64 raw:32; +#else + u64 raw:32; + u64 pkts:32; +#endif + } s; +}; + +union cvmx_pip_xstat3_prtx { + u64 u64; + struct cvmx_pip_xstat3_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bcst:32; + u64 mcst:32; +#else + u64 mcst:32; + u64 bcst:32; +#endif + } s; +}; + +union cvmx_pip_xstat4_prtx { + u64 u64; + struct cvmx_pip_xstat4_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h65to127:32; + u64 h64:32; +#else + u64 h64:32; + u64 h65to127:32; +#endif + } s; +}; + +union cvmx_pip_xstat5_prtx { + u64 u64; + struct cvmx_pip_xstat5_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h256to511:32; + u64 h128to255:32; +#else + u64 h128to255:32; + u64 h256to511:32; +#endif + } s; +}; + +union cvmx_pip_xstat6_prtx { + u64 u64; + struct cvmx_pip_xstat6_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 h1024to1518:32; + u64 h512to1023:32; +#else + u64 h512to1023:32; + u64 h1024to1518:32; +#endif + } s; +}; + +union cvmx_pip_xstat7_prtx { + u64 u64; + struct cvmx_pip_xstat7_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fcs:32; + u64 h1519:32; +#else + u64 h1519:32; + u64 fcs:32; +#endif + } s; +}; + +union cvmx_pip_xstat8_prtx { + u64 u64; + struct cvmx_pip_xstat8_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 frag:32; + u64 undersz:32; +#else + u64 undersz:32; + u64 frag:32; +#endif + } s; +}; + +union cvmx_pip_xstat9_prtx { + u64 u64; + struct cvmx_pip_xstat9_prtx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 jabber:32; + u64 oversz:32; +#else + u64 oversz:32; + u64 jabber:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pip.h b/drivers/staging/octeon/cvmx-pip.h new file mode 100644 index 000000000000..175fb6b8386a --- /dev/null +++ b/drivers/staging/octeon/cvmx-pip.h @@ -0,0 +1,527 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the hardware Packet Input Processing unit. + * + */ + +#ifndef __CVMX_PIP_H__ +#define __CVMX_PIP_H__ + +#include "cvmx-wqe.h" +#include "cvmx-fpa.h" +#include "cvmx-pip-defs.h" + +#define CVMX_PIP_NUM_INPUT_PORTS 48 +#define CVMX_PIP_NUM_WATCHERS 4 + +/* + * Encodes the different error and exception codes + */ +typedef enum { + CVMX_PIP_L4_NO_ERR = 0ull, + /* + * 1 = TCP (UDP) packet not long enough to cover TCP (UDP) + * header + */ + CVMX_PIP_L4_MAL_ERR = 1ull, + /* 2 = TCP/UDP checksum failure */ + CVMX_PIP_CHK_ERR = 2ull, + /* + * 3 = TCP/UDP length check (TCP/UDP length does not match IP + * length). + */ + CVMX_PIP_L4_LENGTH_ERR = 3ull, + /* 4 = illegal TCP/UDP port (either source or dest port is zero) */ + CVMX_PIP_BAD_PRT_ERR = 4ull, + /* 8 = TCP flags = FIN only */ + CVMX_PIP_TCP_FLG8_ERR = 8ull, + /* 9 = TCP flags = 0 */ + CVMX_PIP_TCP_FLG9_ERR = 9ull, + /* 10 = TCP flags = FIN+RST+* */ + CVMX_PIP_TCP_FLG10_ERR = 10ull, + /* 11 = TCP flags = SYN+URG+* */ + CVMX_PIP_TCP_FLG11_ERR = 11ull, + /* 12 = TCP flags = SYN+RST+* */ + CVMX_PIP_TCP_FLG12_ERR = 12ull, + /* 13 = TCP flags = SYN+FIN+* */ + CVMX_PIP_TCP_FLG13_ERR = 13ull +} cvmx_pip_l4_err_t; + +typedef enum { + CVMX_PIP_IP_NO_ERR = 0ull, + /* 1 = not IPv4 or IPv6 */ + CVMX_PIP_NOT_IP = 1ull, + /* 2 = IPv4 header checksum violation */ + CVMX_PIP_IPV4_HDR_CHK = 2ull, + /* 3 = malformed (packet not long enough to cover IP hdr) */ + CVMX_PIP_IP_MAL_HDR = 3ull, + /* 4 = malformed (packet not long enough to cover len in IP hdr) */ + CVMX_PIP_IP_MAL_PKT = 4ull, + /* 5 = TTL / hop count equal zero */ + CVMX_PIP_TTL_HOP = 5ull, + /* 6 = IPv4 options / IPv6 early extension headers */ + CVMX_PIP_OPTS = 6ull +} cvmx_pip_ip_exc_t; + +/** + * NOTES + * late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as bad FCS + * or carrier extend error which is CVMX_PIP_EXTEND_ERR + */ +typedef enum { + /* No error */ + CVMX_PIP_RX_NO_ERR = 0ull, + /* RGM+SPI 1 = partially received packet (buffering/bandwidth + * not adequate) */ + CVMX_PIP_PARTIAL_ERR = 1ull, + /* RGM+SPI 2 = receive packet too large and truncated */ + CVMX_PIP_JABBER_ERR = 2ull, + /* + * RGM 3 = max frame error (pkt len > max frame len) (with FCS + * error) + */ + CVMX_PIP_OVER_FCS_ERR = 3ull, + /* RGM+SPI 4 = max frame error (pkt len > max frame len) */ + CVMX_PIP_OVER_ERR = 4ull, + /* + * RGM 5 = nibble error (data not byte multiple - 100M and 10M + * only) + */ + CVMX_PIP_ALIGN_ERR = 5ull, + /* + * RGM 6 = min frame error (pkt len < min frame len) (with FCS + * error) + */ + CVMX_PIP_UNDER_FCS_ERR = 6ull, + /* RGM 7 = FCS error */ + CVMX_PIP_GMX_FCS_ERR = 7ull, + /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ + CVMX_PIP_UNDER_ERR = 8ull, + /* RGM 9 = Frame carrier extend error */ + CVMX_PIP_EXTEND_ERR = 9ull, + /* + * RGM 10 = length mismatch (len did not match len in L2 + * length/type) + */ + CVMX_PIP_LENGTH_ERR = 10ull, + /* RGM 11 = Frame error (some or all data bits marked err) */ + CVMX_PIP_DAT_ERR = 11ull, + /* SPI 11 = DIP4 error */ + CVMX_PIP_DIP_ERR = 11ull, + /* + * RGM 12 = packet was not large enough to pass the skipper - + * no inspection could occur. + */ + CVMX_PIP_SKIP_ERR = 12ull, + /* + * RGM 13 = studder error (data not repeated - 100M and 10M + * only) + */ + CVMX_PIP_NIBBLE_ERR = 13ull, + /* RGM+SPI 16 = FCS error */ + CVMX_PIP_PIP_FCS = 16L, + /* + * RGM+SPI+PCI 17 = packet was not large enough to pass the + * skipper - no inspection could occur. + */ + CVMX_PIP_PIP_SKIP_ERR = 17L, + /* + * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to + * cover L2 hdr). + */ + CVMX_PIP_PIP_L2_MAL_HDR = 18L + /* + * NOTES: xx = late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as + * bad FCS or carrier extend error which is + * CVMX_PIP_EXTEND_ERR + */ +} cvmx_pip_rcv_err_t; + +/** + * This defines the err_code field errors in the work Q entry + */ +typedef union { + cvmx_pip_l4_err_t l4_err; + cvmx_pip_ip_exc_t ip_exc; + cvmx_pip_rcv_err_t rcv_err; +} cvmx_pip_err_t; + +/** + * Status statistics for a port + */ +typedef struct { + /* Inbound octets marked to be dropped by the IPD */ + u32 dropped_octets; + /* Inbound packets marked to be dropped by the IPD */ + u32 dropped_packets; + /* RAW PCI Packets received by PIP per port */ + u32 pci_raw_packets; + /* Number of octets processed by PIP */ + u32 octets; + /* Number of packets processed by PIP */ + u32 packets; + /* + * Number of identified L2 multicast packets. Does not + * include broadcast packets. Only includes packets whose + * parse mode is SKIP_TO_L2 + */ + u32 multicast_packets; + /* + * Number of identified L2 broadcast packets. Does not + * include multicast packets. Only includes packets whose + * parse mode is SKIP_TO_L2 + */ + u32 broadcast_packets; + /* Number of 64B packets */ + u32 len_64_packets; + /* Number of 65-127B packets */ + u32 len_65_127_packets; + /* Number of 128-255B packets */ + u32 len_128_255_packets; + /* Number of 256-511B packets */ + u32 len_256_511_packets; + /* Number of 512-1023B packets */ + u32 len_512_1023_packets; + /* Number of 1024-1518B packets */ + u32 len_1024_1518_packets; + /* Number of 1519-max packets */ + u32 len_1519_max_packets; + /* Number of packets with FCS or Align opcode errors */ + u32 fcs_align_err_packets; + /* Number of packets with length < min */ + u32 runt_packets; + /* Number of packets with length < min and FCS error */ + u32 runt_crc_packets; + /* Number of packets with length > max */ + u32 oversize_packets; + /* Number of packets with length > max and FCS error */ + u32 oversize_crc_packets; + /* Number of packets without GMX/SPX/PCI errors received by PIP */ + u32 inb_packets; + /* + * Total number of octets from all packets received by PIP, + * including CRC + */ + u64 inb_octets; + /* Number of packets with GMX/SPX/PCI errors received by PIP */ + u16 inb_errors; +} cvmx_pip_port_status_t; + +/** + * Definition of the PIP custom header that can be prepended + * to a packet by external hardware. + */ +typedef union { + u64 u64; + struct { + /* + * Documented as R - Set if the Packet is RAWFULL. If + * set, this header must be the full 8 bytes. + */ + u64 rawfull:1; + /* Must be zero */ + u64 reserved0:5; + /* PIP parse mode for this packet */ + u64 parse_mode:2; + /* Must be zero */ + u64 reserved1:1; + /* + * Skip amount, including this header, to the + * beginning of the packet + */ + u64 skip_len:7; + /* Must be zero */ + u64 reserved2:6; + /* POW input queue for this packet */ + u64 qos:3; + /* POW input group for this packet */ + u64 grp:4; + /* + * Flag to store this packet in the work queue entry, + * if possible + */ + u64 rs:1; + /* POW input tag type */ + u64 tag_type:2; + /* POW input tag */ + u64 tag:32; + } s; +} cvmx_pip_pkt_inst_hdr_t; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Configure an ethernet input port + * + * @port_num: Port number to configure + * @port_cfg: Port hardware configuration + * @port_tag_cfg: + * Port POW tagging configuration + */ +static inline void cvmx_pip_config_port(u64 port_num, + union cvmx_pip_prt_cfgx port_cfg, + union cvmx_pip_prt_tagx port_tag_cfg) +{ + cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); + cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); +} + +#if 0 +/** + * @deprecated This function is a thin wrapper around the Pass1 version + * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for + * setting the group that is incompatible with this function, + * the preferred upgrade path is to use the CSR directly. + * + * Configure the global QoS packet watchers. Each watcher is + * capable of matching a field in a packet to determine the + * QoS queue for scheduling. + * + * @watcher: Watcher number to configure (0 - 3). + * @match_type: Watcher match type + * @match_value: + * Value the watcher will match against + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_watcher(u64 watcher, + cvmx_pip_qos_watch_types match_type, + u64 match_value, u64 qos) +{ + cvmx_pip_port_watcher_cfg_t watcher_config; + + watcher_config.u64 = 0; + watcher_config.s.match_type = match_type; + watcher_config.s.match_value = match_value; + watcher_config.s.qos = qos; + + cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); +} +#endif +/** + * Configure the VLAN priority to QoS queue mapping. + * + * @vlan_priority: + * VLAN priority (0-7) + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_vlan_qos(u64 vlan_priority, + u64 qos) +{ + union cvmx_pip_qos_vlanx pip_qos_vlanx; + + pip_qos_vlanx.u64 = 0; + pip_qos_vlanx.s.qos = qos; + cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); +} + +/** + * Configure the Diffserv to QoS queue mapping. + * + * @diffserv: Diffserv field value (0-63) + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_diffserv_qos(u64 diffserv, u64 qos) +{ + union cvmx_pip_qos_diffx pip_qos_diffx; + + pip_qos_diffx.u64 = 0; + pip_qos_diffx.s.qos = qos; + cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); +} + +/** + * Get the status counters for a port. + * + * @port_num: Port number to get statistics for. + * @clear: Set to 1 to clear the counters after they are read + * @status: Where to put the results. + */ +static inline void cvmx_pip_get_port_status(u64 port_num, u64 clear, + cvmx_pip_port_status_t *status) +{ + union cvmx_pip_stat_ctl pip_stat_ctl; + union cvmx_pip_stat0_prtx stat0; + union cvmx_pip_stat1_prtx stat1; + union cvmx_pip_stat2_prtx stat2; + union cvmx_pip_stat3_prtx stat3; + union cvmx_pip_stat4_prtx stat4; + union cvmx_pip_stat5_prtx stat5; + union cvmx_pip_stat6_prtx stat6; + union cvmx_pip_stat7_prtx stat7; + union cvmx_pip_stat8_prtx stat8; + union cvmx_pip_stat9_prtx stat9; + union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx; + union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx; + union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx; + + pip_stat_ctl.u64 = 0; + pip_stat_ctl.s.rdclr = clear; + cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); + + stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); + stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); + stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); + stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); + stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); + stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); + stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); + stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); + stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); + stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); + pip_stat_inb_pktsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); + pip_stat_inb_octsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); + pip_stat_inb_errsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); + + status->dropped_octets = stat0.s.drp_octs; + status->dropped_packets = stat0.s.drp_pkts; + status->octets = stat1.s.octs; + status->pci_raw_packets = stat2.s.raw; + status->packets = stat2.s.pkts; + status->multicast_packets = stat3.s.mcst; + status->broadcast_packets = stat3.s.bcst; + status->len_64_packets = stat4.s.h64; + status->len_65_127_packets = stat4.s.h65to127; + status->len_128_255_packets = stat5.s.h128to255; + status->len_256_511_packets = stat5.s.h256to511; + status->len_512_1023_packets = stat6.s.h512to1023; + status->len_1024_1518_packets = stat6.s.h1024to1518; + status->len_1519_max_packets = stat7.s.h1519; + status->fcs_align_err_packets = stat7.s.fcs; + status->runt_packets = stat8.s.undersz; + status->runt_crc_packets = stat8.s.frag; + status->oversize_packets = stat9.s.oversz; + status->oversize_crc_packets = stat9.s.jabber; + status->inb_packets = pip_stat_inb_pktsx.s.pkts; + status->inb_octets = pip_stat_inb_octsx.s.octs; + status->inb_errors = pip_stat_inb_errsx.s.errs; + + if (cvmx_octeon_is_pass1()) { + /* + * Kludge to fix Octeon Pass 1 errata - Drop counts + * don't work. + */ + if (status->inb_packets > status->packets) + status->dropped_packets = + status->inb_packets - status->packets; + else + status->dropped_packets = 0; + if (status->inb_octets - status->inb_packets * 4 > + status->octets) + status->dropped_octets = + status->inb_octets - status->inb_packets * 4 - + status->octets; + else + status->dropped_octets = 0; + } +} + +/** + * Configure the hardware CRC engine + * + * @interface: Interface to configure (0 or 1) + * @invert_result: + * Invert the result of the CRC + * @reflect: Reflect + * @initialization_vector: + * CRC initialization vector + */ +static inline void cvmx_pip_config_crc(u64 interface, + u64 invert_result, u64 reflect, + u32 initialization_vector) +{ + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + union cvmx_pip_crc_ctlx config; + union cvmx_pip_crc_ivx pip_crc_ivx; + + config.u64 = 0; + config.s.invres = invert_result; + config.s.reflect = reflect; + cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); + + pip_crc_ivx.u64 = 0; + pip_crc_ivx.s.iv = initialization_vector; + cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); + } +} + +/** + * Clear all bits in a tag mask. This should be called on + * startup before any calls to cvmx_pip_tag_mask_set. Each bit + * set in the final mask represent a byte used in the packet for + * tag generation. + * + * @mask_index: Which tag mask to clear (0..3) + */ +static inline void cvmx_pip_tag_mask_clear(u64 mask_index) +{ + u64 index; + union cvmx_pip_tag_incx pip_tag_incx; + + pip_tag_incx.u64 = 0; + pip_tag_incx.s.en = 0; + for (index = mask_index * 16; index < (mask_index + 1) * 16; index++) + cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); +} + +/** + * Sets a range of bits in the tag mask. The tag mask is used + * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero. + * There are four separate masks that can be configured. + * + * @mask_index: Which tag mask to modify (0..3) + * @offset: Offset into the bitmask to set bits at. Use the GCC macro + * offsetof() to determine the offsets into packet headers. + * For example, offsetof(ethhdr, protocol) returns the offset + * of the ethernet protocol field. The bitmask selects which + * bytes to include the tag, with bit offset X selecting + * byte at offset X from the beginning of the packet data. + * @len: Number of bytes to include. Usually this is the sizeof() + * the field. + */ +static inline void cvmx_pip_tag_mask_set(u64 mask_index, u64 offset, + u64 len) +{ + while (len--) { + union cvmx_pip_tag_incx pip_tag_incx; + u64 index = mask_index * 16 + offset / 8; + + pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); + pip_tag_incx.s.en |= 0x80 >> (offset & 0x7); + cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); + offset++; + } +} + +#endif /* __CVMX_PIP_H__ */ diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/drivers/staging/octeon/cvmx-pko-defs.h new file mode 100644 index 000000000000..e7f40a82533b --- /dev/null +++ b/drivers/staging/octeon/cvmx-pko-defs.h @@ -0,0 +1,2204 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PKO_DEFS_H__ +#define __CVMX_PKO_DEFS_H__ + +#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull)) +#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull)) +#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull)) +#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull)) +#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull)) +#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull)) +#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull)) +#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull)) +#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull)) +#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull)) +#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull)) +#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull)) +#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull)) +#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull)) +#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull)) +#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull)) +#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull)) +#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull)) +#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull)) +#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull)) +#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull)) +#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull)) +#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull)) +#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull)) +#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull)) +#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull)) +#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull)) +#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull)) +#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull)) +#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull)) +#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull)) +#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull)) +#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull)) +#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull)) +#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull)) +#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull)) +#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull)) +#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull)) +#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8) +#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull)) +#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull)) +#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull)) +#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull)) +#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull)) +#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull)) +#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull)) +#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull)) +#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull)) +#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull)) +#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull)) +#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull)) +#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull)) +#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull)) +#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull)) + +union cvmx_pko_mem_count0 { + u64 u64; + struct cvmx_pko_mem_count0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 count:32; +#else + u64 count:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pko_mem_count1 { + u64 u64; + struct cvmx_pko_mem_count1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 count:48; +#else + u64 count:48; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_pko_mem_debug0 { + u64 u64; + struct cvmx_pko_mem_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fau:28; + u64 cmd:14; + u64 segs:6; + u64 size:16; +#else + u64 size:16; + u64 segs:6; + u64 cmd:14; + u64 fau:28; +#endif + } s; +}; + +union cvmx_pko_mem_debug1 { + u64 u64; + struct cvmx_pko_mem_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 ptr:40; +#else + u64 ptr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } s; +}; + +union cvmx_pko_mem_debug10 { + u64 u64; + struct cvmx_pko_mem_debug10_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug10_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fau:28; + u64 cmd:14; + u64 segs:6; + u64 size:16; +#else + u64 size:16; + u64 segs:6; + u64 cmd:14; + u64 fau:28; +#endif + } cn30xx; + struct cvmx_pko_mem_debug10_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 ptrs1:17; + u64 reserved_17_31:15; + u64 ptrs2:17; +#else + u64 ptrs2:17; + u64 reserved_17_31:15; + u64 ptrs1:17; + u64 reserved_49_63:15; +#endif + } cn50xx; +}; + +union cvmx_pko_mem_debug11 { + u64 u64; + struct cvmx_pko_mem_debug11_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 reserved_0_39:40; +#else + u64 reserved_0_39:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } s; + struct cvmx_pko_mem_debug11_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 ptr:40; +#else + u64 ptr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } cn30xx; + struct cvmx_pko_mem_debug11_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 maj:1; + u64 uid:3; + u64 sop:1; + u64 len:1; + u64 chk:1; + u64 cnt:13; + u64 mod:3; +#else + u64 mod:3; + u64 cnt:13; + u64 chk:1; + u64 len:1; + u64 sop:1; + u64 uid:3; + u64 maj:1; + u64 reserved_23_63:41; +#endif + } cn50xx; +}; + +union cvmx_pko_mem_debug12 { + u64 u64; + struct cvmx_pko_mem_debug12_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug12_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } cn30xx; + struct cvmx_pko_mem_debug12_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 fau:28; + u64 cmd:14; + u64 segs:6; + u64 size:16; +#else + u64 size:16; + u64 segs:6; + u64 cmd:14; + u64 fau:28; +#endif + } cn50xx; + struct cvmx_pko_mem_debug12_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 state:64; +#else + u64 state:64; +#endif + } cn68xx; +}; + +union cvmx_pko_mem_debug13 { + u64 u64; + struct cvmx_pko_mem_debug13_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug13_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + u64 widx:17; + u64 ridx2:17; + u64 widx2:17; +#else + u64 widx2:17; + u64 ridx2:17; + u64 widx:17; + u64 reserved_51_63:13; +#endif + } cn30xx; + struct cvmx_pko_mem_debug13_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 ptr:40; +#else + u64 ptr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } cn50xx; + struct cvmx_pko_mem_debug13_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 state:64; +#else + u64 state:64; +#endif + } cn68xx; +}; + +union cvmx_pko_mem_debug14 { + u64 u64; + struct cvmx_pko_mem_debug14_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug14_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 ridx:17; +#else + u64 ridx:17; + u64 reserved_17_63:47; +#endif + } cn30xx; + struct cvmx_pko_mem_debug14_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } cn52xx; +}; + +union cvmx_pko_mem_debug2 { + u64 u64; + struct cvmx_pko_mem_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 ptr:40; +#else + u64 ptr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } s; +}; + +union cvmx_pko_mem_debug3 { + u64 u64; + struct cvmx_pko_mem_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug3_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 i:1; + u64 back:4; + u64 pool:3; + u64 size:16; + u64 ptr:40; +#else + u64 ptr:40; + u64 size:16; + u64 pool:3; + u64 back:4; + u64 i:1; +#endif + } cn30xx; + struct cvmx_pko_mem_debug3_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } cn50xx; +}; + +union cvmx_pko_mem_debug4 { + u64 u64; + struct cvmx_pko_mem_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug4_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 data:64; +#else + u64 data:64; +#endif + } cn30xx; + struct cvmx_pko_mem_debug4_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 cmnd_segs:3; + u64 cmnd_siz:16; + u64 cmnd_off:6; + u64 uid:3; + u64 dread_sop:1; + u64 init_dwrite:1; + u64 chk_once:1; + u64 chk_mode:1; + u64 active:1; + u64 static_p:1; + u64 qos:3; + u64 qcb_ridx:5; + u64 qid_off_max:4; + u64 qid_off:4; + u64 qid_base:8; + u64 wait:1; + u64 minor:2; + u64 major:3; +#else + u64 major:3; + u64 minor:2; + u64 wait:1; + u64 qid_base:8; + u64 qid_off:4; + u64 qid_off_max:4; + u64 qcb_ridx:5; + u64 qos:3; + u64 static_p:1; + u64 active:1; + u64 chk_mode:1; + u64 chk_once:1; + u64 init_dwrite:1; + u64 dread_sop:1; + u64 uid:3; + u64 cmnd_off:6; + u64 cmnd_siz:16; + u64 cmnd_segs:3; +#endif + } cn50xx; + struct cvmx_pko_mem_debug4_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 curr_siz:8; + u64 curr_off:16; + u64 cmnd_segs:6; + u64 cmnd_siz:16; + u64 cmnd_off:6; + u64 uid:2; + u64 dread_sop:1; + u64 init_dwrite:1; + u64 chk_once:1; + u64 chk_mode:1; + u64 wait:1; + u64 minor:2; + u64 major:3; +#else + u64 major:3; + u64 minor:2; + u64 wait:1; + u64 chk_mode:1; + u64 chk_once:1; + u64 init_dwrite:1; + u64 dread_sop:1; + u64 uid:2; + u64 cmnd_off:6; + u64 cmnd_siz:16; + u64 cmnd_segs:6; + u64 curr_off:16; + u64 curr_siz:8; +#endif + } cn52xx; +}; + +union cvmx_pko_mem_debug5 { + u64 u64; + struct cvmx_pko_mem_debug5_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug5_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dwri_mod:1; + u64 dwri_sop:1; + u64 dwri_len:1; + u64 dwri_cnt:13; + u64 cmnd_siz:16; + u64 uid:1; + u64 xfer_wor:1; + u64 xfer_dwr:1; + u64 cbuf_fre:1; + u64 reserved_27_27:1; + u64 chk_mode:1; + u64 active:1; + u64 qos:3; + u64 qcb_ridx:5; + u64 qid_off:3; + u64 qid_base:7; + u64 wait:1; + u64 minor:2; + u64 major:4; +#else + u64 major:4; + u64 minor:2; + u64 wait:1; + u64 qid_base:7; + u64 qid_off:3; + u64 qcb_ridx:5; + u64 qos:3; + u64 active:1; + u64 chk_mode:1; + u64 reserved_27_27:1; + u64 cbuf_fre:1; + u64 xfer_dwr:1; + u64 xfer_wor:1; + u64 uid:1; + u64 cmnd_siz:16; + u64 dwri_cnt:13; + u64 dwri_len:1; + u64 dwri_sop:1; + u64 dwri_mod:1; +#endif + } cn30xx; + struct cvmx_pko_mem_debug5_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 curr_ptr:29; + u64 curr_siz:16; + u64 curr_off:16; + u64 cmnd_segs:3; +#else + u64 cmnd_segs:3; + u64 curr_off:16; + u64 curr_siz:16; + u64 curr_ptr:29; +#endif + } cn50xx; + struct cvmx_pko_mem_debug5_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 nxt_inflt:6; + u64 curr_ptr:40; + u64 curr_siz:8; +#else + u64 curr_siz:8; + u64 curr_ptr:40; + u64 nxt_inflt:6; + u64 reserved_54_63:10; +#endif + } cn52xx; + struct cvmx_pko_mem_debug5_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 ptp:1; + u64 major_3:1; + u64 nxt_inflt:6; + u64 curr_ptr:40; + u64 curr_siz:8; +#else + u64 curr_siz:8; + u64 curr_ptr:40; + u64 nxt_inflt:6; + u64 major_3:1; + u64 ptp:1; + u64 reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_mem_debug5_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_57_63:7; + u64 uid_2:1; + u64 ptp:1; + u64 major_3:1; + u64 nxt_inflt:6; + u64 curr_ptr:40; + u64 curr_siz:8; +#else + u64 curr_siz:8; + u64 curr_ptr:40; + u64 nxt_inflt:6; + u64 major_3:1; + u64 ptp:1; + u64 uid_2:1; + u64 reserved_57_63:7; +#endif + } cn68xx; +}; + +union cvmx_pko_mem_debug6 { + u64 u64; + struct cvmx_pko_mem_debug6_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 qid_offres:4; + u64 qid_offths:4; + u64 preempter:1; + u64 preemptee:1; + u64 preempted:1; + u64 active:1; + u64 statc:1; + u64 qos:3; + u64 qcb_ridx:5; + u64 qid_offmax:4; + u64 reserved_0_11:12; +#else + u64 reserved_0_11:12; + u64 qid_offmax:4; + u64 qcb_ridx:5; + u64 qos:3; + u64 statc:1; + u64 active:1; + u64 preempted:1; + u64 preemptee:1; + u64 preempter:1; + u64 qid_offths:4; + u64 qid_offres:4; + u64 reserved_37_63:27; +#endif + } s; + struct cvmx_pko_mem_debug6_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 qid_offm:3; + u64 static_p:1; + u64 work_min:3; + u64 dwri_chk:1; + u64 dwri_uid:1; + u64 dwri_mod:2; +#else + u64 dwri_mod:2; + u64 dwri_uid:1; + u64 dwri_chk:1; + u64 work_min:3; + u64 static_p:1; + u64 qid_offm:3; + u64 reserved_11_63:53; +#endif + } cn30xx; + struct cvmx_pko_mem_debug6_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 curr_ptr:11; +#else + u64 curr_ptr:11; + u64 reserved_11_63:53; +#endif + } cn50xx; + struct cvmx_pko_mem_debug6_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 qid_offres:4; + u64 qid_offths:4; + u64 preempter:1; + u64 preemptee:1; + u64 preempted:1; + u64 active:1; + u64 statc:1; + u64 qos:3; + u64 qcb_ridx:5; + u64 qid_offmax:4; + u64 qid_off:4; + u64 qid_base:8; +#else + u64 qid_base:8; + u64 qid_off:4; + u64 qid_offmax:4; + u64 qcb_ridx:5; + u64 qos:3; + u64 statc:1; + u64 active:1; + u64 preempted:1; + u64 preemptee:1; + u64 preempter:1; + u64 qid_offths:4; + u64 qid_offres:4; + u64 reserved_37_63:27; +#endif + } cn52xx; +}; + +union cvmx_pko_mem_debug7 { + u64 u64; + struct cvmx_pko_mem_debug7_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_mem_debug7_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_58_63:6; + u64 dwb:9; + u64 start:33; + u64 size:16; +#else + u64 size:16; + u64 start:33; + u64 dwb:9; + u64 reserved_58_63:6; +#endif + } cn30xx; + struct cvmx_pko_mem_debug7_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 qos:5; + u64 tail:1; + u64 buf_siz:13; + u64 buf_ptr:33; + u64 qcb_widx:6; + u64 qcb_ridx:6; +#else + u64 qcb_ridx:6; + u64 qcb_widx:6; + u64 buf_ptr:33; + u64 buf_siz:13; + u64 tail:1; + u64 qos:5; +#endif + } cn50xx; + struct cvmx_pko_mem_debug7_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 qos:3; + u64 tail:1; + u64 buf_siz:13; + u64 buf_ptr:33; + u64 qcb_widx:7; + u64 qcb_ridx:7; +#else + u64 qcb_ridx:7; + u64 qcb_widx:7; + u64 buf_ptr:33; + u64 buf_siz:13; + u64 tail:1; + u64 qos:3; +#endif + } cn68xx; +}; + +union cvmx_pko_mem_debug8 { + u64 u64; + struct cvmx_pko_mem_debug8_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 tail:1; + u64 buf_siz:13; + u64 reserved_0_44:45; +#else + u64 reserved_0_44:45; + u64 buf_siz:13; + u64 tail:1; + u64 reserved_59_63:5; +#endif + } s; + struct cvmx_pko_mem_debug8_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 qos:5; + u64 tail:1; + u64 buf_siz:13; + u64 buf_ptr:33; + u64 qcb_widx:6; + u64 qcb_ridx:6; +#else + u64 qcb_ridx:6; + u64 qcb_widx:6; + u64 buf_ptr:33; + u64 buf_siz:13; + u64 tail:1; + u64 qos:5; +#endif + } cn30xx; + struct cvmx_pko_mem_debug8_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 doorbell:20; + u64 reserved_6_7:2; + u64 static_p:1; + u64 s_tail:1; + u64 static_q:1; + u64 qos:3; +#else + u64 qos:3; + u64 static_q:1; + u64 s_tail:1; + u64 static_p:1; + u64 reserved_6_7:2; + u64 doorbell:20; + u64 reserved_28_63:36; +#endif + } cn50xx; + struct cvmx_pko_mem_debug8_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 preempter:1; + u64 doorbell:20; + u64 reserved_7_7:1; + u64 preemptee:1; + u64 static_p:1; + u64 s_tail:1; + u64 static_q:1; + u64 qos:3; +#else + u64 qos:3; + u64 static_q:1; + u64 s_tail:1; + u64 static_p:1; + u64 preemptee:1; + u64 reserved_7_7:1; + u64 doorbell:20; + u64 preempter:1; + u64 reserved_29_63:35; +#endif + } cn52xx; + struct cvmx_pko_mem_debug8_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_42_63:22; + u64 qid_qqos:8; + u64 reserved_33_33:1; + u64 qid_idx:4; + u64 preempter:1; + u64 doorbell:20; + u64 reserved_7_7:1; + u64 preemptee:1; + u64 static_p:1; + u64 s_tail:1; + u64 static_q:1; + u64 qos:3; +#else + u64 qos:3; + u64 static_q:1; + u64 s_tail:1; + u64 static_p:1; + u64 preemptee:1; + u64 reserved_7_7:1; + u64 doorbell:20; + u64 preempter:1; + u64 qid_idx:4; + u64 reserved_33_33:1; + u64 qid_qqos:8; + u64 reserved_42_63:22; +#endif + } cn61xx; + struct cvmx_pko_mem_debug8_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_37_63:27; + u64 preempter:1; + u64 doorbell:20; + u64 reserved_9_15:7; + u64 preemptee:1; + u64 static_p:1; + u64 s_tail:1; + u64 static_q:1; + u64 qos:5; +#else + u64 qos:5; + u64 static_q:1; + u64 s_tail:1; + u64 static_p:1; + u64 preemptee:1; + u64 reserved_9_15:7; + u64 doorbell:20; + u64 preempter:1; + u64 reserved_37_63:27; +#endif + } cn68xx; +}; + +union cvmx_pko_mem_debug9 { + u64 u64; + struct cvmx_pko_mem_debug9_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 ptrs0:17; + u64 reserved_0_31:32; +#else + u64 reserved_0_31:32; + u64 ptrs0:17; + u64 reserved_49_63:15; +#endif + } s; + struct cvmx_pko_mem_debug9_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 doorbell:20; + u64 reserved_5_7:3; + u64 s_tail:1; + u64 static_q:1; + u64 qos:3; +#else + u64 qos:3; + u64 static_q:1; + u64 s_tail:1; + u64 reserved_5_7:3; + u64 doorbell:20; + u64 reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_pko_mem_debug9_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 doorbell:20; + u64 reserved_6_7:2; + u64 static_p:1; + u64 s_tail:1; + u64 static_q:1; + u64 qos:3; +#else + u64 qos:3; + u64 static_q:1; + u64 s_tail:1; + u64 static_p:1; + u64 reserved_6_7:2; + u64 doorbell:20; + u64 reserved_28_63:36; +#endif + } cn38xx; + struct cvmx_pko_mem_debug9_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_49_63:15; + u64 ptrs0:17; + u64 reserved_17_31:15; + u64 ptrs3:17; +#else + u64 ptrs3:17; + u64 reserved_17_31:15; + u64 ptrs0:17; + u64 reserved_49_63:15; +#endif + } cn50xx; +}; + +union cvmx_pko_mem_iport_ptrs { + u64 u64; + struct cvmx_pko_mem_iport_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 crc:1; + u64 static_p:1; + u64 qos_mask:8; + u64 min_pkt:3; + u64 reserved_31_49:19; + u64 pipe:7; + u64 reserved_21_23:3; + u64 intr:5; + u64 reserved_13_15:3; + u64 eid:5; + u64 reserved_7_7:1; + u64 ipid:7; +#else + u64 ipid:7; + u64 reserved_7_7:1; + u64 eid:5; + u64 reserved_13_15:3; + u64 intr:5; + u64 reserved_21_23:3; + u64 pipe:7; + u64 reserved_31_49:19; + u64 min_pkt:3; + u64 qos_mask:8; + u64 static_p:1; + u64 crc:1; + u64 reserved_63_63:1; +#endif + } s; +}; + +union cvmx_pko_mem_iport_qos { + u64 u64; + struct cvmx_pko_mem_iport_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 qos_mask:8; + u64 reserved_13_52:40; + u64 eid:5; + u64 reserved_7_7:1; + u64 ipid:7; +#else + u64 ipid:7; + u64 reserved_7_7:1; + u64 eid:5; + u64 reserved_13_52:40; + u64 qos_mask:8; + u64 reserved_61_63:3; +#endif + } s; +}; + +union cvmx_pko_mem_iqueue_ptrs { + u64 u64; + struct cvmx_pko_mem_iqueue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 s_tail:1; + u64 static_p:1; + u64 static_q:1; + u64 qos_mask:8; + u64 buf_ptr:31; + u64 tail:1; + u64 index:5; + u64 reserved_15_15:1; + u64 ipid:7; + u64 qid:8; +#else + u64 qid:8; + u64 ipid:7; + u64 reserved_15_15:1; + u64 index:5; + u64 tail:1; + u64 buf_ptr:31; + u64 qos_mask:8; + u64 static_q:1; + u64 static_p:1; + u64 s_tail:1; +#endif + } s; +}; + +union cvmx_pko_mem_iqueue_qos { + u64 u64; + struct cvmx_pko_mem_iqueue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 qos_mask:8; + u64 reserved_15_52:38; + u64 ipid:7; + u64 qid:8; +#else + u64 qid:8; + u64 ipid:7; + u64 reserved_15_52:38; + u64 qos_mask:8; + u64 reserved_61_63:3; +#endif + } s; +}; + +union cvmx_pko_mem_port_ptrs { + u64 u64; + struct cvmx_pko_mem_port_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + u64 static_p:1; + u64 qos_mask:8; + u64 reserved_16_52:37; + u64 bp_port:6; + u64 eid:4; + u64 pid:6; +#else + u64 pid:6; + u64 eid:4; + u64 bp_port:6; + u64 reserved_16_52:37; + u64 qos_mask:8; + u64 static_p:1; + u64 reserved_62_63:2; +#endif + } s; +}; + +union cvmx_pko_mem_port_qos { + u64 u64; + struct cvmx_pko_mem_port_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 qos_mask:8; + u64 reserved_10_52:43; + u64 eid:4; + u64 pid:6; +#else + u64 pid:6; + u64 eid:4; + u64 reserved_10_52:43; + u64 qos_mask:8; + u64 reserved_61_63:3; +#endif + } s; +}; + +union cvmx_pko_mem_port_rate0 { + u64 u64; + struct cvmx_pko_mem_port_rate0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + u64 rate_word:19; + u64 rate_pkt:24; + u64 reserved_7_7:1; + u64 pid:7; +#else + u64 pid:7; + u64 reserved_7_7:1; + u64 rate_pkt:24; + u64 rate_word:19; + u64 reserved_51_63:13; +#endif + } s; + struct cvmx_pko_mem_port_rate0_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + u64 rate_word:19; + u64 rate_pkt:24; + u64 reserved_6_7:2; + u64 pid:6; +#else + u64 pid:6; + u64 reserved_6_7:2; + u64 rate_pkt:24; + u64 rate_word:19; + u64 reserved_51_63:13; +#endif + } cn52xx; +}; + +union cvmx_pko_mem_port_rate1 { + u64 u64; + struct cvmx_pko_mem_port_rate1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rate_lim:24; + u64 reserved_7_7:1; + u64 pid:7; +#else + u64 pid:7; + u64 reserved_7_7:1; + u64 rate_lim:24; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_pko_mem_port_rate1_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rate_lim:24; + u64 reserved_6_7:2; + u64 pid:6; +#else + u64 pid:6; + u64 reserved_6_7:2; + u64 rate_lim:24; + u64 reserved_32_63:32; +#endif + } cn52xx; +}; + +union cvmx_pko_mem_queue_ptrs { + u64 u64; + struct cvmx_pko_mem_queue_ptrs_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 s_tail:1; + u64 static_p:1; + u64 static_q:1; + u64 qos_mask:8; + u64 buf_ptr:36; + u64 tail:1; + u64 index:3; + u64 port:6; + u64 queue:7; +#else + u64 queue:7; + u64 port:6; + u64 index:3; + u64 tail:1; + u64 buf_ptr:36; + u64 qos_mask:8; + u64 static_q:1; + u64 static_p:1; + u64 s_tail:1; +#endif + } s; +}; + +union cvmx_pko_mem_queue_qos { + u64 u64; + struct cvmx_pko_mem_queue_qos_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_61_63:3; + u64 qos_mask:8; + u64 reserved_13_52:40; + u64 pid:6; + u64 qid:7; +#else + u64 qid:7; + u64 pid:6; + u64 reserved_13_52:40; + u64 qos_mask:8; + u64 reserved_61_63:3; +#endif + } s; +}; + +union cvmx_pko_mem_throttle_int { + u64 u64; + struct cvmx_pko_mem_throttle_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 word:15; + u64 reserved_14_31:18; + u64 packet:6; + u64 reserved_5_7:3; + u64 intr:5; +#else + u64 intr:5; + u64 reserved_5_7:3; + u64 packet:6; + u64 reserved_14_31:18; + u64 word:15; + u64 reserved_47_63:17; +#endif + } s; +}; + +union cvmx_pko_mem_throttle_pipe { + u64 u64; + struct cvmx_pko_mem_throttle_pipe_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 word:15; + u64 reserved_14_31:18; + u64 packet:6; + u64 reserved_7_7:1; + u64 pipe:7; +#else + u64 pipe:7; + u64 reserved_7_7:1; + u64 packet:6; + u64 reserved_14_31:18; + u64 word:15; + u64 reserved_47_63:17; +#endif + } s; +}; + +union cvmx_pko_reg_bist_result { + u64 u64; + struct cvmx_pko_reg_bist_result_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_pko_reg_bist_result_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 psb2:5; + u64 count:1; + u64 rif:1; + u64 wif:1; + u64 ncb:1; + u64 out:1; + u64 crc:1; + u64 chk:1; + u64 qsb:2; + u64 qcb:2; + u64 pdb:4; + u64 psb:7; +#else + u64 psb:7; + u64 pdb:4; + u64 qcb:2; + u64 qsb:2; + u64 chk:1; + u64 crc:1; + u64 out:1; + u64 ncb:1; + u64 wif:1; + u64 rif:1; + u64 count:1; + u64 psb2:5; + u64 reserved_27_63:37; +#endif + } cn30xx; + struct cvmx_pko_reg_bist_result_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 csr:1; + u64 iob:1; + u64 out_crc:1; + u64 out_ctl:3; + u64 out_sta:1; + u64 out_wif:1; + u64 prt_chk:3; + u64 prt_nxt:1; + u64 prt_psb:6; + u64 ncb_inb:2; + u64 prt_qcb:2; + u64 prt_qsb:3; + u64 dat_dat:4; + u64 dat_ptr:4; +#else + u64 dat_ptr:4; + u64 dat_dat:4; + u64 prt_qsb:3; + u64 prt_qcb:2; + u64 ncb_inb:2; + u64 prt_psb:6; + u64 prt_nxt:1; + u64 prt_chk:3; + u64 out_wif:1; + u64 out_sta:1; + u64 out_ctl:3; + u64 out_crc:1; + u64 iob:1; + u64 csr:1; + u64 reserved_33_63:31; +#endif + } cn50xx; + struct cvmx_pko_reg_bist_result_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 csr:1; + u64 iob:1; + u64 out_dat:1; + u64 out_ctl:3; + u64 out_sta:1; + u64 out_wif:1; + u64 prt_chk:3; + u64 prt_nxt:1; + u64 prt_psb:8; + u64 ncb_inb:2; + u64 prt_qcb:2; + u64 prt_qsb:3; + u64 prt_ctl:2; + u64 dat_dat:2; + u64 dat_ptr:4; +#else + u64 dat_ptr:4; + u64 dat_dat:2; + u64 prt_ctl:2; + u64 prt_qsb:3; + u64 prt_qcb:2; + u64 ncb_inb:2; + u64 prt_psb:8; + u64 prt_nxt:1; + u64 prt_chk:3; + u64 out_wif:1; + u64 out_sta:1; + u64 out_ctl:3; + u64 out_dat:1; + u64 iob:1; + u64 csr:1; + u64 reserved_35_63:29; +#endif + } cn52xx; + struct cvmx_pko_reg_bist_result_cn68xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_36_63:28; + u64 crc:1; + u64 csr:1; + u64 iob:1; + u64 out_dat:1; + u64 reserved_31_31:1; + u64 out_ctl:2; + u64 out_sta:1; + u64 out_wif:1; + u64 prt_chk:3; + u64 prt_nxt:1; + u64 prt_psb7:1; + u64 reserved_21_21:1; + u64 prt_psb:6; + u64 ncb_inb:2; + u64 prt_qcb:2; + u64 prt_qsb:3; + u64 prt_ctl:2; + u64 dat_dat:2; + u64 dat_ptr:4; +#else + u64 dat_ptr:4; + u64 dat_dat:2; + u64 prt_ctl:2; + u64 prt_qsb:3; + u64 prt_qcb:2; + u64 ncb_inb:2; + u64 prt_psb:6; + u64 reserved_21_21:1; + u64 prt_psb7:1; + u64 prt_nxt:1; + u64 prt_chk:3; + u64 out_wif:1; + u64 out_sta:1; + u64 out_ctl:2; + u64 reserved_31_31:1; + u64 out_dat:1; + u64 iob:1; + u64 csr:1; + u64 crc:1; + u64 reserved_36_63:28; +#endif + } cn68xx; + struct cvmx_pko_reg_bist_result_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_35_63:29; + u64 csr:1; + u64 iob:1; + u64 out_dat:1; + u64 reserved_31_31:1; + u64 out_ctl:2; + u64 out_sta:1; + u64 out_wif:1; + u64 prt_chk:3; + u64 prt_nxt:1; + u64 prt_psb7:1; + u64 reserved_21_21:1; + u64 prt_psb:6; + u64 ncb_inb:2; + u64 prt_qcb:2; + u64 prt_qsb:3; + u64 prt_ctl:2; + u64 dat_dat:2; + u64 dat_ptr:4; +#else + u64 dat_ptr:4; + u64 dat_dat:2; + u64 prt_ctl:2; + u64 prt_qsb:3; + u64 prt_qcb:2; + u64 ncb_inb:2; + u64 prt_psb:6; + u64 reserved_21_21:1; + u64 prt_psb7:1; + u64 prt_nxt:1; + u64 prt_chk:3; + u64 out_wif:1; + u64 out_sta:1; + u64 out_ctl:2; + u64 reserved_31_31:1; + u64 out_dat:1; + u64 iob:1; + u64 csr:1; + u64 reserved_35_63:29; +#endif + } cn68xxp1; +}; + +union cvmx_pko_reg_cmd_buf { + u64 u64; + struct cvmx_pko_reg_cmd_buf_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_23_63:41; + u64 pool:3; + u64 reserved_13_19:7; + u64 size:13; +#else + u64 size:13; + u64 reserved_13_19:7; + u64 pool:3; + u64 reserved_23_63:41; +#endif + } s; +}; + +union cvmx_pko_reg_crc_ctlx { + u64 u64; + struct cvmx_pko_reg_crc_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 invres:1; + u64 refin:1; +#else + u64 refin:1; + u64 invres:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pko_reg_crc_enable { + u64 u64; + struct cvmx_pko_reg_crc_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enable:32; +#else + u64 enable:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pko_reg_crc_ivx { + u64 u64; + struct cvmx_pko_reg_crc_ivx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iv:32; +#else + u64 iv:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pko_reg_debug0 { + u64 u64; + struct cvmx_pko_reg_debug0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 asserts:64; +#else + u64 asserts:64; +#endif + } s; + struct cvmx_pko_reg_debug0_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 asserts:17; +#else + u64 asserts:17; + u64 reserved_17_63:47; +#endif + } cn30xx; +}; + +union cvmx_pko_reg_debug1 { + u64 u64; + struct cvmx_pko_reg_debug1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 asserts:64; +#else + u64 asserts:64; +#endif + } s; +}; + +union cvmx_pko_reg_debug2 { + u64 u64; + struct cvmx_pko_reg_debug2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 asserts:64; +#else + u64 asserts:64; +#endif + } s; +}; + +union cvmx_pko_reg_debug3 { + u64 u64; + struct cvmx_pko_reg_debug3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 asserts:64; +#else + u64 asserts:64; +#endif + } s; +}; + +union cvmx_pko_reg_debug4 { + u64 u64; + struct cvmx_pko_reg_debug4_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 asserts:64; +#else + u64 asserts:64; +#endif + } s; +}; + +union cvmx_pko_reg_engine_inflight { + u64 u64; + struct cvmx_pko_reg_engine_inflight_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 engine15:4; + u64 engine14:4; + u64 engine13:4; + u64 engine12:4; + u64 engine11:4; + u64 engine10:4; + u64 engine9:4; + u64 engine8:4; + u64 engine7:4; + u64 engine6:4; + u64 engine5:4; + u64 engine4:4; + u64 engine3:4; + u64 engine2:4; + u64 engine1:4; + u64 engine0:4; +#else + u64 engine0:4; + u64 engine1:4; + u64 engine2:4; + u64 engine3:4; + u64 engine4:4; + u64 engine5:4; + u64 engine6:4; + u64 engine7:4; + u64 engine8:4; + u64 engine9:4; + u64 engine10:4; + u64 engine11:4; + u64 engine12:4; + u64 engine13:4; + u64 engine14:4; + u64 engine15:4; +#endif + } s; + struct cvmx_pko_reg_engine_inflight_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 engine9:4; + u64 engine8:4; + u64 engine7:4; + u64 engine6:4; + u64 engine5:4; + u64 engine4:4; + u64 engine3:4; + u64 engine2:4; + u64 engine1:4; + u64 engine0:4; +#else + u64 engine0:4; + u64 engine1:4; + u64 engine2:4; + u64 engine3:4; + u64 engine4:4; + u64 engine5:4; + u64 engine6:4; + u64 engine7:4; + u64 engine8:4; + u64 engine9:4; + u64 reserved_40_63:24; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_inflight_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 engine13:4; + u64 engine12:4; + u64 engine11:4; + u64 engine10:4; + u64 engine9:4; + u64 engine8:4; + u64 engine7:4; + u64 engine6:4; + u64 engine5:4; + u64 engine4:4; + u64 engine3:4; + u64 engine2:4; + u64 engine1:4; + u64 engine0:4; +#else + u64 engine0:4; + u64 engine1:4; + u64 engine2:4; + u64 engine3:4; + u64 engine4:4; + u64 engine5:4; + u64 engine6:4; + u64 engine7:4; + u64 engine8:4; + u64 engine9:4; + u64 engine10:4; + u64 engine11:4; + u64 engine12:4; + u64 engine13:4; + u64 reserved_56_63:8; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_inflight_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 engine11:4; + u64 engine10:4; + u64 engine9:4; + u64 engine8:4; + u64 engine7:4; + u64 engine6:4; + u64 engine5:4; + u64 engine4:4; + u64 engine3:4; + u64 engine2:4; + u64 engine1:4; + u64 engine0:4; +#else + u64 engine0:4; + u64 engine1:4; + u64 engine2:4; + u64 engine3:4; + u64 engine4:4; + u64 engine5:4; + u64 engine6:4; + u64 engine7:4; + u64 engine8:4; + u64 engine9:4; + u64 engine10:4; + u64 engine11:4; + u64 reserved_48_63:16; +#endif + } cn63xx; +}; + +union cvmx_pko_reg_engine_inflight1 { + u64 u64; + struct cvmx_pko_reg_engine_inflight1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 engine19:4; + u64 engine18:4; + u64 engine17:4; + u64 engine16:4; +#else + u64 engine16:4; + u64 engine17:4; + u64 engine18:4; + u64 engine19:4; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pko_reg_engine_storagex { + u64 u64; + struct cvmx_pko_reg_engine_storagex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 engine15:4; + u64 engine14:4; + u64 engine13:4; + u64 engine12:4; + u64 engine11:4; + u64 engine10:4; + u64 engine9:4; + u64 engine8:4; + u64 engine7:4; + u64 engine6:4; + u64 engine5:4; + u64 engine4:4; + u64 engine3:4; + u64 engine2:4; + u64 engine1:4; + u64 engine0:4; +#else + u64 engine0:4; + u64 engine1:4; + u64 engine2:4; + u64 engine3:4; + u64 engine4:4; + u64 engine5:4; + u64 engine6:4; + u64 engine7:4; + u64 engine8:4; + u64 engine9:4; + u64 engine10:4; + u64 engine11:4; + u64 engine12:4; + u64 engine13:4; + u64 engine14:4; + u64 engine15:4; +#endif + } s; +}; + +union cvmx_pko_reg_engine_thresh { + u64 u64; + struct cvmx_pko_reg_engine_thresh_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 mask:20; +#else + u64 mask:20; + u64 reserved_20_63:44; +#endif + } s; + struct cvmx_pko_reg_engine_thresh_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 mask:10; +#else + u64 mask:10; + u64 reserved_10_63:54; +#endif + } cn52xx; + struct cvmx_pko_reg_engine_thresh_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 mask:14; +#else + u64 mask:14; + u64 reserved_14_63:50; +#endif + } cn61xx; + struct cvmx_pko_reg_engine_thresh_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 mask:12; +#else + u64 mask:12; + u64 reserved_12_63:52; +#endif + } cn63xx; +}; + +union cvmx_pko_reg_error { + u64 u64; + struct cvmx_pko_reg_error_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 loopback:1; + u64 currzero:1; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 currzero:1; + u64 loopback:1; + u64 reserved_4_63:60; +#endif + } s; + struct cvmx_pko_reg_error_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 reserved_2_63:62; +#endif + } cn30xx; + struct cvmx_pko_reg_error_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 currzero:1; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 currzero:1; + u64 reserved_3_63:61; +#endif + } cn50xx; +}; + +union cvmx_pko_reg_flags { + u64 u64; + struct cvmx_pko_reg_flags_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 dis_perf3:1; + u64 dis_perf2:1; + u64 dis_perf1:1; + u64 dis_perf0:1; + u64 ena_throttle:1; + u64 reset:1; + u64 store_be:1; + u64 ena_dwb:1; + u64 ena_pko:1; +#else + u64 ena_pko:1; + u64 ena_dwb:1; + u64 store_be:1; + u64 reset:1; + u64 ena_throttle:1; + u64 dis_perf0:1; + u64 dis_perf1:1; + u64 dis_perf2:1; + u64 dis_perf3:1; + u64 reserved_9_63:55; +#endif + } s; + struct cvmx_pko_reg_flags_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 reset:1; + u64 store_be:1; + u64 ena_dwb:1; + u64 ena_pko:1; +#else + u64 ena_pko:1; + u64 ena_dwb:1; + u64 store_be:1; + u64 reset:1; + u64 reserved_4_63:60; +#endif + } cn30xx; + struct cvmx_pko_reg_flags_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 dis_perf3:1; + u64 dis_perf2:1; + u64 reserved_4_6:3; + u64 reset:1; + u64 store_be:1; + u64 ena_dwb:1; + u64 ena_pko:1; +#else + u64 ena_pko:1; + u64 ena_dwb:1; + u64 store_be:1; + u64 reset:1; + u64 reserved_4_6:3; + u64 dis_perf2:1; + u64 dis_perf3:1; + u64 reserved_9_63:55; +#endif + } cn61xx; + struct cvmx_pko_reg_flags_cn68xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 dis_perf1:1; + u64 dis_perf0:1; + u64 ena_throttle:1; + u64 reset:1; + u64 store_be:1; + u64 ena_dwb:1; + u64 ena_pko:1; +#else + u64 ena_pko:1; + u64 ena_dwb:1; + u64 store_be:1; + u64 reset:1; + u64 ena_throttle:1; + u64 dis_perf0:1; + u64 dis_perf1:1; + u64 reserved_7_63:57; +#endif + } cn68xxp1; +}; + +union cvmx_pko_reg_gmx_port_mode { + u64 u64; + struct cvmx_pko_reg_gmx_port_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 mode1:3; + u64 mode0:3; +#else + u64 mode0:3; + u64 mode1:3; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_pko_reg_int_mask { + u64 u64; + struct cvmx_pko_reg_int_mask_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 loopback:1; + u64 currzero:1; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 currzero:1; + u64 loopback:1; + u64 reserved_4_63:60; +#endif + } s; + struct cvmx_pko_reg_int_mask_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 reserved_2_63:62; +#endif + } cn30xx; + struct cvmx_pko_reg_int_mask_cn50xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 currzero:1; + u64 doorbell:1; + u64 parity:1; +#else + u64 parity:1; + u64 doorbell:1; + u64 currzero:1; + u64 reserved_3_63:61; +#endif + } cn50xx; +}; + +union cvmx_pko_reg_loopback_bpid { + u64 u64; + struct cvmx_pko_reg_loopback_bpid_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 bpid7:6; + u64 reserved_52_52:1; + u64 bpid6:6; + u64 reserved_45_45:1; + u64 bpid5:6; + u64 reserved_38_38:1; + u64 bpid4:6; + u64 reserved_31_31:1; + u64 bpid3:6; + u64 reserved_24_24:1; + u64 bpid2:6; + u64 reserved_17_17:1; + u64 bpid1:6; + u64 reserved_10_10:1; + u64 bpid0:6; + u64 reserved_0_3:4; +#else + u64 reserved_0_3:4; + u64 bpid0:6; + u64 reserved_10_10:1; + u64 bpid1:6; + u64 reserved_17_17:1; + u64 bpid2:6; + u64 reserved_24_24:1; + u64 bpid3:6; + u64 reserved_31_31:1; + u64 bpid4:6; + u64 reserved_38_38:1; + u64 bpid5:6; + u64 reserved_45_45:1; + u64 bpid6:6; + u64 reserved_52_52:1; + u64 bpid7:6; + u64 reserved_59_63:5; +#endif + } s; +}; + +union cvmx_pko_reg_loopback_pkind { + u64 u64; + struct cvmx_pko_reg_loopback_pkind_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 pkind7:6; + u64 reserved_52_52:1; + u64 pkind6:6; + u64 reserved_45_45:1; + u64 pkind5:6; + u64 reserved_38_38:1; + u64 pkind4:6; + u64 reserved_31_31:1; + u64 pkind3:6; + u64 reserved_24_24:1; + u64 pkind2:6; + u64 reserved_17_17:1; + u64 pkind1:6; + u64 reserved_10_10:1; + u64 pkind0:6; + u64 num_ports:4; +#else + u64 num_ports:4; + u64 pkind0:6; + u64 reserved_10_10:1; + u64 pkind1:6; + u64 reserved_17_17:1; + u64 pkind2:6; + u64 reserved_24_24:1; + u64 pkind3:6; + u64 reserved_31_31:1; + u64 pkind4:6; + u64 reserved_38_38:1; + u64 pkind5:6; + u64 reserved_45_45:1; + u64 pkind6:6; + u64 reserved_52_52:1; + u64 pkind7:6; + u64 reserved_59_63:5; +#endif + } s; +}; + +union cvmx_pko_reg_min_pkt { + u64 u64; + struct cvmx_pko_reg_min_pkt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 size7:8; + u64 size6:8; + u64 size5:8; + u64 size4:8; + u64 size3:8; + u64 size2:8; + u64 size1:8; + u64 size0:8; +#else + u64 size0:8; + u64 size1:8; + u64 size2:8; + u64 size3:8; + u64 size4:8; + u64 size5:8; + u64 size6:8; + u64 size7:8; +#endif + } s; +}; + +union cvmx_pko_reg_preempt { + u64 u64; + struct cvmx_pko_reg_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 min_size:16; +#else + u64 min_size:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pko_reg_queue_mode { + u64 u64; + struct cvmx_pko_reg_queue_mode_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 mode:2; +#else + u64 mode:2; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pko_reg_queue_preempt { + u64 u64; + struct cvmx_pko_reg_queue_preempt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 preemptee:1; + u64 preempter:1; +#else + u64 preempter:1; + u64 preemptee:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pko_reg_queue_ptrs1 { + u64 u64; + struct cvmx_pko_reg_queue_ptrs1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 idx3:1; + u64 qid7:1; +#else + u64 qid7:1; + u64 idx3:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_pko_reg_read_idx { + u64 u64; + struct cvmx_pko_reg_read_idx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 inc:8; + u64 index:8; +#else + u64 index:8; + u64 inc:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_pko_reg_throttle { + u64 u64; + struct cvmx_pko_reg_throttle_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 int_mask:32; +#else + u64 int_mask:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pko_reg_timestamp { + u64 u64; + struct cvmx_pko_reg_timestamp_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 wqe_word:4; +#else + u64 wqe_word:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/drivers/staging/octeon/cvmx-pko.c similarity index 71% rename from arch/mips/cavium-octeon/executive/cvmx-pko.c rename to drivers/staging/octeon/cvmx-pko.c index 6e70b859a0ac..e41fa7f2b7ee 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-pko.c +++ b/drivers/staging/octeon/cvmx-pko.c @@ -1,43 +1,42 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * Support library for the hardware Packet Output unit. - */ + * Support library for the hardware Packet Output unit. + */ -#include +#include "octeon.h" -#include -#include -#include +#include "cvmx-config.h" +#include "cvmx-pko.h" +#include "cvmx-helper.h" /* - * Internal state of packet output - */ + * Internal state of packet output + */ static int __cvmx_pko_int(int interface, int index) { @@ -76,7 +75,7 @@ static void __cvmx_pko_iport_config(int pko_port) for (queue = 0; queue < num_queues; queue++) { union cvmx_pko_mem_iqueue_ptrs config; cvmx_cmd_queue_result_t cmd_res; - uint64_t *buf_ptr; + u64 *buf_ptr; config.u64 = 0; config.s.index = queue; @@ -100,7 +99,7 @@ static void __cvmx_pko_iport_config(int pko_port) __func__, (int)cmd_res, pko_port, base_queue, num_queues, queue); - buf_ptr = (uint64_t *)cvmx_cmd_queue_buffer( + buf_ptr = (u64 *)cvmx_cmd_queue_buffer( CVMX_CMD_QUEUE_PKO(base_queue + queue)); config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7; CVMX_SYNCWS; @@ -169,7 +168,7 @@ static void __cvmx_pko_chip_init(void) * Initialize queues */ for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) { - const uint64_t priority = 8; + const u64 priority = 8; cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority); @@ -177,10 +176,10 @@ static void __cvmx_pko_chip_init(void) } /* - * Call before any other calls to initialize the packet - * output system. This does chip global config, and should only be - * done by one core. - */ + * Call before any other calls to initialize the packet + * output system. This does chip global config, and should only be + * done by one core. + */ void cvmx_pko_initialize_global(void) { @@ -206,9 +205,9 @@ void cvmx_pko_initialize_global(void) * If we aren't using all of the queues optimize PKO's * internal memory. */ - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) - || OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX) || + OCTEON_IS_MODEL(OCTEON_CN52XX)) { int num_interfaces = cvmx_helper_get_number_of_interfaces(); int last_port = cvmx_helper_get_last_ipd_port(num_interfaces - 1); @@ -230,9 +229,9 @@ void cvmx_pko_initialize_global(void) } /* - * Enables the packet output hardware. It must already be - * configured. - */ + * Enables the packet output hardware. It must already be + * configured. + */ void cvmx_pko_enable(void) { union cvmx_pko_reg_flags flags; @@ -253,11 +252,12 @@ void cvmx_pko_enable(void) } /* - * Disables the packet output. Does not affect any configuration. - */ + * Disables the packet output. Does not affect any configuration. + */ void cvmx_pko_disable(void) { union cvmx_pko_reg_flags pko_reg_flags; + pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); pko_reg_flags.s.ena_pko = 0; cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); @@ -265,19 +265,20 @@ void cvmx_pko_disable(void) EXPORT_SYMBOL_GPL(cvmx_pko_disable); /* - * Reset the packet output. - */ + * Reset the packet output. + */ static void __cvmx_pko_reset(void) { union cvmx_pko_reg_flags pko_reg_flags; + pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); pko_reg_flags.s.reset = 1; cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); } /* - * Shutdown and free resources required by packet output. - */ + * Shutdown and free resources required by packet output. + */ void cvmx_pko_shutdown(void) { union cvmx_pko_mem_queue_ptrs config; @@ -295,6 +296,7 @@ void cvmx_pko_shutdown(void) config.s.buf_ptr = 0; if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { union cvmx_pko_reg_queue_ptrs1 config1; + config1.u64 = 0; config1.s.qid7 = queue >> 7; cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); @@ -307,28 +309,28 @@ void cvmx_pko_shutdown(void) EXPORT_SYMBOL_GPL(cvmx_pko_shutdown); /* - * Configure a output port and the associated queues for use. - * - * @port: Port to configure. - * @base_queue: First queue number to associate with this port. - * @num_queues: Number of queues to associate with this port - * @priority: Array of priority levels for each queue. Values are - * allowed to be 0-8. A value of 8 get 8 times the traffic - * of a value of 1. A value of 0 indicates that no rounds - * will be participated in. These priorities can be changed - * on the fly while the pko is enabled. A priority of 9 - * indicates that static priority should be used. If static - * priority is used all queues with static priority must be - * contiguous starting at the base_queue, and lower numbered - * queues have higher priority than higher numbered queues. - * There must be num_queues elements in the array. - */ -cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, - uint64_t num_queues, - const uint64_t priority[]) + * Configure a output port and the associated queues for use. + * + * @port: Port to configure. + * @base_queue: First queue number to associate with this port. + * @num_queues: Number of queues to associate with this port + * @priority: Array of priority levels for each queue. Values are + * allowed to be 0-8. A value of 8 get 8 times the traffic + * of a value of 1. A value of 0 indicates that no rounds + * will be participated in. These priorities can be changed + * on the fly while the pko is enabled. A priority of 9 + * indicates that static priority should be used. If static + * priority is used all queues with static priority must be + * contiguous starting at the base_queue, and lower numbered + * queues have higher priority than higher numbered queues. + * There must be num_queues elements in the array. + */ +cvmx_pko_status_t cvmx_pko_config_port(u64 port, u64 base_queue, + u64 num_queues, + const u64 priority[]) { cvmx_pko_status_t result_code; - uint64_t queue; + u64 queue; union cvmx_pko_mem_queue_ptrs config; union cvmx_pko_reg_queue_ptrs1 config1; int static_priority_base = -1; @@ -337,8 +339,8 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, if (OCTEON_IS_MODEL(OCTEON_CN68XX)) return CVMX_PKO_SUCCESS; - if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) - && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { + if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) && + (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", (unsigned long long)port); return CVMX_PKO_INVALID_PORT; @@ -359,19 +361,19 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, */ for (queue = 0; queue < num_queues; queue++) { /* Find first queue of static priority */ - if (static_priority_base == -1 - && priority[queue] == + if (static_priority_base == -1 && + priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY) static_priority_base = queue; /* Find last queue of static priority */ - if (static_priority_base != -1 - && static_priority_end == -1 - && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY - && queue) + if (static_priority_base != -1 && + static_priority_end == -1 && + priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && + queue) static_priority_end = queue - 1; - else if (static_priority_base != -1 - && static_priority_end == -1 - && queue == num_queues - 1) + else if (static_priority_base != -1 && + static_priority_end == -1 && + queue == num_queues - 1) /* all queues are static priority */ static_priority_end = queue; /* @@ -380,28 +382,23 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, * cases of static priorities not starting at * queue 0. */ - if (static_priority_end != -1 - && (int)queue > static_priority_end - && priority[queue] == + if (static_priority_end != -1 && + (int)queue > static_priority_end && + priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY) { - cvmx_dprintf("ERROR: cvmx_pko_config_port: " - "Static priority queues aren't " - "contiguous or don't start at " - "base queue. q: %d, eq: %d\n", + cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d\n", (int)queue, static_priority_end); return CVMX_PKO_INVALID_PRIORITY; } } if (static_priority_base > 0) { - cvmx_dprintf("ERROR: cvmx_pko_config_port: Static " - "priority queues don't start at base " - "queue. sq: %d\n", + cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d\n", static_priority_base); return CVMX_PKO_INVALID_PRIORITY; } #if 0 - cvmx_dprintf("Port %d: Static priority queue base: %d, " - "end: %d\n", port, + cvmx_dprintf("Port %d: Static priority queue base: %d, end: %d\n", + port, static_priority_base, static_priority_end); #endif } @@ -420,7 +417,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, #endif for (queue = 0; queue < num_queues; queue++) { - uint64_t *buf_ptr = NULL; + u64 *buf_ptr = NULL; config1.u64 = 0; config1.s.idx3 = queue >> 3; @@ -477,9 +474,8 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, } fallthrough; /* to the error case, when Pass 1 */ default: - cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " - "priority %llu\n", - (unsigned long long)priority[queue]); + cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", + (unsigned long long)priority[queue]); config.s.qos_mask = 0xff; result_code = CVMX_PKO_INVALID_PRIORITY; break; @@ -492,16 +488,13 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, CVMX_PKO_MAX_QUEUE_DEPTH, CVMX_FPA_OUTPUT_BUFFER_POOL, CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - - + - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST * 8); if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) { switch (cmd_res) { case CVMX_CMD_QUEUE_NO_MEMORY: - cvmx_dprintf("ERROR: " - "cvmx_pko_config_port: " - "Unable to allocate " - "output buffer.\n"); + cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n"); return CVMX_PKO_NO_MEMORY; case CVMX_CMD_QUEUE_ALREADY_SETUP: cvmx_dprintf @@ -516,7 +509,7 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, } buf_ptr = - (uint64_t *) + (u64 *) cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO (base_queue + queue)); config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr); @@ -535,9 +528,9 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, #ifdef PKO_DEBUG /* - * Show map of ports -> queues for different cores. - */ -void cvmx_pko_show_queue_map() + * Show map of ports -> queues for different cores. + */ +void cvmx_pko_show_queue_map(void) { int core, port; int pko_output_ports = 36; @@ -560,16 +553,16 @@ void cvmx_pko_show_queue_map() #endif /* - * Rate limit a PKO port to a max packets/sec. This function is only - * supported on CN51XX and higher, excluding CN58XX. - * - * @port: Port to rate limit - * @packets_s: Maximum packet/sec - * @burst: Maximum number of packets to burst in a row before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ + * Rate limit a PKO port to a max packets/sec. This function is only + * supported on CN51XX and higher, excluding CN58XX. + * + * @port: Port to rate limit + * @packets_s: Maximum packet/sec + * @burst: Maximum number of packets to burst in a row before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) { union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; @@ -585,7 +578,7 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) pko_mem_port_rate1.u64 = 0; pko_mem_port_rate1.s.pid = port; pko_mem_port_rate1.s.rate_lim = - ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; + ((u64)pko_mem_port_rate0.s.rate_pkt * burst) >> 8; cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); @@ -593,22 +586,22 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) } /* - * Rate limit a PKO port to a max bits/sec. This function is only - * supported on CN51XX and higher, excluding CN58XX. - * - * @port: Port to rate limit - * @bits_s: PKO rate limit in bits/sec - * @burst: Maximum number of bits to burst before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ -int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) + * Rate limit a PKO port to a max bits/sec. This function is only + * supported on CN51XX and higher, excluding CN58XX. + * + * @port: Port to rate limit + * @bits_s: PKO rate limit in bits/sec + * @burst: Maximum number of bits to burst before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +int cvmx_pko_rate_limit_bits(int port, u64 bits_s, int burst) { union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; - uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; - uint64_t tokens_per_bit = clock_rate * 16 / bits_s; + u64 clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; + u64 tokens_per_bit = clock_rate * 16 / bits_s; pko_mem_port_rate0.u64 = 0; pko_mem_port_rate0.s.pid = port; diff --git a/drivers/staging/octeon/cvmx-pko.h b/drivers/staging/octeon/cvmx-pko.h new file mode 100644 index 000000000000..2389c38e25d3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pko.h @@ -0,0 +1,645 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Interface to the hardware Packet Output unit. + * + * Starting with SDK 1.7.0, the PKO output functions now support + * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to + * function similarly to previous SDKs by using POW atomic tags + * to preserve ordering and exclusivity. As a new option, you + * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc + * memory based locking instead. This locking has the advantage + * of not affecting the tag state but doesn't preserve packet + * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most + * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used + * with hand tuned fast path code. + * + * Some of other SDK differences visible to the command queuing: + * - PKO indexes are no longer stored in the FAU. A large + * percentage of the FAU register block used to be tied up + * maintaining PKO queue pointers. These are now stored in a + * global named block. + * - The PKO use_locking parameter can now have a global + * effect. Since all application use the same named block, + * queue locking correctly applies across all operating + * systems when using CVMX_PKO_LOCK_CMD_QUEUE. + * - PKO 3 word commands are now supported. Use + * cvmx_pko_send_packet_finish3(). + * + */ + +#ifndef __CVMX_PKO_H__ +#define __CVMX_PKO_H__ + +#include "cvmx-fpa.h" +#include "cvmx-pow.h" +#include "cvmx-cmd-queue.h" +#include "cvmx-pko-defs.h" + +/* Adjust the command buffer size by 1 word so that in the case of using only + * two word PKO commands no command words stradle buffers. The useful values + * for this are 0 and 1. */ +#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) + +#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 +#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ + OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ + OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ + (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ + OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) +#define CVMX_PKO_NUM_OUTPUT_PORTS 40 +/* use this for queues that are not used */ +#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 +#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 +#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF +#define CVMX_PKO_MAX_QUEUE_DEPTH 0 + +typedef enum { + CVMX_PKO_SUCCESS, + CVMX_PKO_INVALID_PORT, + CVMX_PKO_INVALID_QUEUE, + CVMX_PKO_INVALID_PRIORITY, + CVMX_PKO_NO_MEMORY, + CVMX_PKO_PORT_ALREADY_SETUP, + CVMX_PKO_CMD_QUEUE_INIT_ERROR +} cvmx_pko_status_t; + +/** + * This enumeration represents the different locking modes supported by PKO. + */ +typedef enum { + /* + * PKO doesn't do any locking. It is the responsibility of the + * application to make sure that no other core is accessing + * the same queue at the same time + */ + CVMX_PKO_LOCK_NONE = 0, + /* + * PKO performs an atomic tagswitch to insure exclusive access + * to the output queue. This will maintain packet ordering on + * output. + */ + CVMX_PKO_LOCK_ATOMIC_TAG = 1, + /* + * PKO uses the common command queue locks to insure exclusive + * access to the output queue. This is a memory based + * ll/sc. This is the most portable locking mechanism. + */ + CVMX_PKO_LOCK_CMD_QUEUE = 2, +} cvmx_pko_lock_t; + +typedef struct { + u32 packets; + u64 octets; + u64 doorbell; +} cvmx_pko_port_status_t; + +/** + * This structure defines the address to use on a packet enqueue + */ +typedef union { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Must CVMX_IO_SEG */ + u64 mem_space:2; + /* Must be zero */ + u64 reserved:13; + /* Must be one */ + u64 is_io:1; + /* The ID of the device on the non-coherent bus */ + u64 did:8; + /* Must be zero */ + u64 reserved2:4; + /* Must be zero */ + u64 reserved3:18; + /* + * The hardware likes to have the output port in + * addition to the output queue, + */ + u64 port:6; + /* + * The output queue to send the packet to (0-127 are + * legal) + */ + u64 queue:9; + /* Must be zero */ + u64 reserved4:3; +#else + u64 reserved4:3; + u64 queue:9; + u64 port:9; + u64 reserved3:15; + u64 reserved2:4; + u64 did:8; + u64 is_io:1; + u64 reserved:13; + u64 mem_space:2; +#endif + } s; +} cvmx_pko_doorbell_address_t; + +/** + * Structure of the first packet output command word. + */ +union cvmx_pko_command_word0 { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * The size of the reg1 operation - could be 8, 16, + * 32, or 64 bits. + */ + u64 size1:2; + /* + * The size of the reg0 operation - could be 8, 16, + * 32, or 64 bits. + */ + u64 size0:2; + /* + * If set, subtract 1, if clear, subtract packet + * size. + */ + u64 subone1:1; + /* + * The register, subtract will be done if reg1 is + * non-zero. + */ + u64 reg1:11; + /* If set, subtract 1, if clear, subtract packet size */ + u64 subone0:1; + /* The register, subtract will be done if reg0 is non-zero */ + u64 reg0:11; + /* + * When set, interpret segment pointer and segment + * bytes in little endian order. + */ + u64 le:1; + /* + * When set, packet data not allocated in L2 cache by + * PKO. + */ + u64 n2:1; + /* + * If set and rsp is set, word3 contains a pointer to + * a work queue entry. + */ + u64 wqp:1; + /* If set, the hardware will send a response when done */ + u64 rsp:1; + /* + * If set, the supplied pkt_ptr is really a pointer to + * a list of pkt_ptr's. + */ + u64 gather:1; + /* + * If ipoffp1 is non zero, (ipoffp1-1) is the number + * of bytes to IP header, and the hardware will + * calculate and insert the UDP/TCP checksum. + */ + u64 ipoffp1:7; + /* + * If set, ignore the I bit (force to zero) from all + * pointer structures. + */ + u64 ignore_i:1; + /* + * If clear, the hardware will attempt to free the + * buffers containing the packet. + */ + u64 dontfree:1; + /* + * The total number of segs in the packet, if gather + * set, also gather list length. + */ + u64 segs:6; + /* Including L2, but no trailing CRC */ + u64 total_bytes:16; +#else + u64 total_bytes:16; + u64 segs:6; + u64 dontfree:1; + u64 ignore_i:1; + u64 ipoffp1:7; + u64 gather:1; + u64 rsp:1; + u64 wqp:1; + u64 n2:1; + u64 le:1; + u64 reg0:11; + u64 subone0:1; + u64 reg1:11; + u64 subone1:1; + u64 size0:2; + u64 size1:2; +#endif + } s; +}; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Definition of internal state for Packet output processing + */ +typedef struct { + /* ptr to start of buffer, offset kept in FAU reg */ + u64 *start_ptr; +} cvmx_pko_state_elem_t; + +/** + * Call before any other calls to initialize the packet + * output system. + */ +void cvmx_pko_initialize_global(void); + +/** + * Enables the packet output hardware. It must already be + * configured. + */ +void cvmx_pko_enable(void); + +/** + * Disables the packet output. Does not affect any configuration. + */ +void cvmx_pko_disable(void); + +/** + * Shutdown and free resources required by packet output. + */ + +void cvmx_pko_shutdown(void); + +/** + * Configure a output port and the associated queues for use. + * + * @port: Port to configure. + * @base_queue: First queue number to associate with this port. + * @num_queues: Number of queues t oassociate with this port + * @priority: Array of priority levels for each queue. Values are + * allowed to be 1-8. A value of 8 get 8 times the traffic + * of a value of 1. There must be num_queues elements in the + * array. + */ +cvmx_pko_status_t cvmx_pko_config_port(u64 port, + u64 base_queue, + u64 num_queues, + const u64 priority[]); + +/** + * Ring the packet output doorbell. This tells the packet + * output hardware that "len" command words have been added + * to its pending list. This command includes the required + * CVMX_SYNCWS before the doorbell ring. + * + * @port: Port the packet is for + * @queue: Queue the packet is for + * @len: Length of the command in 64 bit words + */ +static inline void cvmx_pko_doorbell(u64 port, u64 queue, + u64 len) +{ + cvmx_pko_doorbell_address_t ptr; + + ptr.u64 = 0; + ptr.s.mem_space = CVMX_IO_SEG; + ptr.s.did = CVMX_OCT_DID_PKT_SEND; + ptr.s.is_io = 1; + ptr.s.port = port; + ptr.s.queue = queue; + /* + * Need to make sure output queue data is in DRAM before + * doorbell write. + */ + CVMX_SYNCWS; + cvmx_write_io(ptr.u64, len); +} + +/** + * Prepare to send a packet. This may initiate a tag switch to + * get exclusive access to the output queue structure, and + * performs other prep work for the packet send operation. + * + * cvmx_pko_send_packet_finish() MUST be called after this function is called, + * and must be called with the same port/queue/use_locking arguments. + * + * The use_locking parameter allows the caller to use three + * possible locking modes. + * - CVMX_PKO_LOCK_NONE + * - PKO doesn't do any locking. It is the responsibility + * of the application to make sure that no other core + * is accessing the same queue at the same time. + * - CVMX_PKO_LOCK_ATOMIC_TAG + * - PKO performs an atomic tagswitch to insure exclusive + * access to the output queue. This will maintain + * packet ordering on output. + * - CVMX_PKO_LOCK_CMD_QUEUE + * - PKO uses the common command queue locks to insure + * exclusive access to the output queue. This is a + * memory based ll/sc. This is the most portable + * locking mechanism. + * + * NOTE: If atomic locking is used, the POW entry CANNOT be + * descheduled, as it does not contain a valid WQE pointer. + * + * @port: Port to send it on + * @queue: Queue to use + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + */ + +static inline void cvmx_pko_send_packet_prepare(u64 port, u64 queue, + cvmx_pko_lock_t use_locking) +{ + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) { + /* + * Must do a full switch here to handle all cases. We + * use a fake WQE pointer, as the POW does not access + * this memory. The WQE pointer and group are only + * used if this work is descheduled, which is not + * supported by the + * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish + * combination. Note that this is a special case in + * which these fake values can be used - this is not a + * general technique. + */ + u32 tag = + CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | + CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | + (CVMX_TAG_SUBGROUP_MASK & queue); + cvmx_pow_tag_sw_full((struct cvmx_wqe *)cvmx_phys_to_ptr(0x80), tag, + CVMX_POW_TAG_TYPE_ATOMIC, 0); + } +} + +/** + * Complete packet output. cvmx_pko_send_packet_prepare() must be + * called exactly once before this, and the same parameters must be + * passed to both cvmx_pko_send_packet_prepare() and + * cvmx_pko_send_packet_finish(). + * + * @port: Port to send it on + * @queue: Queue to use + * @pko_command: + * PKO HW command word + * @packet: Packet to send + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + * + * Returns: CVMX_PKO_SUCCESS on success, or error code on + * failure of output + */ +static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( + u64 port, + u64 queue, + union cvmx_pko_command_word0 pko_command, + union cvmx_buf_ptr packet, + cvmx_pko_lock_t use_locking) +{ + cvmx_cmd_queue_result_t result; + + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) + cvmx_pow_tag_sw_wait(); + result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue), + (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), + pko_command.u64, packet.u64); + if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { + cvmx_pko_doorbell(port, queue, 2); + return CVMX_PKO_SUCCESS; + } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || + (result == CVMX_CMD_QUEUE_FULL)) { + return CVMX_PKO_NO_MEMORY; + } else { + return CVMX_PKO_INVALID_QUEUE; + } +} + +/** + * Complete packet output. cvmx_pko_send_packet_prepare() must be + * called exactly once before this, and the same parameters must be + * passed to both cvmx_pko_send_packet_prepare() and + * cvmx_pko_send_packet_finish(). + * + * @port: Port to send it on + * @queue: Queue to use + * @pko_command: + * PKO HW command word + * @packet: Packet to send + * @addr: Plysical address of a work queue entry or physical address + * to zero on complete. + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + * + * Returns: CVMX_PKO_SUCCESS on success, or error code on + * failure of output + */ +static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( + u64 port, + u64 queue, + union cvmx_pko_command_word0 pko_command, + union cvmx_buf_ptr packet, + u64 addr, + cvmx_pko_lock_t use_locking) +{ + cvmx_cmd_queue_result_t result; + + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) + cvmx_pow_tag_sw_wait(); + result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue), + (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), + pko_command.u64, packet.u64, addr); + if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { + cvmx_pko_doorbell(port, queue, 3); + return CVMX_PKO_SUCCESS; + } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || + (result == CVMX_CMD_QUEUE_FULL)) { + return CVMX_PKO_NO_MEMORY; + } else { + return CVMX_PKO_INVALID_QUEUE; + } +} + +/** + * Return the pko output queue associated with a port and a specific core. + * In normal mode (PKO lockless operation is disabled), the value returned + * is the base queue. + * + * @port: Port number + * @core: Core to get queue for + * + * Returns Core-specific output queue + */ +static inline int cvmx_pko_get_base_queue_per_core(int port, int core) +{ +#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 +#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16 +#endif +#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 +#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16 +#endif + + if (port < CVMX_PKO_MAX_PORTS_INTERFACE0) + return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core; + else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port - + 16) * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core; + else if ((port >= 32) && (port < 36)) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + + CVMX_PKO_MAX_PORTS_INTERFACE1 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port - + 32) * + CVMX_PKO_QUEUES_PER_PORT_PCI; + else if ((port >= 36) && (port < 40)) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + + CVMX_PKO_MAX_PORTS_INTERFACE1 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + + 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port - + 36) * + CVMX_PKO_QUEUES_PER_PORT_LOOP; + else + /* Given the limit on the number of ports we can map to + * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256, + * divided among all cores), the remaining unmapped ports + * are assigned an illegal queue number */ + return CVMX_PKO_ILLEGAL_QUEUE; +} + +/** + * For a given port number, return the base pko output queue + * for the port. + * + * @port: Port number + * Returns Base output queue + */ +static inline int cvmx_pko_get_base_queue(int port) +{ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + return port; + + return cvmx_pko_get_base_queue_per_core(port, 0); +} + +/** + * For a given port number, return the number of pko output queues. + * + * @port: Port number + * Returns Number of output queues + */ +static inline int cvmx_pko_get_num_queues(int port) +{ + if (port < 16) + return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0; + else if (port < 32) + return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1; + else if (port < 36) + return CVMX_PKO_QUEUES_PER_PORT_PCI; + else if (port < 40) + return CVMX_PKO_QUEUES_PER_PORT_LOOP; + else + return 0; +} + +/** + * Get the status counters for a port. + * + * @port_num: Port number to get statistics for. + * @clear: Set to 1 to clear the counters after they are read + * @status: Where to put the results. + */ +static inline void cvmx_pko_get_port_status(u64 port_num, u64 clear, + cvmx_pko_port_status_t *status) +{ + union cvmx_pko_reg_read_idx pko_reg_read_idx; + union cvmx_pko_mem_count0 pko_mem_count0; + union cvmx_pko_mem_count1 pko_mem_count1; + + pko_reg_read_idx.u64 = 0; + pko_reg_read_idx.s.index = port_num; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + + pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); + status->packets = pko_mem_count0.s.count; + if (clear) { + pko_mem_count0.s.count = port_num; + cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); + } + + pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); + status->octets = pko_mem_count1.s.count; + if (clear) { + pko_mem_count1.s.count = port_num; + cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); + } + + if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pko_mem_debug9 debug9; + + pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); + status->doorbell = debug9.cn38xx.doorbell; + } else { + union cvmx_pko_mem_debug8 debug8; + + pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); + status->doorbell = debug8.cn50xx.doorbell; + } +} + +/** + * Rate limit a PKO port to a max packets/sec. This function is only + * supported on CN57XX, CN56XX, CN55XX, and CN54XX. + * + * @port: Port to rate limit + * @packets_s: Maximum packet/sec + * @burst: Maximum number of packets to burst in a row before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); + +/** + * Rate limit a PKO port to a max bits/sec. This function is only + * supported on CN57XX, CN56XX, CN55XX, and CN54XX. + * + * @port: Port to rate limit + * @bits_s: PKO rate limit in bits/sec + * @burst: Maximum number of bits to burst before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +int cvmx_pko_rate_limit_bits(int port, u64 bits_s, int burst); + +#endif /* __CVMX_PKO_H__ */ diff --git a/drivers/staging/octeon/cvmx-pow-defs.h b/drivers/staging/octeon/cvmx-pow-defs.h new file mode 100644 index 000000000000..c840919596b8 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pow-defs.h @@ -0,0 +1,1000 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_POW_DEFS_H__ +#define __CVMX_POW_DEFS_H__ + +#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull)) +#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull)) +#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull)) +#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull)) +#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8) +#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull)) +#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull)) +#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull)) +#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8) +#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull)) +#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull)) +#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull)) +#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8) +#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8) +#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8) +#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull)) +#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull)) +#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8) +#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull)) +#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8) +#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull)) +#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8) +#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8) + +#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull)) +#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull)) +#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull)) +#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8) +#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8) + +union cvmx_pow_bist_stat { + u64 u64; + struct cvmx_pow_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pp:16; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 pp:16; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_pow_bist_stat_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 pp:1; + u64 reserved_9_15:7; + u64 cam:1; + u64 nbt1:1; + u64 nbt0:1; + u64 index:1; + u64 fidx:1; + u64 nbr1:1; + u64 nbr0:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 nbr0:1; + u64 nbr1:1; + u64 fidx:1; + u64 index:1; + u64 nbt0:1; + u64 nbt1:1; + u64 cam:1; + u64 reserved_9_15:7; + u64 pp:1; + u64 reserved_17_63:47; +#endif + } cn30xx; + struct cvmx_pow_bist_stat_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_18_63:46; + u64 pp:2; + u64 reserved_9_15:7; + u64 cam:1; + u64 nbt1:1; + u64 nbt0:1; + u64 index:1; + u64 fidx:1; + u64 nbr1:1; + u64 nbr0:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 nbr0:1; + u64 nbr1:1; + u64 fidx:1; + u64 index:1; + u64 nbt0:1; + u64 nbt1:1; + u64 cam:1; + u64 reserved_9_15:7; + u64 pp:2; + u64 reserved_18_63:46; +#endif + } cn31xx; + struct cvmx_pow_bist_stat_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 pp:16; + u64 reserved_10_15:6; + u64 cam:1; + u64 nbt:1; + u64 index:1; + u64 fidx:1; + u64 nbr1:1; + u64 nbr0:1; + u64 pend1:1; + u64 pend0:1; + u64 adr1:1; + u64 adr0:1; +#else + u64 adr0:1; + u64 adr1:1; + u64 pend0:1; + u64 pend1:1; + u64 nbr0:1; + u64 nbr1:1; + u64 fidx:1; + u64 index:1; + u64 nbt:1; + u64 cam:1; + u64 reserved_10_15:6; + u64 pp:16; + u64 reserved_32_63:32; +#endif + } cn38xx; + struct cvmx_pow_bist_stat_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pp:4; + u64 reserved_9_15:7; + u64 cam:1; + u64 nbt1:1; + u64 nbt0:1; + u64 index:1; + u64 fidx:1; + u64 nbr1:1; + u64 nbr0:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 nbr0:1; + u64 nbr1:1; + u64 fidx:1; + u64 index:1; + u64 nbt0:1; + u64 nbt1:1; + u64 cam:1; + u64 reserved_9_15:7; + u64 pp:4; + u64 reserved_20_63:44; +#endif + } cn52xx; + struct cvmx_pow_bist_stat_cn56xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 pp:12; + u64 reserved_10_15:6; + u64 cam:1; + u64 nbt:1; + u64 index:1; + u64 fidx:1; + u64 nbr1:1; + u64 nbr0:1; + u64 pend1:1; + u64 pend0:1; + u64 adr1:1; + u64 adr0:1; +#else + u64 adr0:1; + u64 adr1:1; + u64 pend0:1; + u64 pend1:1; + u64 nbr0:1; + u64 nbr1:1; + u64 fidx:1; + u64 index:1; + u64 nbt:1; + u64 cam:1; + u64 reserved_10_15:6; + u64 pp:12; + u64 reserved_28_63:36; +#endif + } cn56xx; + struct cvmx_pow_bist_stat_cn61xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 pp:4; + u64 reserved_12_15:4; + u64 cam:1; + u64 nbr:3; + u64 nbt:4; + u64 index:1; + u64 fidx:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 fidx:1; + u64 index:1; + u64 nbt:4; + u64 nbr:3; + u64 cam:1; + u64 reserved_12_15:4; + u64 pp:4; + u64 reserved_20_63:44; +#endif + } cn61xx; + struct cvmx_pow_bist_stat_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 pp:6; + u64 reserved_12_15:4; + u64 cam:1; + u64 nbr:3; + u64 nbt:4; + u64 index:1; + u64 fidx:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 fidx:1; + u64 index:1; + u64 nbt:4; + u64 nbr:3; + u64 cam:1; + u64 reserved_12_15:4; + u64 pp:6; + u64 reserved_22_63:42; +#endif + } cn63xx; + struct cvmx_pow_bist_stat_cn66xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_26_63:38; + u64 pp:10; + u64 reserved_12_15:4; + u64 cam:1; + u64 nbr:3; + u64 nbt:4; + u64 index:1; + u64 fidx:1; + u64 pend:1; + u64 adr:1; +#else + u64 adr:1; + u64 pend:1; + u64 fidx:1; + u64 index:1; + u64 nbt:4; + u64 nbr:3; + u64 cam:1; + u64 reserved_12_15:4; + u64 pp:10; + u64 reserved_26_63:38; +#endif + } cn66xx; +}; + +union cvmx_pow_ds_pc { + u64 u64; + struct cvmx_pow_ds_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ds_pc:32; +#else + u64 ds_pc:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_ecc_err { + u64 u64; + struct cvmx_pow_ecc_err_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 iop_ie:13; + u64 reserved_29_31:3; + u64 iop:13; + u64 reserved_14_15:2; + u64 rpe_ie:1; + u64 rpe:1; + u64 reserved_9_11:3; + u64 syn:5; + u64 dbe_ie:1; + u64 sbe_ie:1; + u64 dbe:1; + u64 sbe:1; +#else + u64 sbe:1; + u64 dbe:1; + u64 sbe_ie:1; + u64 dbe_ie:1; + u64 syn:5; + u64 reserved_9_11:3; + u64 rpe:1; + u64 rpe_ie:1; + u64 reserved_14_15:2; + u64 iop:13; + u64 reserved_29_31:3; + u64 iop_ie:13; + u64 reserved_45_63:19; +#endif + } s; + struct cvmx_pow_ecc_err_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 rpe_ie:1; + u64 rpe:1; + u64 reserved_9_11:3; + u64 syn:5; + u64 dbe_ie:1; + u64 sbe_ie:1; + u64 dbe:1; + u64 sbe:1; +#else + u64 sbe:1; + u64 dbe:1; + u64 sbe_ie:1; + u64 dbe_ie:1; + u64 syn:5; + u64 reserved_9_11:3; + u64 rpe:1; + u64 rpe_ie:1; + u64 reserved_14_63:50; +#endif + } cn31xx; +}; + +union cvmx_pow_int_ctl { + u64 u64; + struct cvmx_pow_int_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 pfr_dis:1; + u64 nbr_thr:5; +#else + u64 nbr_thr:5; + u64 pfr_dis:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_pow_iq_cntx { + u64 u64; + struct cvmx_pow_iq_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iq_cnt:32; +#else + u64 iq_cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_iq_com_cnt { + u64 u64; + struct cvmx_pow_iq_com_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iq_cnt:32; +#else + u64 iq_cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_iq_int { + u64 u64; + struct cvmx_pow_iq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 iq_int:8; +#else + u64 iq_int:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pow_iq_int_en { + u64 u64; + struct cvmx_pow_iq_int_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 int_en:8; +#else + u64 int_en:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pow_iq_thrx { + u64 u64; + struct cvmx_pow_iq_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iq_thr:32; +#else + u64 iq_thr:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_nos_cnt { + u64 u64; + struct cvmx_pow_nos_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 nos_cnt:12; +#else + u64 nos_cnt:12; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_pow_nos_cnt_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 nos_cnt:7; +#else + u64 nos_cnt:7; + u64 reserved_7_63:57; +#endif + } cn30xx; + struct cvmx_pow_nos_cnt_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 nos_cnt:9; +#else + u64 nos_cnt:9; + u64 reserved_9_63:55; +#endif + } cn31xx; + struct cvmx_pow_nos_cnt_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 nos_cnt:10; +#else + u64 nos_cnt:10; + u64 reserved_10_63:54; +#endif + } cn52xx; + struct cvmx_pow_nos_cnt_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 nos_cnt:11; +#else + u64 nos_cnt:11; + u64 reserved_11_63:53; +#endif + } cn63xx; +}; + +union cvmx_pow_nw_tim { + u64 u64; + struct cvmx_pow_nw_tim_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 nw_tim:10; +#else + u64 nw_tim:10; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_pow_pf_rst_msk { + u64 u64; + struct cvmx_pow_pf_rst_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 rst_msk:8; +#else + u64 rst_msk:8; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_pow_pp_grp_mskx { + u64 u64; + struct cvmx_pow_pp_grp_mskx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 qos7_pri:4; + u64 qos6_pri:4; + u64 qos5_pri:4; + u64 qos4_pri:4; + u64 qos3_pri:4; + u64 qos2_pri:4; + u64 qos1_pri:4; + u64 qos0_pri:4; + u64 grp_msk:16; +#else + u64 grp_msk:16; + u64 qos0_pri:4; + u64 qos1_pri:4; + u64 qos2_pri:4; + u64 qos3_pri:4; + u64 qos4_pri:4; + u64 qos5_pri:4; + u64 qos6_pri:4; + u64 qos7_pri:4; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_pow_pp_grp_mskx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 grp_msk:16; +#else + u64 grp_msk:16; + u64 reserved_16_63:48; +#endif + } cn30xx; +}; + +union cvmx_pow_qos_rndx { + u64 u64; + struct cvmx_pow_qos_rndx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 rnd_p3:8; + u64 rnd_p2:8; + u64 rnd_p1:8; + u64 rnd:8; +#else + u64 rnd:8; + u64 rnd_p1:8; + u64 rnd_p2:8; + u64 rnd_p3:8; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_qos_thrx { + u64 u64; + struct cvmx_pow_qos_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 des_cnt:12; + u64 buf_cnt:12; + u64 free_cnt:12; + u64 reserved_23_23:1; + u64 max_thr:11; + u64 reserved_11_11:1; + u64 min_thr:11; +#else + u64 min_thr:11; + u64 reserved_11_11:1; + u64 max_thr:11; + u64 reserved_23_23:1; + u64 free_cnt:12; + u64 buf_cnt:12; + u64 des_cnt:12; + u64 reserved_60_63:4; +#endif + } s; + struct cvmx_pow_qos_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_55_63:9; + u64 des_cnt:7; + u64 reserved_43_47:5; + u64 buf_cnt:7; + u64 reserved_31_35:5; + u64 free_cnt:7; + u64 reserved_18_23:6; + u64 max_thr:6; + u64 reserved_6_11:6; + u64 min_thr:6; +#else + u64 min_thr:6; + u64 reserved_6_11:6; + u64 max_thr:6; + u64 reserved_18_23:6; + u64 free_cnt:7; + u64 reserved_31_35:5; + u64 buf_cnt:7; + u64 reserved_43_47:5; + u64 des_cnt:7; + u64 reserved_55_63:9; +#endif + } cn30xx; + struct cvmx_pow_qos_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_57_63:7; + u64 des_cnt:9; + u64 reserved_45_47:3; + u64 buf_cnt:9; + u64 reserved_33_35:3; + u64 free_cnt:9; + u64 reserved_20_23:4; + u64 max_thr:8; + u64 reserved_8_11:4; + u64 min_thr:8; +#else + u64 min_thr:8; + u64 reserved_8_11:4; + u64 max_thr:8; + u64 reserved_20_23:4; + u64 free_cnt:9; + u64 reserved_33_35:3; + u64 buf_cnt:9; + u64 reserved_45_47:3; + u64 des_cnt:9; + u64 reserved_57_63:7; +#endif + } cn31xx; + struct cvmx_pow_qos_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_58_63:6; + u64 des_cnt:10; + u64 reserved_46_47:2; + u64 buf_cnt:10; + u64 reserved_34_35:2; + u64 free_cnt:10; + u64 reserved_21_23:3; + u64 max_thr:9; + u64 reserved_9_11:3; + u64 min_thr:9; +#else + u64 min_thr:9; + u64 reserved_9_11:3; + u64 max_thr:9; + u64 reserved_21_23:3; + u64 free_cnt:10; + u64 reserved_34_35:2; + u64 buf_cnt:10; + u64 reserved_46_47:2; + u64 des_cnt:10; + u64 reserved_58_63:6; +#endif + } cn52xx; + struct cvmx_pow_qos_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_59_63:5; + u64 des_cnt:11; + u64 reserved_47_47:1; + u64 buf_cnt:11; + u64 reserved_35_35:1; + u64 free_cnt:11; + u64 reserved_22_23:2; + u64 max_thr:10; + u64 reserved_10_11:2; + u64 min_thr:10; +#else + u64 min_thr:10; + u64 reserved_10_11:2; + u64 max_thr:10; + u64 reserved_22_23:2; + u64 free_cnt:11; + u64 reserved_35_35:1; + u64 buf_cnt:11; + u64 reserved_47_47:1; + u64 des_cnt:11; + u64 reserved_59_63:5; +#endif + } cn63xx; +}; + +union cvmx_pow_ts_pc { + u64 u64; + struct cvmx_pow_ts_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ts_pc:32; +#else + u64 ts_pc:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_wa_com_pc { + u64 u64; + struct cvmx_pow_wa_com_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wa_pc:32; +#else + u64 wa_pc:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_wa_pcx { + u64 u64; + struct cvmx_pow_wa_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 wa_pc:32; +#else + u64 wa_pc:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_wq_int { + u64 u64; + struct cvmx_pow_wq_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 iq_dis:16; + u64 wq_int:16; +#else + u64 wq_int:16; + u64 iq_dis:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_pow_wq_int_cntx { + u64 u64; + struct cvmx_pow_wq_int_cntx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 tc_cnt:4; + u64 ds_cnt:12; + u64 iq_cnt:12; +#else + u64 iq_cnt:12; + u64 ds_cnt:12; + u64 tc_cnt:4; + u64 reserved_28_63:36; +#endif + } s; + struct cvmx_pow_wq_int_cntx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 tc_cnt:4; + u64 reserved_19_23:5; + u64 ds_cnt:7; + u64 reserved_7_11:5; + u64 iq_cnt:7; +#else + u64 iq_cnt:7; + u64 reserved_7_11:5; + u64 ds_cnt:7; + u64 reserved_19_23:5; + u64 tc_cnt:4; + u64 reserved_28_63:36; +#endif + } cn30xx; + struct cvmx_pow_wq_int_cntx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 tc_cnt:4; + u64 reserved_21_23:3; + u64 ds_cnt:9; + u64 reserved_9_11:3; + u64 iq_cnt:9; +#else + u64 iq_cnt:9; + u64 reserved_9_11:3; + u64 ds_cnt:9; + u64 reserved_21_23:3; + u64 tc_cnt:4; + u64 reserved_28_63:36; +#endif + } cn31xx; + struct cvmx_pow_wq_int_cntx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 tc_cnt:4; + u64 reserved_22_23:2; + u64 ds_cnt:10; + u64 reserved_10_11:2; + u64 iq_cnt:10; +#else + u64 iq_cnt:10; + u64 reserved_10_11:2; + u64 ds_cnt:10; + u64 reserved_22_23:2; + u64 tc_cnt:4; + u64 reserved_28_63:36; +#endif + } cn52xx; + struct cvmx_pow_wq_int_cntx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 tc_cnt:4; + u64 reserved_23_23:1; + u64 ds_cnt:11; + u64 reserved_11_11:1; + u64 iq_cnt:11; +#else + u64 iq_cnt:11; + u64 reserved_11_11:1; + u64 ds_cnt:11; + u64 reserved_23_23:1; + u64 tc_cnt:4; + u64 reserved_28_63:36; +#endif + } cn63xx; +}; + +union cvmx_pow_wq_int_pc { + u64 u64; + struct cvmx_pow_wq_int_pc_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_60_63:4; + u64 pc:28; + u64 reserved_28_31:4; + u64 pc_thr:20; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 pc_thr:20; + u64 reserved_28_31:4; + u64 pc:28; + u64 reserved_60_63:4; +#endif + } s; +}; + +union cvmx_pow_wq_int_thrx { + u64 u64; + struct cvmx_pow_wq_int_thrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_23_23:1; + u64 ds_thr:11; + u64 reserved_11_11:1; + u64 iq_thr:11; +#else + u64 iq_thr:11; + u64 reserved_11_11:1; + u64 ds_thr:11; + u64 reserved_23_23:1; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_29_63:35; +#endif + } s; + struct cvmx_pow_wq_int_thrx_cn30xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_18_23:6; + u64 ds_thr:6; + u64 reserved_6_11:6; + u64 iq_thr:6; +#else + u64 iq_thr:6; + u64 reserved_6_11:6; + u64 ds_thr:6; + u64 reserved_18_23:6; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_29_63:35; +#endif + } cn30xx; + struct cvmx_pow_wq_int_thrx_cn31xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_20_23:4; + u64 ds_thr:8; + u64 reserved_8_11:4; + u64 iq_thr:8; +#else + u64 iq_thr:8; + u64 reserved_8_11:4; + u64 ds_thr:8; + u64 reserved_20_23:4; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_29_63:35; +#endif + } cn31xx; + struct cvmx_pow_wq_int_thrx_cn52xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_21_23:3; + u64 ds_thr:9; + u64 reserved_9_11:3; + u64 iq_thr:9; +#else + u64 iq_thr:9; + u64 reserved_9_11:3; + u64 ds_thr:9; + u64 reserved_21_23:3; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_29_63:35; +#endif + } cn52xx; + struct cvmx_pow_wq_int_thrx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_29_63:35; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_22_23:2; + u64 ds_thr:10; + u64 reserved_10_11:2; + u64 iq_thr:10; +#else + u64 iq_thr:10; + u64 reserved_10_11:2; + u64 ds_thr:10; + u64 reserved_22_23:2; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_29_63:35; +#endif + } cn63xx; +}; + +union cvmx_pow_ws_pcx { + u64 u64; + struct cvmx_pow_ws_pcx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 ws_pc:32; +#else + u64 ws_pc:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sso_wq_int_thrx { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 tc_en:1; + u64 tc_thr:4; + u64 reserved_26_27:2; + u64 ds_thr:12; + u64 reserved_12_13:2; + u64 iq_thr:12; +#else + u64 iq_thr:12; + u64 reserved_12_13:2; + u64 ds_thr:12; + u64 reserved_26_27:2; + u64 tc_thr:4; + u64 tc_en:1; + u64 reserved_33_63:31; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pow.h b/drivers/staging/octeon/cvmx-pow.h new file mode 100644 index 000000000000..83a025f57e31 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pow.h @@ -0,0 +1,2219 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * Interface to the hardware Packet Order / Work unit. + * + * New, starting with SDK 1.7.0, cvmx-pow supports a number of + * extended consistency checks. The define + * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW + * internal state checks to find common programming errors. If + * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default + * enabled. For example, cvmx-pow will check for the following + * program errors or POW state inconsistency. + * - Requesting a POW operation with an active tag switch in + * progress. + * - Waiting for a tag switch to complete for an excessively + * long period. This is normally a sign of an error in locking + * causing deadlock. + * - Illegal tag switches from NULL_NULL. + * - Illegal tag switches from NULL. + * - Illegal deschedule request. + * - WQE pointer not matching the one attached to the core by + * the POW. + * + */ + +#ifndef __CVMX_POW_H__ +#define __CVMX_POW_H__ + +#include "cvmx-pow-defs.h" + +#include "cvmx-scratch.h" +#include "cvmx-wqe.h" + +/* Default to having all POW constancy checks turned on */ +#ifndef CVMX_ENABLE_POW_CHECKS +#define CVMX_ENABLE_POW_CHECKS 1 +#endif + +enum cvmx_pow_tag_type { + /* Tag ordering is maintained */ + CVMX_POW_TAG_TYPE_ORDERED = 0L, + /* Tag ordering is maintained, and at most one PP has the tag */ + CVMX_POW_TAG_TYPE_ATOMIC = 1L, + /* + * The work queue entry from the order - NEVER tag switch from + * NULL to NULL + */ + CVMX_POW_TAG_TYPE_NULL = 2L, + /* A tag switch to NULL, and there is no space reserved in POW + * - NEVER tag switch to NULL_NULL + * - NEVER tag switch from NULL_NULL + * - NULL_NULL is entered at the beginning of time and on a deschedule. + * - NULL_NULL can be exited by a new work request. A NULL_SWITCH + * load can also switch the state to NULL + */ + CVMX_POW_TAG_TYPE_NULL_NULL = 3L +}; + +/** + * Wait flag values for pow functions. + */ +typedef enum { + CVMX_POW_WAIT = 1, + CVMX_POW_NO_WAIT = 0, +} cvmx_pow_wait_t; + +/** + * POW tag operations. These are used in the data stored to the POW. + */ +typedef enum { + /* + * switch the tag (only) for this PP + * - the previous tag should be non-NULL in this case + * - tag switch response required + * - fields used: op, type, tag + */ + CVMX_POW_TAG_OP_SWTAG = 0L, + /* + * switch the tag for this PP, with full information + * - this should be used when the previous tag is NULL + * - tag switch response required + * - fields used: address, op, grp, type, tag + */ + CVMX_POW_TAG_OP_SWTAG_FULL = 1L, + /* + * switch the tag (and/or group) for this PP and de-schedule + * - OK to keep the tag the same and only change the group + * - fields used: op, no_sched, grp, type, tag + */ + CVMX_POW_TAG_OP_SWTAG_DESCH = 2L, + /* + * just de-schedule + * - fields used: op, no_sched + */ + CVMX_POW_TAG_OP_DESCH = 3L, + /* + * create an entirely new work queue entry + * - fields used: address, op, qos, grp, type, tag + */ + CVMX_POW_TAG_OP_ADDWQ = 4L, + /* + * just update the work queue pointer and grp for this PP + * - fields used: address, op, grp + */ + CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L, + /* + * set the no_sched bit on the de-schedule list + * + * - does nothing if the selected entry is not on the + * de-schedule list + * + * - does nothing if the stored work queue pointer does not + * match the address field + * + * - fields used: address, index, op + * + * Before issuing a *_NSCHED operation, SW must guarantee + * that all prior deschedules and set/clr NSCHED operations + * are complete and all prior switches are complete. The + * hardware provides the opsdone bit and swdone bit for SW + * polling. After issuing a *_NSCHED operation, SW must + * guarantee that the set/clr NSCHED is complete before any + * subsequent operations. + */ + CVMX_POW_TAG_OP_SET_NSCHED = 6L, + /* + * clears the no_sched bit on the de-schedule list + * + * - does nothing if the selected entry is not on the + * de-schedule list + * + * - does nothing if the stored work queue pointer does not + * match the address field + * + * - fields used: address, index, op + * + * Before issuing a *_NSCHED operation, SW must guarantee that + * all prior deschedules and set/clr NSCHED operations are + * complete and all prior switches are complete. The hardware + * provides the opsdone bit and swdone bit for SW + * polling. After issuing a *_NSCHED operation, SW must + * guarantee that the set/clr NSCHED is complete before any + * subsequent operations. + */ + CVMX_POW_TAG_OP_CLR_NSCHED = 7L, + /* do nothing */ + CVMX_POW_TAG_OP_NOP = 15L +} cvmx_pow_tag_op_t; + +/** + * This structure defines the store data on a store to POW + */ +typedef union { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * Don't reschedule this entry. no_sched is used for + * CVMX_POW_TAG_OP_SWTAG_DESCH and + * CVMX_POW_TAG_OP_DESCH + */ + u64 no_sched:1; + u64 unused:2; + /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */ + u64 index:13; + /* The operation to perform */ + cvmx_pow_tag_op_t op:4; + u64 unused2:2; + /* + * The QOS level for the packet. qos is only used for + * CVMX_POW_TAG_OP_ADDWQ + */ + u64 qos:3; + /* + * The group that the work queue entry will be + * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, + * CVMX_POW_TAG_OP_SWTAG_FULL, + * CVMX_POW_TAG_OP_SWTAG_DESCH, and + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP + */ + u64 grp:4; + /* + * The type of the tag. type is used for everything + * except CVMX_POW_TAG_OP_DESCH, + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and + * CVMX_POW_TAG_OP_*_NSCHED + */ + u64 type:3; + /* + * The actual tag. tag is used for everything except + * CVMX_POW_TAG_OP_DESCH, + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and + * CVMX_POW_TAG_OP_*_NSCHED + */ + u64 tag:32; +#else + u64 tag:32; + u64 type:3; + u64 grp:4; + u64 qos:3; + u64 unused2:2; + cvmx_pow_tag_op_t op:4; + u64 index:13; + u64 unused:2; + u64 no_sched:1; +#endif + } s; +} cvmx_pow_tag_req_t; + +/** + * This structure describes the address to load stuff from POW + */ +typedef union { + u64 u64; + + /** + * Address for new work request loads (did<2:0> == 0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Mips64 address region. Should be CVMX_IO_SEG */ + u64 mem_region:2; + /* Must be zero */ + u64 reserved_49_61:13; + /* Must be one */ + u64 is_io:1; + /* the ID of POW -- did<2:0> == 0 in this case */ + u64 did:8; + /* Must be zero */ + u64 reserved_4_39:36; + /* + * If set, don't return load response until work is + * available. + */ + u64 wait:1; + /* Must be zero */ + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 wait:1; + u64 reserved_4_39:36; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_region:2; +#endif + } swork; + + /** + * Address for loads to get POW internal status + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Mips64 address region. Should be CVMX_IO_SEG */ + u64 mem_region:2; + /* Must be zero */ + u64 reserved_49_61:13; + /* Must be one */ + u64 is_io:1; + /* the ID of POW -- did<2:0> == 1 in this case */ + u64 did:8; + /* Must be zero */ + u64 reserved_10_39:30; + /* The core id to get status for */ + u64 coreid:4; + /* + * If set and get_cur is set, return reverse tag-list + * pointer rather than forward tag-list pointer. + */ + u64 get_rev:1; + /* + * If set, return current status rather than pending + * status. + */ + u64 get_cur:1; + /* + * If set, get the work-queue pointer rather than + * tag/type. + */ + u64 get_wqp:1; + /* Must be zero */ + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 get_wqp:1; + u64 get_cur:1; + u64 get_rev:1; + u64 coreid:4; + u64 reserved_10_39:30; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_region:2; +#endif + } sstatus; + + /** + * Address for memory loads to get POW internal state + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Mips64 address region. Should be CVMX_IO_SEG */ + u64 mem_region:2; + /* Must be zero */ + u64 reserved_49_61:13; + /* Must be one */ + u64 is_io:1; + /* the ID of POW -- did<2:0> == 2 in this case */ + u64 did:8; + /* Must be zero */ + u64 reserved_16_39:24; + /* POW memory index */ + u64 index:11; + /* + * If set, return deschedule information rather than + * the standard response for work-queue index (invalid + * if the work-queue entry is not on the deschedule + * list). + */ + u64 get_des:1; + /* + * If set, get the work-queue pointer rather than + * tag/type (no effect when get_des set). + */ + u64 get_wqp:1; + /* Must be zero */ + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 get_wqp:1; + u64 get_des:1; + u64 index:11; + u64 reserved_16_39:24; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_region:2; +#endif + } smemload; + + /** + * Address for index/pointer loads + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Mips64 address region. Should be CVMX_IO_SEG */ + u64 mem_region:2; + /* Must be zero */ + u64 reserved_49_61:13; + /* Must be one */ + u64 is_io:1; + /* the ID of POW -- did<2:0> == 3 in this case */ + u64 did:8; + /* Must be zero */ + u64 reserved_9_39:31; + /* + * when {get_rmt ==0 AND get_des_get_tail == 0}, this + * field selects one of eight POW internal-input + * queues (0-7), one per QOS level; values 8-15 are + * illegal in this case; when {get_rmt ==0 AND + * get_des_get_tail == 1}, this field selects one of + * 16 deschedule lists (per group); when get_rmt ==1, + * this field selects one of 16 memory-input queue + * lists. The two memory-input queue lists associated + * with each QOS level are: + * + * - qosgrp = 0, qosgrp = 8: QOS0 + * - qosgrp = 1, qosgrp = 9: QOS1 + * - qosgrp = 2, qosgrp = 10: QOS2 + * - qosgrp = 3, qosgrp = 11: QOS3 + * - qosgrp = 4, qosgrp = 12: QOS4 + * - qosgrp = 5, qosgrp = 13: QOS5 + * - qosgrp = 6, qosgrp = 14: QOS6 + * - qosgrp = 7, qosgrp = 15: QOS7 + */ + u64 qosgrp:4; + /* + * If set and get_rmt is clear, return deschedule list + * indexes rather than indexes for the specified qos + * level; if set and get_rmt is set, return the tail + * pointer rather than the head pointer for the + * specified qos level. + */ + u64 get_des_get_tail:1; + /* + * If set, return remote pointers rather than the + * local indexes for the specified qos level. + */ + u64 get_rmt:1; + /* Must be zero */ + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 get_rmt:1; + u64 get_des_get_tail:1; + u64 qosgrp:4; + u64 reserved_9_39:31; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_region:2; +#endif + } sindexload; + + /** + * address for NULL_RD request (did<2:0> == 4) when this is read, + * HW attempts to change the state to NULL if it is NULL_NULL (the + * hardware cannot switch from NULL_NULL to NULL if a POW entry is + * not available - software may need to recover by finishing + * another piece of work before a POW entry can ever become + * available.) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Mips64 address region. Should be CVMX_IO_SEG */ + u64 mem_region:2; + /* Must be zero */ + u64 reserved_49_61:13; + /* Must be one */ + u64 is_io:1; + /* the ID of POW -- did<2:0> == 4 in this case */ + u64 did:8; + /* Must be zero */ + u64 reserved_0_39:40; +#else + u64 reserved_0_39:40; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_region:2; +#endif + } snull_rd; +} cvmx_pow_load_addr_t; + +/** + * This structure defines the response to a load/SENDSINGLE to POW + * (except CSR reads) + */ +typedef union { + u64 u64; + + /** + * Response to new work request loads + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * Set when no new work queue entry was returned. * + * If there was de-scheduled work, the HW will + * definitely return it. When this bit is set, it + * could mean either mean: + * + * - There was no work, or + * + * - There was no work that the HW could find. This + * case can happen, regardless of the wait bit value + * in the original request, when there is work in + * the IQ's that is too deep down the list. + */ + u64 no_work:1; + /* Must be zero */ + u64 reserved_40_62:23; + /* 36 in O1 -- the work queue pointer */ + u64 addr:40; +#else + u64 addr:40; + u64 reserved_40_62:23; + u64 no_work:1; +#endif + } s_work; + + /** + * Result for a POW Status Load (when get_cur==0 and get_wqp==0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* Set when there is a pending non-NULL SWTAG or + * SWTAG_FULL, and the POW entry has not left the list + * for the original tag. */ + u64 pend_switch:1; + /* Set when SWTAG_FULL and pend_switch is set. */ + u64 pend_switch_full:1; + /* + * Set when there is a pending NULL SWTAG, or an + * implicit switch to NULL. + */ + u64 pend_switch_null:1; + /* Set when there is a pending DESCHED or SWTAG_DESCHED. */ + u64 pend_desched:1; + /* + * Set when there is a pending SWTAG_DESCHED and + * pend_desched is set. + */ + u64 pend_desched_switch:1; + /* Set when nosched is desired and pend_desched is set. */ + u64 pend_nosched:1; + /* Set when there is a pending GET_WORK. */ + u64 pend_new_work:1; + /* + * When pend_new_work is set, this bit indicates that + * the wait bit was set. + */ + u64 pend_new_work_wait:1; + /* Set when there is a pending NULL_RD. */ + u64 pend_null_rd:1; + /* Set when there is a pending CLR_NSCHED. */ + u64 pend_nosched_clr:1; + u64 reserved_51:1; + /* This is the index when pend_nosched_clr is set. */ + u64 pend_index:11; + /* + * This is the new_grp when (pend_desched AND + * pend_desched_switch) is set. + */ + u64 pend_grp:4; + u64 reserved_34_35:2; + /* + * This is the tag type when pend_switch or + * (pend_desched AND pend_desched_switch) are set. + */ + u64 pend_type:2; + /* + * - this is the tag when pend_switch or (pend_desched + * AND pend_desched_switch) are set. + */ + u64 pend_tag:32; +#else + u64 pend_tag:32; + u64 pend_type:2; + u64 reserved_34_35:2; + u64 pend_grp:4; + u64 pend_index:11; + u64 reserved_51:1; + u64 pend_nosched_clr:1; + u64 pend_null_rd:1; + u64 pend_new_work_wait:1; + u64 pend_new_work:1; + u64 pend_nosched:1; + u64 pend_desched_switch:1; + u64 pend_desched:1; + u64 pend_switch_null:1; + u64 pend_switch_full:1; + u64 pend_switch:1; + u64 reserved_62_63:2; +#endif + } s_sstatus0; + + /** + * Result for a POW Status Load (when get_cur==0 and get_wqp==1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* + * Set when there is a pending non-NULL SWTAG or + * SWTAG_FULL, and the POW entry has not left the list + * for the original tag. + */ + u64 pend_switch:1; + /* Set when SWTAG_FULL and pend_switch is set. */ + u64 pend_switch_full:1; + /* + * Set when there is a pending NULL SWTAG, or an + * implicit switch to NULL. + */ + u64 pend_switch_null:1; + /* + * Set when there is a pending DESCHED or + * SWTAG_DESCHED. + */ + u64 pend_desched:1; + /* + * Set when there is a pending SWTAG_DESCHED and + * pend_desched is set. + */ + u64 pend_desched_switch:1; + /* Set when nosched is desired and pend_desched is set. */ + u64 pend_nosched:1; + /* Set when there is a pending GET_WORK. */ + u64 pend_new_work:1; + /* + * When pend_new_work is set, this bit indicates that + * the wait bit was set. + */ + u64 pend_new_work_wait:1; + /* Set when there is a pending NULL_RD. */ + u64 pend_null_rd:1; + /* Set when there is a pending CLR_NSCHED. */ + u64 pend_nosched_clr:1; + u64 reserved_51:1; + /* This is the index when pend_nosched_clr is set. */ + u64 pend_index:11; + /* + * This is the new_grp when (pend_desched AND + * pend_desched_switch) is set. + */ + u64 pend_grp:4; + /* This is the wqp when pend_nosched_clr is set. */ + u64 pend_wqp:36; +#else + u64 pend_wqp:36; + u64 pend_grp:4; + u64 pend_index:11; + u64 reserved_51:1; + u64 pend_nosched_clr:1; + u64 pend_null_rd:1; + u64 pend_new_work_wait:1; + u64 pend_new_work:1; + u64 pend_nosched:1; + u64 pend_desched_switch:1; + u64 pend_desched:1; + u64 pend_switch_null:1; + u64 pend_switch_full:1; + u64 pend_switch:1; + u64 reserved_62_63:2; +#endif + } s_sstatus1; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==0, and + * get_rev==0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* + * Points to the next POW entry in the tag list when + * tail == 0 (and tag_type is not NULL or NULL_NULL). + */ + u64 link_index:11; + /* The POW entry attached to the core. */ + u64 index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + u64 grp:4; + /* + * Set when this POW entry is at the head of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + u64 head:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + u64 tail:1; + /* + * The tag type attached to the core (updated when new + * tag list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + u64 tag_type:2; + /* + * The tag attached to the core (updated when new tag + * list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 tail:1; + u64 head:1; + u64 grp:4; + u64 index:11; + u64 link_index:11; + u64 reserved_62_63:2; +#endif + } s_sstatus2; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* + * Points to the prior POW entry in the tag list when + * head == 0 (and tag_type is not NULL or + * NULL_NULL). This field is unpredictable when the + * core's state is NULL or NULL_NULL. + */ + u64 revlink_index:11; + /* The POW entry attached to the core. */ + u64 index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + u64 grp:4; + /* Set when this POW entry is at the head of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + u64 head:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + u64 tail:1; + /* + * The tag type attached to the core (updated when new + * tag list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + u64 tag_type:2; + /* + * The tag attached to the core (updated when new tag + * list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 tail:1; + u64 head:1; + u64 grp:4; + u64 index:11; + u64 revlink_index:11; + u64 reserved_62_63:2; +#endif + } s_sstatus3; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==1, and + * get_rev==0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* + * Points to the next POW entry in the tag list when + * tail == 0 (and tag_type is not NULL or NULL_NULL). + */ + u64 link_index:11; + /* The POW entry attached to the core. */ + u64 index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + u64 grp:4; + /* + * The wqp attached to the core (updated when new tag + * list entered on SWTAG_FULL). + */ + u64 wqp:36; +#else + u64 wqp:36; + u64 grp:4; + u64 index:11; + u64 link_index:11; + u64 reserved_62_63:2; +#endif + } s_sstatus4; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==1, and + * get_rev==1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_62_63:2; + /* + * Points to the prior POW entry in the tag list when + * head == 0 (and tag_type is not NULL or + * NULL_NULL). This field is unpredictable when the + * core's state is NULL or NULL_NULL. + */ + u64 revlink_index:11; + /* The POW entry attached to the core. */ + u64 index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + u64 grp:4; + /* + * The wqp attached to the core (updated when new tag + * list entered on SWTAG_FULL). + */ + u64 wqp:36; +#else + u64 wqp:36; + u64 grp:4; + u64 index:11; + u64 revlink_index:11; + u64 reserved_62_63:2; +#endif + } s_sstatus5; + + /** + * Result For POW Memory Load (get_des == 0 and get_wqp == 0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + /* + * The next entry in the input, free, descheduled_head + * list (unpredictable if entry is the tail of the + * list). + */ + u64 next_index:11; + /* The group of the POW entry. */ + u64 grp:4; + u64 reserved_35:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + u64 tail:1; + /* The tag type of the POW entry. */ + u64 tag_type:2; + /* The tag of the POW entry. */ + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 tail:1; + u64 reserved_35:1; + u64 grp:4; + u64 next_index:11; + u64 reserved_51_63:13; +#endif + } s_smemload0; + + /** + * Result For POW Memory Load (get_des == 0 and get_wqp == 1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + /* + * The next entry in the input, free, descheduled_head + * list (unpredictable if entry is the tail of the + * list). + */ + u64 next_index:11; + /* The group of the POW entry. */ + u64 grp:4; + /* The WQP held in the POW entry. */ + u64 wqp:36; +#else + u64 wqp:36; + u64 grp:4; + u64 next_index:11; + u64 reserved_51_63:13; +#endif + } s_smemload1; + + /** + * Result For POW Memory Load (get_des == 1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_51_63:13; + /* + * The next entry in the tag list connected to the + * descheduled head. + */ + u64 fwd_index:11; + /* The group of the POW entry. */ + u64 grp:4; + /* The nosched bit for the POW entry. */ + u64 nosched:1; + /* There is a pending tag switch */ + u64 pend_switch:1; + /* + * The next tag type for the new tag list when + * pend_switch is set. + */ + u64 pend_type:2; + /* + * The next tag for the new tag list when pend_switch + * is set. + */ + u64 pend_tag:32; +#else + u64 pend_tag:32; + u64 pend_type:2; + u64 pend_switch:1; + u64 nosched:1; + u64 grp:4; + u64 fwd_index:11; + u64 reserved_51_63:13; +#endif + } s_smemload2; + + /** + * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + /* + * set when there is one or more POW entries on the + * free list. + */ + u64 free_val:1; + /* + * set when there is exactly one POW entry on the free + * list. + */ + u64 free_one:1; + u64 reserved_49:1; + /* + * when free_val is set, indicates the first entry on + * the free list. + */ + u64 free_head:11; + u64 reserved_37:1; + /* + * when free_val is set, indicates the last entry on + * the free list. + */ + u64 free_tail:11; + /* + * set when there is one or more POW entries on the + * input Q list selected by qosgrp. + */ + u64 loc_val:1; + /* + * set when there is exactly one POW entry on the + * input Q list selected by qosgrp. + */ + u64 loc_one:1; + u64 reserved_23:1; + /* + * when loc_val is set, indicates the first entry on + * the input Q list selected by qosgrp. + */ + u64 loc_head:11; + u64 reserved_11:1; + /* + * when loc_val is set, indicates the last entry on + * the input Q list selected by qosgrp. + */ + u64 loc_tail:11; +#else + u64 loc_tail:11; + u64 reserved_11:1; + u64 loc_head:11; + u64 reserved_23:1; + u64 loc_one:1; + u64 loc_val:1; + u64 free_tail:11; + u64 reserved_37:1; + u64 free_head:11; + u64 reserved_49:1; + u64 free_one:1; + u64 free_val:1; + u64 reserved_52_63:12; +#endif + } sindexload0; + + /** + * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_52_63:12; + /* + * set when there is one or more POW entries on the + * nosched list. + */ + u64 nosched_val:1; + /* + * set when there is exactly one POW entry on the + * nosched list. + */ + u64 nosched_one:1; + u64 reserved_49:1; + /* + * when nosched_val is set, indicates the first entry + * on the nosched list. + */ + u64 nosched_head:11; + u64 reserved_37:1; + /* + * when nosched_val is set, indicates the last entry + * on the nosched list. + */ + u64 nosched_tail:11; + /* + * set when there is one or more descheduled heads on + * the descheduled list selected by qosgrp. + */ + u64 des_val:1; + /* + * set when there is exactly one descheduled head on + * the descheduled list selected by qosgrp. + */ + u64 des_one:1; + u64 reserved_23:1; + /* + * when des_val is set, indicates the first + * descheduled head on the descheduled list selected + * by qosgrp. + */ + u64 des_head:11; + u64 reserved_11:1; + /* + * when des_val is set, indicates the last descheduled + * head on the descheduled list selected by qosgrp. + */ + u64 des_tail:11; +#else + u64 des_tail:11; + u64 reserved_11:1; + u64 des_head:11; + u64 reserved_23:1; + u64 des_one:1; + u64 des_val:1; + u64 nosched_tail:11; + u64 reserved_37:1; + u64 nosched_head:11; + u64 reserved_49:1; + u64 nosched_one:1; + u64 nosched_val:1; + u64 reserved_52_63:12; +#endif + } sindexload1; + + /** + * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + /* + * Set when this DRAM list is the current head + * (i.e. is the next to be reloaded when the POW + * hardware reloads a POW entry from DRAM). The POW + * hardware alternates between the two DRAM lists + * associated with a QOS level when it reloads work + * from DRAM into the POW unit. + */ + u64 rmt_is_head:1; + /* + * Set when the DRAM portion of the input Q list + * selected by qosgrp contains one or more pieces of + * work. + */ + u64 rmt_val:1; + /* + * Set when the DRAM portion of the input Q list + * selected by qosgrp contains exactly one piece of + * work. + */ + u64 rmt_one:1; + /* + * When rmt_val is set, indicates the first piece of + * work on the DRAM input Q list selected by + * qosgrp. + */ + u64 rmt_head:36; +#else + u64 rmt_head:36; + u64 rmt_one:1; + u64 rmt_val:1; + u64 rmt_is_head:1; + u64 reserved_39_63:25; +#endif + } sindexload2; + + /** + * Result For POW Index/Pointer Load (get_rmt == + * 1/get_des_get_tail == 1) + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_39_63:25; + /* + * set when this DRAM list is the current head + * (i.e. is the next to be reloaded when the POW + * hardware reloads a POW entry from DRAM). The POW + * hardware alternates between the two DRAM lists + * associated with a QOS level when it reloads work + * from DRAM into the POW unit. + */ + u64 rmt_is_head:1; + /* + * set when the DRAM portion of the input Q list + * selected by qosgrp contains one or more pieces of + * work. + */ + u64 rmt_val:1; + /* + * set when the DRAM portion of the input Q list + * selected by qosgrp contains exactly one piece of + * work. + */ + u64 rmt_one:1; + /* + * when rmt_val is set, indicates the last piece of + * work on the DRAM input Q list selected by + * qosgrp. + */ + u64 rmt_tail:36; +#else + u64 rmt_tail:36; + u64 rmt_one:1; + u64 rmt_val:1; + u64 rmt_is_head:1; + u64 reserved_39_63:25; +#endif + } sindexload3; + + /** + * Response to NULL_RD request loads + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 unused:62; + /* of type cvmx_pow_tag_type_t. state is one of the + * following: + * + * - CVMX_POW_TAG_TYPE_ORDERED + * - CVMX_POW_TAG_TYPE_ATOMIC + * - CVMX_POW_TAG_TYPE_NULL + * - CVMX_POW_TAG_TYPE_NULL_NULL + */ + u64 state:2; +#else + u64 state:2; + u64 unused:62; +#endif + } s_null_rd; + +} cvmx_pow_tag_load_resp_t; + +/** + * This structure describes the address used for stores to the POW. + * The store address is meaningful on stores to the POW. The + * hardware assumes that an aligned 64-bit store was used for all + * these stores. Note the assumption that the work queue entry is + * aligned on an 8-byte boundary (since the low-order 3 address bits + * must be zero). Note that not all fields are used by all + * operations. + * + * NOTE: The following is the behavior of the pending switch bit at the PP + * for POW stores (i.e. when did<7:3> == 0xc) + * - did<2:0> == 0 => pending switch bit is set + * - did<2:0> == 1 => no affect on the pending switch bit + * - did<2:0> == 3 => pending switch bit is cleared + * - did<2:0> == 7 => no affect on the pending switch bit + * - did<2:0> == others => must not be used + * - No other loads/stores have an affect on the pending switch bit + * - The switch bus from POW can clear the pending switch bit + * + * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle + * ADDWQ command that only contains the pointer). SW must never use + * did<2:0> == 2. + */ +typedef union { + /** + * Unsigned 64 bit integer representation of store address + */ + u64 u64; + + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* Memory region. Should be CVMX_IO_SEG in most cases */ + u64 mem_reg:2; + u64 reserved_49_61:13; /* Must be zero */ + u64 is_io:1; /* Must be one */ + /* Device ID of POW. Note that different sub-dids are used. */ + u64 did:8; + u64 reserved_36_39:4; /* Must be zero */ + /* Address field. addr<2:0> must be zero */ + u64 addr:36; +#else + u64 addr:36; + u64 reserved_36_39:4; + u64 did:8; + u64 is_io:1; + u64 reserved_49_61:13; + u64 mem_reg:2; +#endif + } stag; +} cvmx_pow_tag_store_addr_t; + +/** + * decode of the store data when an IOBDMA SENDSINGLE is sent to POW + */ +typedef union { + u64 u64; + + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * the (64-bit word) location in scratchpad to write + * to (if len != 0) + */ + u64 scraddr:8; + /* the number of words in the response (0 => no response) */ + u64 len:8; + /* the ID of the device on the non-coherent bus */ + u64 did:8; + u64 unused:36; + /* if set, don't return load response until work is available */ + u64 wait:1; + u64 unused2:3; +#else + u64 unused2:3; + u64 wait:1; + u64 unused:36; + u64 did:8; + u64 len:8; + u64 scraddr:8; +#endif + } s; + +} cvmx_pow_iobdma_store_t; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Get the POW tag for this core. This returns the current + * tag type, tag, group, and POW entry index associated with + * this core. Index is only valid if the tag type isn't NULL_NULL. + * If a tag switch is pending this routine returns the tag before + * the tag switch, not after. + * + * Returns Current tag + */ +static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void) +{ + cvmx_pow_load_addr_t load_addr; + cvmx_pow_tag_load_resp_t load_resp; + cvmx_pow_tag_req_t result; + + load_addr.u64 = 0; + load_addr.sstatus.mem_region = CVMX_IO_SEG; + load_addr.sstatus.is_io = 1; + load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; + load_addr.sstatus.coreid = cvmx_get_core_num(); + load_addr.sstatus.get_cur = 1; + load_resp.u64 = cvmx_read_csr(load_addr.u64); + result.u64 = 0; + result.s.grp = load_resp.s_sstatus2.grp; + result.s.index = load_resp.s_sstatus2.index; + result.s.type = load_resp.s_sstatus2.tag_type; + result.s.tag = load_resp.s_sstatus2.tag; + return result; +} + +/** + * Get the POW WQE for this core. This returns the work queue + * entry currently associated with this core. + * + * Returns WQE pointer + */ +static inline struct cvmx_wqe *cvmx_pow_get_current_wqp(void) +{ + cvmx_pow_load_addr_t load_addr; + cvmx_pow_tag_load_resp_t load_resp; + + load_addr.u64 = 0; + load_addr.sstatus.mem_region = CVMX_IO_SEG; + load_addr.sstatus.is_io = 1; + load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; + load_addr.sstatus.coreid = cvmx_get_core_num(); + load_addr.sstatus.get_cur = 1; + load_addr.sstatus.get_wqp = 1; + load_resp.u64 = cvmx_read_csr(load_addr.u64); + return (struct cvmx_wqe *)cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp); +} + +#ifndef CVMX_MF_CHORD +#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) +#endif + +/** + * Print a warning if a tag switch is pending for this core + * + * @function: Function name checking for a pending tag switch + */ +static inline void __cvmx_pow_warn_if_pending_switch(const char *function) +{ + u64 switch_complete; + + CVMX_MF_CHORD(switch_complete); + if (!switch_complete) + pr_warn("%s called with tag switch in progress\n", function); +} + +/** + * Waits for a tag switch to complete by polling the completion bit. + * Note that switches to NULL complete immediately and do not need + * to be waited for. + */ +static inline void cvmx_pow_tag_sw_wait(void) +{ + const u64 MAX_CYCLES = 1ull << 31; + u64 switch_complete; + u64 start_cycle = cvmx_get_cycle(); + + while (1) { + CVMX_MF_CHORD(switch_complete); + if (unlikely(switch_complete)) + break; + if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) { + pr_warn("Tag switch is taking a long time, possible deadlock\n"); + start_cycle = -MAX_CYCLES - 1; + } + } +} + +/** + * Synchronous work request. Requests work from the POW. + * This function does NOT wait for previous tag switches to complete, + * so the caller must ensure that there is not a pending tag switch. + * + * @wait: When set, call stalls until work becomes available, or times out. + * If not set, returns immediately. + * + * Returns: the WQE pointer from POW. Returns NULL if no work + * was available. + */ +static inline struct cvmx_wqe *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t + wait) +{ + cvmx_pow_load_addr_t ptr; + cvmx_pow_tag_load_resp_t result; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + ptr.u64 = 0; + ptr.swork.mem_region = CVMX_IO_SEG; + ptr.swork.is_io = 1; + ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG; + ptr.swork.wait = wait; + + result.u64 = cvmx_read_csr(ptr.u64); + + if (result.s_work.no_work) + return NULL; + else + return (struct cvmx_wqe *)cvmx_phys_to_ptr(result.s_work.addr); +} + +/** + * Synchronous work request. Requests work from the POW. + * This function waits for any previous tag switch to complete before + * requesting the new work. + * + * @wait: When set, call stalls until work becomes available, or times out. + * If not set, returns immediately. + * + * Returns: the WQE pointer from POW. Returns NULL if no work + * was available. + */ +static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + return cvmx_pow_work_request_sync_nocheck(wait); +} + +/** + * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. + * This function waits for any previous tag switch to complete before + * requesting the null_rd. + * + * Returns: the POW state of type cvmx_pow_tag_type_t. + */ +static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) +{ + cvmx_pow_load_addr_t ptr; + cvmx_pow_tag_load_resp_t result; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + + ptr.u64 = 0; + ptr.snull_rd.mem_region = CVMX_IO_SEG; + ptr.snull_rd.is_io = 1; + ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD; + + result.u64 = cvmx_read_csr(ptr.u64); + + return (enum cvmx_pow_tag_type)result.s_null_rd.state; +} + +/** + * Asynchronous work request. Work is requested from the POW unit, + * and should later be checked with function + * cvmx_pow_work_response_async. This function does NOT wait for + * previous tag switches to complete, so the caller must ensure that + * there is not a pending tag switch. + * + * @scr_addr: Scratch memory address that response will be returned + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. + * + * @wait: 1 to cause response to wait for work to become available (or + * timeout), 0 to cause response to return immediately + */ +static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, + cvmx_pow_wait_t wait) +{ + cvmx_pow_iobdma_store_t data; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* scr_addr must be 8 byte aligned */ + data.s.scraddr = scr_addr >> 3; + data.s.len = 1; + data.s.did = CVMX_OCT_DID_TAG_SWTAG; + data.s.wait = wait; + cvmx_send_single(data.u64); +} + +/** + * Asynchronous work request. Work is requested from the POW unit, + * and should later be checked with function + * cvmx_pow_work_response_async. This function waits for any previous + * tag switch to complete before requesting the new work. + * + * @scr_addr: Scratch memory address that response will be returned + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. + * + * @wait: 1 to cause response to wait for work to become available (or + * timeout), 0 to cause response to return immediately + */ +static inline void cvmx_pow_work_request_async(int scr_addr, + cvmx_pow_wait_t wait) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_work_request_async_nocheck(scr_addr, wait); +} + +/** + * Gets result of asynchronous work request. Performs a IOBDMA sync + * to wait for the response. + * + * @scr_addr: Scratch memory address to get result from Byte address, + * must be 8 byte aligned. + * + * Returns: the WQE from the scratch register, or NULL if no + * work was available. + */ +static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr) +{ + cvmx_pow_tag_load_resp_t result; + + CVMX_SYNCIOBDMA; + result.u64 = cvmx_scratch_read64(scr_addr); + + if (result.s_work.no_work) + return NULL; + else + return (struct cvmx_wqe *)cvmx_phys_to_ptr(result.s_work.addr); +} + +/** + * Checks if a work queue entry pointer returned by a work + * request is valid. It may be invalid due to no work + * being available or due to a timeout. + * + * @wqe_ptr: pointer to a work queue entry returned by the POW + * + * Returns 0 if pointer is valid + * 1 if invalid (no work was returned) + */ +static inline u64 cvmx_pow_work_invalid(struct cvmx_wqe *wqe_ptr) +{ + return !wqe_ptr; +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * NOTE: This should not be used when switching from a NULL tag. Use + * cvmx_pow_tag_sw_full() instead. + * + * This function does no checks, so the caller must ensure that any + * previous tag switch has completed. + * + * @tag: new tag value + * @tag_type: new tag type (ordered or atomic) + */ +static inline void cvmx_pow_tag_sw_nocheck(u32 tag, + enum cvmx_pow_tag_type tag_type) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warn("%s called with NULL_NULL tag\n", __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called with NULL tag\n", __func__); + if ((current_tag.s.type == tag_type) && + (current_tag.s.tag == tag)) + pr_warn("%s called to perform a tag switch to the same tag\n", + __func__); + if (tag_type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", + __func__); + } + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; + + /* once this store arrives at POW, it will attempt the switch + software must wait for the switch to complete separately */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * NOTE: This should not be used when switching from a NULL tag. Use + * cvmx_pow_tag_sw_full() instead. + * + * This function waits for any previous tag switch to complete, and also + * displays an error on tag switches to NULL. + * + * @tag: new tag value + * @tag_type: new tag type (ordered or atomic) + */ +static inline void cvmx_pow_tag_sw(u32 tag, + enum cvmx_pow_tag_type tag_type) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_nocheck(tag, tag_type); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * This function must be used for tag switches from NULL. + * + * This function does no checks, so the caller must ensure that any + * previous tag switch has completed. + * + * @wqp: pointer to work queue entry to submit. This entry is + * updated to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @group: group value for the work queue entry. + */ +static inline void cvmx_pow_tag_sw_full_nocheck(struct cvmx_wqe *wqp, u32 tag, + enum cvmx_pow_tag_type tag_type, + u64 group) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warn("%s called with NULL_NULL tag\n", __func__); + if ((current_tag.s.type == tag_type) && + (current_tag.s.tag == tag)) + pr_warn("%s called to perform a tag switch to the same tag\n", + __func__); + if (tag_type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", + __func__); + if (wqp != cvmx_phys_to_ptr(0x80)) + if (wqp != cvmx_pow_get_current_wqp()) + pr_warn("%s passed WQE(%p) doesn't match the address in the POW(%p)\n", + __func__, wqp, + cvmx_pow_get_current_wqp()); + } + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + tag_req.s.grp = group; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; + ptr.sio.offset = CAST64(wqp); + + /* + * once this store arrives at POW, it will attempt the switch + * software must wait for the switch to complete separately. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * This function must be used for tag switches from NULL. + * + * This function waits for any pending tag switches to complete + * before requesting the tag switch. + * + * @wqp: pointer to work queue entry to submit. This entry is updated + * to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @group: group value for the work queue entry. + */ +static inline void cvmx_pow_tag_sw_full(struct cvmx_wqe *wqp, u32 tag, + enum cvmx_pow_tag_type tag_type, + u64 group) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group); +} + +/** + * Switch to a NULL tag, which ends any ordering or + * synchronization provided by the POW for the current + * work queue entry. This operation completes immediately, + * so completion should not be waited for. + * This function does NOT wait for previous tag switches to complete, + * so the caller must ensure that any previous tag switches have completed. + */ +static inline void cvmx_pow_tag_sw_null_nocheck(void) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warn("%s called with NULL_NULL tag\n", __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called when we already have a NULL tag\n", + __func__); + } + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; + tag_req.s.type = CVMX_POW_TAG_TYPE_NULL; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; + + cvmx_write_io(ptr.u64, tag_req.u64); + + /* switch to NULL completes immediately */ +} + +/** + * Switch to a NULL tag, which ends any ordering or + * synchronization provided by the POW for the current + * work queue entry. This operation completes immediately, + * so completion should not be waited for. + * This function waits for any pending tag switches to complete + * before requesting the switch to NULL. + */ +static inline void cvmx_pow_tag_sw_null(void) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_null_nocheck(); + + /* switch to NULL completes immediately */ +} + +/** + * Submits work to an input queue. This function updates the work + * queue entry in DRAM to match the arguments given. Note that the + * tag provided is for the work queue entry submitted, and is + * unrelated to the tag that the core currently holds. + * + * @wqp: pointer to work queue entry to submit. This entry is + * updated to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @qos: Input queue to add to. + * @grp: group value for the work queue entry. + */ +static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, u32 tag, + enum cvmx_pow_tag_type tag_type, + u64 qos, u64 grp) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + wqp->word1.tag = tag; + wqp->word1.tag_type = tag_type; + + cvmx_wqe_set_qos(wqp, qos); + cvmx_wqe_set_grp(wqp, grp); + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ; + tag_req.s.type = tag_type; + tag_req.s.tag = tag; + tag_req.s.qos = qos; + tag_req.s.grp = grp; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; + ptr.sio.offset = cvmx_ptr_to_phys(wqp); + + /* + * SYNC write to memory before the work submit. This is + * necessary as POW may read values from DRAM at this time. + */ + CVMX_SYNCWS; + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * This function sets the group mask for a core. The group mask + * indicates which groups each core will accept work from. There are + * 16 groups. + * + * @core_num: core to apply mask to + * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, + * representing groups 0-15. + * Each 1 bit in the mask enables the core to accept work from + * the corresponding group. + */ +static inline void cvmx_pow_set_group_mask(u64 core_num, u64 mask) +{ + union cvmx_pow_pp_grp_mskx grp_msk; + + grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); + grp_msk.s.grp_msk = mask; + cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); +} + +/** + * This function sets POW static priorities for a core. Each input queue has + * an associated priority value. + * + * @core_num: core to apply priorities to + * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). + * Highest priority is 0 and lowest is 7. A priority value + * of 0xF instructs POW to skip the Input Queue when + * scheduling to this specific core. + * NOTE: priorities should not have gaps in values, meaning + * {0,1,1,1,1,1,1,1} is a valid configuration while + * {0,2,2,2,2,2,2,2} is not. + */ +static inline void cvmx_pow_set_priority(u64 core_num, + const u8 priority[]) +{ + /* POW priorities are supported on CN5xxx and later */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pow_pp_grp_mskx grp_msk; + + grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); + grp_msk.s.qos0_pri = priority[0]; + grp_msk.s.qos1_pri = priority[1]; + grp_msk.s.qos2_pri = priority[2]; + grp_msk.s.qos3_pri = priority[3]; + grp_msk.s.qos4_pri = priority[4]; + grp_msk.s.qos5_pri = priority[5]; + grp_msk.s.qos6_pri = priority[6]; + grp_msk.s.qos7_pri = priority[7]; + + /* Detect gaps between priorities and flag error */ + { + int i; + u32 prio_mask = 0; + + for (i = 0; i < 8; i++) + if (priority[i] != 0xF) + prio_mask |= 1 << priority[i]; + + if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) { + pr_err("POW static priorities should be contiguous (0x%llx)\n", + (unsigned long long)prio_mask); + return; + } + } + + cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); + } +} + +/** + * Performs a tag switch and then an immediate deschedule. This completes + * immediately, so completion must not be waited for. This function does NOT + * update the wqe in DRAM to match arguments. + * + * This function does NOT wait for any prior tag switches to complete, so the + * calling code must do this. + * + * Note the following CAVEAT of the Octeon HW behavior when + * re-scheduling DE-SCHEDULEd items whose (next) state is + * ORDERED: + * - If there are no switches pending at the time that the + * HW executes the de-schedule, the HW will only re-schedule + * the head of the FIFO associated with the given tag. This + * means that in many respects, the HW treats this ORDERED + * tag as an ATOMIC tag. Note that in the SWTAG_DESCH + * case (to an ORDERED tag), the HW will do the switch + * before the deschedule whenever it is possible to do + * the switch immediately, so it may often look like + * this case. + * - If there is a pending switch to ORDERED at the time + * the HW executes the de-schedule, the HW will perform + * the switch at the time it re-schedules, and will be + * able to reschedule any/all of the entries with the + * same tag. + * Due to this behavior, the RECOMMENDATION to software is + * that they have a (next) state of ATOMIC when they + * DE-SCHEDULE. If an ORDERED tag is what was really desired, + * SW can choose to immediately switch to an ORDERED tag + * after the work (that has an ATOMIC tag) is re-scheduled. + * Note that since there are never any tag switches pending + * when the HW re-schedules, this switch can be IMMEDIATE upon + * the reception of the pointer during the re-schedule. + * + * @tag: New tag value + * @tag_type: New tag type + * @group: New group value + * @no_sched: Control whether this work queue entry will be rescheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. + */ +static inline void cvmx_pow_tag_sw_desched_nocheck( + u32 tag, + enum cvmx_pow_tag_type tag_type, + u64 group, + u64 no_sched) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warn("%s called with NULL_NULL tag\n", __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called with NULL tag. Deschedule not allowed from NULL state\n", + __func__); + if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) && + (tag_type != CVMX_POW_TAG_TYPE_ATOMIC)) + pr_warn("%s called where neither the before or after tag is ATOMIC\n", + __func__); + } + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + tag_req.s.grp = group; + tag_req.s.no_sched = no_sched; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; + /* + * since TAG3 is used, this store will clear the local pending + * switch bit. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Performs a tag switch and then an immediate deschedule. This completes + * immediately, so completion must not be waited for. This function does NOT + * update the wqe in DRAM to match arguments. + * + * This function waits for any prior tag switches to complete, so the + * calling code may call this function with a pending tag switch. + * + * Note the following CAVEAT of the Octeon HW behavior when + * re-scheduling DE-SCHEDULEd items whose (next) state is + * ORDERED: + * - If there are no switches pending at the time that the + * HW executes the de-schedule, the HW will only re-schedule + * the head of the FIFO associated with the given tag. This + * means that in many respects, the HW treats this ORDERED + * tag as an ATOMIC tag. Note that in the SWTAG_DESCH + * case (to an ORDERED tag), the HW will do the switch + * before the deschedule whenever it is possible to do + * the switch immediately, so it may often look like + * this case. + * - If there is a pending switch to ORDERED at the time + * the HW executes the de-schedule, the HW will perform + * the switch at the time it re-schedules, and will be + * able to reschedule any/all of the entries with the + * same tag. + * Due to this behavior, the RECOMMENDATION to software is + * that they have a (next) state of ATOMIC when they + * DE-SCHEDULE. If an ORDERED tag is what was really desired, + * SW can choose to immediately switch to an ORDERED tag + * after the work (that has an ATOMIC tag) is re-scheduled. + * Note that since there are never any tag switches pending + * when the HW re-schedules, this switch can be IMMEDIATE upon + * the reception of the pointer during the re-schedule. + * + * @tag: New tag value + * @tag_type: New tag type + * @group: New group value + * @no_sched: Control whether this work queue entry will be rescheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. + */ +static inline void cvmx_pow_tag_sw_desched(u32 tag, + enum cvmx_pow_tag_type tag_type, + u64 group, u64 no_sched) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Need to make sure any writes to the work queue entry are complete */ + CVMX_SYNCWS; + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched); +} + +/** + * Deschedules the current work queue entry. + * + * @no_sched: no schedule flag value to be set on the work queue + * entry. If this is set the entry will not be + * rescheduled. + */ +static inline void cvmx_pow_desched(u64 no_sched) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warn("%s called with NULL_NULL tag\n", __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warn("%s called with NULL tag. Deschedule not expected from NULL state\n", + __func__); + } + + /* Need to make sure any writes to the work queue entry are complete */ + CVMX_SYNCWS; + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_DESCH; + tag_req.s.no_sched = no_sched; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; + /* + * since TAG3 is used, this store will clear the local pending + * switch bit. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/**************************************************** +* Define usage of bits within the 32 bit tag values. +*****************************************************/ + +/* + * Number of bits of the tag used by software. The SW bits are always + * a contiguous block of the high starting at bit 31. The hardware + * bits are always the low bits. By default, the top 8 bits of the + * tag are reserved for software, and the low 24 are set by the IPD + * unit. + */ +#define CVMX_TAG_SW_BITS (8) +#define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS) + +/* Below is the list of values for the top 8 bits of the tag. */ +/* + * Tag values with top byte of this value are reserved for internal + * executive uses. + */ +#define CVMX_TAG_SW_BITS_INTERNAL 0x1 +/* The executive divides the remaining 24 bits as follows: + * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup + * + * - the lower 16 bits (bits 15 - 0 of the tag) define are the value + * with the subgroup + * + * Note that this section describes the format of tags generated by + * software - refer to the hardware documentation for a description of + * the tags values generated by the packet input hardware. Subgroups + * are defined here. + */ +/* Mask for the value portion of the tag */ +#define CVMX_TAG_SUBGROUP_MASK 0xFFFF +#define CVMX_TAG_SUBGROUP_SHIFT 16 +#define CVMX_TAG_SUBGROUP_PKO 0x1 + +/* End of executive tag subgroup definitions */ + +/* + * The remaining values software bit values 0x2 - 0xff are available + * for application use. + */ + +/** + * This function creates a 32 bit tag value from the two values provided. + * + * @sw_bits: The upper bits (number depends on configuration) are set + * to this value. The remainder of bits are set by the + * hw_bits parameter. + * + * @hw_bits: The lower bits (number depends on configuration) are set + * to this value. The remainder of bits are set by the + * sw_bits parameter. + * + * Returns 32 bit value of the combined hw and sw bits. + */ +static inline u32 cvmx_pow_tag_compose(u64 sw_bits, u64 hw_bits) +{ + return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) << + CVMX_TAG_SW_SHIFT) | + (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS)); +} + +/** + * Extracts the bits allocated for software use from the tag + * + * @tag: 32 bit tag value + * + * Returns N bit software tag value, where N is configurable with the + * CVMX_TAG_SW_BITS define + */ +static inline u32 cvmx_pow_tag_get_sw_bits(u64 tag) +{ + return (tag >> (32 - CVMX_TAG_SW_BITS)) & + cvmx_build_mask(CVMX_TAG_SW_BITS); +} + +/** + * + * Extracts the bits allocated for hardware use from the tag + * + * @tag: 32 bit tag value + * + * Returns (32 - N) bit software tag value, where N is configurable + * with the CVMX_TAG_SW_BITS define + */ +static inline u32 cvmx_pow_tag_get_hw_bits(u64 tag) +{ + return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS); +} + +/** + * Store the current POW internal state into the supplied + * buffer. It is recommended that you pass a buffer of at least + * 128KB. The format of the capture may change based on SDK + * version and Octeon chip. + * + * @buffer: Buffer to store capture into + * @buffer_size: + * The size of the supplied buffer + * + * Returns Zero on success, negative on failure + */ +int cvmx_pow_capture(void *buffer, int buffer_size); + +/** + * Dump a POW capture to the console in a human readable format. + * + * @buffer: POW capture from cvmx_pow_capture() + * @buffer_size: + * Size of the buffer + */ +void cvmx_pow_display(void *buffer, int buffer_size); + +/** + * Return the number of POW entries supported by this chip + * + * Returns Number of POW entries + */ +int cvmx_pow_get_num_entries(void); + +#endif /* __CVMX_POW_H__ */ diff --git a/drivers/staging/octeon/cvmx-rst-defs.h b/drivers/staging/octeon/cvmx-rst-defs.h new file mode 100644 index 000000000000..eb35a1b4b637 --- /dev/null +++ b/drivers/staging/octeon/cvmx-rst-defs.h @@ -0,0 +1,277 @@ +/***********************license start*************** + * Author: Cavium Inc. + * + * Contact: support@cavium.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2014 Cavium Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Inc. for more information + ***********************license end**************************************/ + +#ifndef __CVMX_RST_DEFS_H__ +#define __CVMX_RST_DEFS_H__ + +#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull)) +#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull)) +#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull)) +#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8) +#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull)) +#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull)) +#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull)) +#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull)) +#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull)) +#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull)) +#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8) +#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull)) + +union cvmx_rst_boot { + u64 u64; + struct cvmx_rst_boot_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 chipkill:1; + u64 jtcsrdis:1; + u64 ejtagdis:1; + u64 romen:1; + u64 ckill_ppdis:1; + u64 jt_tstmode:1; + u64 vrm_err:1; + u64 reserved_37_56:20; + u64 c_mul:7; + u64 pnr_mul:6; + u64 reserved_21_23:3; + u64 lboot_oci:3; + u64 lboot_ext:6; + u64 lboot:10; + u64 rboot:1; + u64 rboot_pin:1; +#else + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 lboot_ext:6; + u64 lboot_oci:3; + u64 reserved_21_23:3; + u64 pnr_mul:6; + u64 c_mul:7; + u64 reserved_37_56:20; + u64 vrm_err:1; + u64 jt_tstmode:1; + u64 ckill_ppdis:1; + u64 romen:1; + u64 ejtagdis:1; + u64 jtcsrdis:1; + u64 chipkill:1; +#endif + } s; +}; + +union cvmx_rst_cfg { + u64 u64; + struct cvmx_rst_cfg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bist_delay:58; + u64 reserved_3_5:3; + u64 cntl_clr_bist:1; + u64 warm_clr_bist:1; + u64 soft_clr_bist:1; +#else + u64 soft_clr_bist:1; + u64 warm_clr_bist:1; + u64 cntl_clr_bist:1; + u64 reserved_3_5:3; + u64 bist_delay:58; +#endif + } s; +}; + +union cvmx_rst_ckill { + u64 u64; + struct cvmx_rst_ckill_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_47_63:17; + u64 timer:47; +#else + u64 timer:47; + u64 reserved_47_63:17; +#endif + } s; +}; + +union cvmx_rst_ctlx { + u64 u64; + struct cvmx_rst_ctlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 prst_link:1; + u64 rst_done:1; + u64 rst_link:1; + u64 host_mode:1; + u64 reserved_4_5:2; + u64 rst_drv:1; + u64 rst_rcv:1; + u64 rst_chip:1; + u64 rst_val:1; +#else + u64 rst_val:1; + u64 rst_chip:1; + u64 rst_rcv:1; + u64 rst_drv:1; + u64 reserved_4_5:2; + u64 host_mode:1; + u64 rst_link:1; + u64 rst_done:1; + u64 prst_link:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_rst_delay { + u64 u64; + struct cvmx_rst_delay_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 warm_rst_dly:16; + u64 soft_rst_dly:16; +#else + u64 soft_rst_dly:16; + u64 warm_rst_dly:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_rst_eco { + u64 u64; + struct cvmx_rst_eco_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 eco_rw:32; +#else + u64 eco_rw:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_rst_int { + u64 u64; + struct cvmx_rst_int_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 perst:4; + u64 reserved_4_7:4; + u64 rst_link:4; +#else + u64 rst_link:4; + u64 reserved_4_7:4; + u64 perst:4; + u64 reserved_12_63:52; +#endif + } s; + struct cvmx_rst_int_cn70xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 perst:3; + u64 reserved_3_7:5; + u64 rst_link:3; +#else + u64 rst_link:3; + u64 reserved_3_7:5; + u64 perst:3; + u64 reserved_11_63:53; +#endif + } cn70xx; +}; + +union cvmx_rst_ocx { + u64 u64; + struct cvmx_rst_ocx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 rst_link:3; +#else + u64 rst_link:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_rst_power_dbg { + u64 u64; + struct cvmx_rst_power_dbg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 str:3; +#else + u64 str:3; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_rst_pp_power { + u64 u64; + struct cvmx_rst_pp_power_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 gate:48; +#else + u64 gate:48; + u64 reserved_48_63:16; +#endif + } s; + struct cvmx_rst_pp_power_cn70xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 gate:4; +#else + u64 gate:4; + u64 reserved_4_63:60; +#endif + } cn70xx; +}; + +union cvmx_rst_soft_prstx { + u64 u64; + struct cvmx_rst_soft_prstx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 soft_prst:1; +#else + u64 soft_prst:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_rst_soft_rst { + u64 u64; + struct cvmx_rst_soft_rst_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 soft_rst:1; +#else + u64 soft_rst:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-scratch.h b/drivers/staging/octeon/cvmx-scratch.h new file mode 100644 index 000000000000..8bb4e00e76b3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-scratch.h @@ -0,0 +1,138 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * This file provides support for the processor local scratch memory. + * Scratch memory is byte addressable - all addresses are byte addresses. + * + */ + +#ifndef __CVMX_SCRATCH_H__ +#define __CVMX_SCRATCH_H__ + +/* + * Note: This define must be a long, not a long long in order to + * compile without warnings for both 32bit and 64bit. + */ +#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ + +/** + * Reads an 8 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline u8 cvmx_scratch_read8(u64 address) +{ + return *CASTPTR(volatile u8, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 16 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline u16 cvmx_scratch_read16(u64 address) +{ + return *CASTPTR(volatile u16, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 32 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline u32 cvmx_scratch_read32(u64 address) +{ + return *CASTPTR(volatile u32, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 64 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline u64 cvmx_scratch_read64(u64 address) +{ + return *CASTPTR(volatile u64, CVMX_SCRATCH_BASE + address); +} + +/** + * Writes an 8 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write8(u64 address, u64 value) +{ + *CASTPTR(volatile u8, CVMX_SCRATCH_BASE + address) = + (u8)value; +} + +/** + * Writes a 32 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write16(u64 address, u64 value) +{ + *CASTPTR(volatile u16, CVMX_SCRATCH_BASE + address) = + (u16)value; +} + +/** + * Writes a 16 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write32(u64 address, u64 value) +{ + *CASTPTR(volatile u32, CVMX_SCRATCH_BASE + address) = + (u32)value; +} + +/** + * Writes a 64 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write64(u64 address, u64 value) +{ + *CASTPTR(volatile u64, CVMX_SCRATCH_BASE + address) = value; +} + +#endif /* __CVMX_SCRATCH_H__ */ diff --git a/drivers/staging/octeon/cvmx-sli-defs.h b/drivers/staging/octeon/cvmx-sli-defs.h new file mode 100644 index 000000000000..4a7377966d95 --- /dev/null +++ b/drivers/staging/octeon/cvmx-sli-defs.h @@ -0,0 +1,127 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SLI_DEFS_H__ +#define __CVMX_SLI_DEFS_H__ + +#include + +#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC() +static inline u64 CVMX_SLI_PCIE_MSI_RCV_FUNC(void) +{ + switch (cvmx_get_octeon_family()) { + case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: + case OCTEON_CN61XX & OCTEON_FAMILY_MASK: + case OCTEON_CN63XX & OCTEON_FAMILY_MASK: + case OCTEON_CN66XX & OCTEON_FAMILY_MASK: + case OCTEON_CN68XX & OCTEON_FAMILY_MASK: + case OCTEON_CN70XX & OCTEON_FAMILY_MASK: + return 0x0000000000003CB0ull; + case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: + case OCTEON_CN73XX & OCTEON_FAMILY_MASK: + case OCTEON_CN78XX & OCTEON_FAMILY_MASK: + if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) + return 0x0000000000003CB0ull; + fallthrough; + default: + return 0x0000000000023CB0ull; + } +} + +union cvmx_sli_ctl_portx { + u64 u64; + struct cvmx_sli_ctl_portx_s { + __BITFIELD_FIELD(u64 reserved_22_63:42, + __BITFIELD_FIELD(u64 intd:1, + __BITFIELD_FIELD(u64 intc:1, + __BITFIELD_FIELD(u64 intb:1, + __BITFIELD_FIELD(u64 inta:1, + __BITFIELD_FIELD(u64 dis_port:1, + __BITFIELD_FIELD(u64 waitl_com:1, + __BITFIELD_FIELD(u64 intd_map:2, + __BITFIELD_FIELD(u64 intc_map:2, + __BITFIELD_FIELD(u64 intb_map:2, + __BITFIELD_FIELD(u64 inta_map:2, + __BITFIELD_FIELD(u64 ctlp_ro:1, + __BITFIELD_FIELD(u64 reserved_6_6:1, + __BITFIELD_FIELD(u64 ptlp_ro:1, + __BITFIELD_FIELD(u64 reserved_1_4:4, + __BITFIELD_FIELD(u64 wait_com:1, + ;)))))))))))))))) + } s; +}; + +union cvmx_sli_mem_access_ctl { + u64 u64; + struct cvmx_sli_mem_access_ctl_s { + __BITFIELD_FIELD(u64 reserved_14_63:50, + __BITFIELD_FIELD(u64 max_word:4, + __BITFIELD_FIELD(u64 timer:10, + ;))) + } s; +}; + +union cvmx_sli_s2m_portx_ctl { + u64 u64; + struct cvmx_sli_s2m_portx_ctl_s { + __BITFIELD_FIELD(u64 reserved_5_63:59, + __BITFIELD_FIELD(u64 wind_d:1, + __BITFIELD_FIELD(u64 bar0_d:1, + __BITFIELD_FIELD(u64 mrrs:3, + ;)))) + } s; +}; + +union cvmx_sli_mem_access_subidx { + u64 u64; + struct cvmx_sli_mem_access_subidx_s { + __BITFIELD_FIELD(u64 reserved_43_63:21, + __BITFIELD_FIELD(u64 zero:1, + __BITFIELD_FIELD(u64 port:3, + __BITFIELD_FIELD(u64 nmerge:1, + __BITFIELD_FIELD(u64 esr:2, + __BITFIELD_FIELD(u64 esw:2, + __BITFIELD_FIELD(u64 wtype:2, + __BITFIELD_FIELD(u64 rtype:2, + __BITFIELD_FIELD(u64 ba:30, + ;))))))))) + } s; + struct cvmx_sli_mem_access_subidx_cn68xx { + __BITFIELD_FIELD(u64 reserved_43_63:21, + __BITFIELD_FIELD(u64 zero:1, + __BITFIELD_FIELD(u64 port:3, + __BITFIELD_FIELD(u64 nmerge:1, + __BITFIELD_FIELD(u64 esr:2, + __BITFIELD_FIELD(u64 esw:2, + __BITFIELD_FIELD(u64 wtype:2, + __BITFIELD_FIELD(u64 rtype:2, + __BITFIELD_FIELD(u64 ba:28, + __BITFIELD_FIELD(u64 reserved_0_1:2, + ;)))))))))) + } cn68xx; +}; + +#endif diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/drivers/staging/octeon/cvmx-spi.c similarity index 70% rename from arch/mips/cavium-octeon/executive/cvmx-spi.c rename to drivers/staging/octeon/cvmx-spi.c index eb9333e84a6b..7b4890422a82 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-spi.c +++ b/drivers/staging/octeon/cvmx-spi.c @@ -1,44 +1,43 @@ /***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ /* - * - * Support library for the SPI - */ -#include + * + * Support library for the SPI + */ +#include "octeon.h" -#include +#include "cvmx-config.h" -#include -#include +#include "cvmx-pko.h" +#include "cvmx-spi.h" -#include -#include -#include +#include "cvmx-spxx-defs.h" +#include "cvmx-stxx-defs.h" +#include "cvmx-srxx-defs.h" #define INVOKE_CB(function_p, args...) \ do { \ @@ -50,13 +49,13 @@ } while (0) #if CVMX_ENABLE_DEBUG_PRINTS -static const char *modes[] = - { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" }; +static const char *modes[] = { + "XXXXXXX", "XXXXXXXXXXX", "XXXXXXXXXXX", "XXXXXX" }; #endif /* Default callbacks, can be overridden - * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks - */ + * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks + */ static cvmx_spi_callbacks_t cvmx_spi_callbacks = { .reset_cb = cvmx_spi_reset_cb, .calendar_setup_cb = cvmx_spi_calendar_setup_cb, @@ -67,41 +66,41 @@ static cvmx_spi_callbacks_t cvmx_spi_callbacks = { }; /* - * Get current SPI4 initialization callbacks - * - * @callbacks: Pointer to the callbacks structure.to fill - * - * Returns Pointer to cvmx_spi_callbacks_t structure. - */ + * Get current SPI4 initialization callbacks + * + * @callbacks: Pointer to the callbacks structure.to fill + * + * Returns Pointer to cvmx_spi_callbacks_t structure. + */ void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks) { memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks)); } /* - * Set new SPI4 initialization callbacks - * - * @new_callbacks: Pointer to an updated callbacks structure. - */ + * Set new SPI4 initialization callbacks + * + * @new_callbacks: Pointer to an updated callbacks structure. + */ void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks) { memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks)); } /* - * Initialize and start the SPI interface. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * @num_ports: Number of SPI ports to configure - * - * Returns Zero on success, negative of failure. - */ + * Initialize and start the SPI interface. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * @num_ports: Number of SPI ports to configure + * + * Returns Zero on success, negative of failure. + */ int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, int num_ports) { @@ -134,19 +133,19 @@ int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, } /* - * This routine restarts the SPI interface after it has lost synchronization - * with its correspondent system. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * - * Returns Zero on success, negative of failure. - */ + * This routine restarts the SPI interface after it has lost synchronization + * with its correspondent system. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, negative of failure. + */ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) { int res = -1; @@ -180,18 +179,18 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface); /* - * Callback to perform SPI4 reset - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to perform SPI4 reset + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) { union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl; @@ -201,7 +200,7 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) union cvmx_stxx_int_msk stxx_int_msk; union cvmx_spxx_trn4_ctl spxx_trn4_ctl; int index; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + u64 MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; /* Disable SPI error events while we run BIST */ spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); @@ -295,24 +294,25 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) } /* - * Callback to setup calendar and miscellaneous settings before clock detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @num_ports: Number of ports to configure on SPI - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to setup calendar and miscellaneous settings before clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @num_ports: Number of ports to configure on SPI + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, int num_ports) { int port; int index; + if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { union cvmx_srxx_com_ctl srxx_com_ctl; union cvmx_srxx_spi4_stat srxx_spi4_stat; @@ -329,6 +329,7 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, index = 0; while (port < num_ports) { union cvmx_srxx_spi4_calx srxx_spi4_calx; + srxx_spi4_calx.u64 = 0; srxx_spi4_calx.s.prt0 = port++; srxx_spi4_calx.s.prt1 = port++; @@ -392,6 +393,7 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, index = 0; while (port < num_ports) { union cvmx_stxx_spi4_calx stxx_spi4_calx; + stxx_spi4_calx.u64 = 0; stxx_spi4_calx.s.prt0 = port++; stxx_spi4_calx.s.prt1 = port++; @@ -414,25 +416,25 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, } /* - * Callback to perform clock detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to perform clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) { int clock_transitions; union cvmx_spxx_clk_stat stat; - uint64_t timeout_time; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + u64 timeout_time; + u64 MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; /* * Regardless of operating mode, both Tx and Rx clocks must be @@ -492,29 +494,30 @@ int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) } /* - * Callback to perform link training - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for link to be trained (in seconds) - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to perform link training + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for link to be trained (in seconds) + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) { union cvmx_spxx_trn4_ctl spxx_trn4_ctl; union cvmx_spxx_clk_stat stat; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; - uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; + u64 MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + u64 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; int rx_training_needed; /* SRX0 & STX0 Inf0 Links are configured - begin training */ union cvmx_spxx_clk_ctl spxx_clk_ctl; + spxx_clk_ctl.u64 = 0; spxx_clk_ctl.s.seetrn = 0; spxx_clk_ctl.s.clkdly = 0x10; @@ -561,25 +564,27 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) } /* - * Callback to perform calendar data synchronization - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for calendar data in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to perform calendar data synchronization + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for calendar data in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) { - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + u64 MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { /* SRX0 interface should be good, send calendar data */ union cvmx_srxx_com_ctl srxx_com_ctl; + cvmx_dprintf ("SPI%d: Rx is synchronized, start sending calendar data\n", interface); @@ -594,8 +599,9 @@ int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) /* The corespondant board should be sending calendar data */ /* Enable the STX0 STAT receiver. */ union cvmx_spxx_clk_stat stat; - uint64_t timeout_time; + u64 timeout_time; union cvmx_stxx_com_ctl stxx_com_ctl; + stxx_com_ctl.u64 = 0; stxx_com_ctl.s.st_en = 1; cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); @@ -618,18 +624,18 @@ int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) } /* - * Callback to handle interface up - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ + * Callback to handle interface up + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) { union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min; @@ -638,6 +644,7 @@ int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { union cvmx_srxx_com_ctl srxx_com_ctl; + srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); srxx_com_ctl.s.inf_en = 1; cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); @@ -646,6 +653,7 @@ int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { union cvmx_stxx_com_ctl stxx_com_ctl; + stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); stxx_com_ctl.s.inf_en = 1; cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); diff --git a/drivers/staging/octeon/cvmx-spi.h b/drivers/staging/octeon/cvmx-spi.h new file mode 100644 index 000000000000..8d6aafc1d42a --- /dev/null +++ b/drivers/staging/octeon/cvmx-spi.h @@ -0,0 +1,270 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * This file contains defines for the SPI interface + */ +#ifndef __CVMX_SPI_H__ +#define __CVMX_SPI_H__ + +#include "cvmx-gmxx-defs.h" + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +typedef enum { + CVMX_SPI_MODE_UNKNOWN = 0, + CVMX_SPI_MODE_TX_HALFPLEX = 1, + CVMX_SPI_MODE_RX_HALFPLEX = 2, + CVMX_SPI_MODE_DUPLEX = 3 +} cvmx_spi_mode_t; + +/** Callbacks structure to customize SPI4 initialization sequence */ +typedef struct { + /** Called to reset SPI4 DLL */ + int (*reset_cb)(int interface, cvmx_spi_mode_t mode); + + /** Called to setup calendar */ + int (*calendar_setup_cb)(int interface, cvmx_spi_mode_t mode, + int num_ports); + + /** Called for Tx and Rx clock detection */ + int (*clock_detect_cb)(int interface, cvmx_spi_mode_t mode, + int timeout); + + /** Called to perform link training */ + int (*training_cb)(int interface, cvmx_spi_mode_t mode, int timeout); + + /** Called for calendar data synchronization */ + int (*calendar_sync_cb)(int interface, cvmx_spi_mode_t mode, + int timeout); + + /** Called when interface is up */ + int (*interface_up_cb)(int interface, cvmx_spi_mode_t mode); + +} cvmx_spi_callbacks_t; + +/** + * Return true if the supplied interface is configured for SPI + * + * @interface: Interface to check + * Returns True if interface is SPI + */ +static inline int cvmx_spi_is_spi_interface(int interface) +{ + u64 gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + return (gmxState & 0x2) && (gmxState & 0x1); +} + +/** + * Initialize and start the SPI interface. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * @num_ports: Number of SPI ports to configure + * + * Returns Zero on success, negative of failure. + */ +int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, + int timeout, int num_ports); + +/** + * This routine restarts the SPI interface after it has lost synchronization + * with its corespondant system. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * Returns Zero on success, negative of failure. + */ +int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Return non-zero if the SPI interface has a SPI4000 attached + * + * @interface: SPI interface the SPI4000 is connected to + * + * Returns + */ +static inline int cvmx_spi4000_is_present(int interface) +{ + return 0; +} + +/** + * Initialize the SPI4000 for use + * + * @interface: SPI interface the SPI4000 is connected to + */ +static inline int cvmx_spi4000_initialize(int interface) +{ + return 0; +} + +/** + * Poll all the SPI4000 port and check its speed + * + * @interface: Interface the SPI4000 is on + * @port: Port to poll (0-9) + * Returns Status of the port. 0=down. All other values the port is up. + */ +static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( + int interface, + int port) +{ + union cvmx_gmxx_rxx_rx_inbnd r; + + r.u64 = 0; + return r; +} + +/** + * Get current SPI4 initialization callbacks + * + * @callbacks: Pointer to the callbacks structure.to fill + * + * Returns Pointer to cvmx_spi_callbacks_t structure. + */ +void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks); + +/** + * Set new SPI4 initialization callbacks + * + * @new_callbacks: Pointer to an updated callbacks structure. + */ +void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); + +/** + * Callback to perform SPI4 reset + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); + +/** + * Callback to setup calendar and miscellaneous settings before clock + * detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @num_ports: Number of ports to configure on SPI + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, + int num_ports); + +/** + * Callback to perform clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to perform link training + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for link to be trained (in seconds) + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to perform calendar data synchronization + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for calendar data in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to handle interface up + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode); + +#endif /* __CVMX_SPI_H__ */ diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/drivers/staging/octeon/cvmx-spxx-defs.h new file mode 100644 index 000000000000..fe1f3e492b35 --- /dev/null +++ b/drivers/staging/octeon/cvmx-spxx-defs.h @@ -0,0 +1,445 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SPXX_DEFS_H__ +#define __CVMX_SPXX_DEFS_H__ + +#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull) + +void __cvmx_interrupt_spxx_int_msk_enable(int index); + +union cvmx_spxx_bckprs_cnt { + u64 u64; + struct cvmx_spxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_spxx_bist_stat { + u64 u64; + struct cvmx_spxx_bist_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 stat2:1; + u64 stat1:1; + u64 stat0:1; +#else + u64 stat0:1; + u64 stat1:1; + u64 stat2:1; + u64 reserved_3_63:61; +#endif + } s; +}; + +union cvmx_spxx_clk_ctl { + u64 u64; + struct cvmx_spxx_clk_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 seetrn:1; + u64 reserved_12_15:4; + u64 clkdly:5; + u64 runbist:1; + u64 statdrv:1; + u64 statrcv:1; + u64 sndtrn:1; + u64 drptrn:1; + u64 rcvtrn:1; + u64 srxdlck:1; +#else + u64 srxdlck:1; + u64 rcvtrn:1; + u64 drptrn:1; + u64 sndtrn:1; + u64 statrcv:1; + u64 statdrv:1; + u64 runbist:1; + u64 clkdly:5; + u64 reserved_12_15:4; + u64 seetrn:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_spxx_clk_stat { + u64 u64; + struct cvmx_spxx_clk_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_11_63:53; + u64 stxcal:1; + u64 reserved_9_9:1; + u64 srxtrn:1; + u64 s4clk1:1; + u64 s4clk0:1; + u64 d4clk1:1; + u64 d4clk0:1; + u64 reserved_0_3:4; +#else + u64 reserved_0_3:4; + u64 d4clk0:1; + u64 d4clk1:1; + u64 s4clk0:1; + u64 s4clk1:1; + u64 srxtrn:1; + u64 reserved_9_9:1; + u64 stxcal:1; + u64 reserved_11_63:53; +#endif + } s; +}; + +union cvmx_spxx_dbg_deskew_ctl { + u64 u64; + struct cvmx_spxx_dbg_deskew_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_30_63:34; + u64 fallnop:1; + u64 fall8:1; + u64 reserved_26_27:2; + u64 sstep_go:1; + u64 sstep:1; + u64 reserved_22_23:2; + u64 clrdly:1; + u64 dec:1; + u64 inc:1; + u64 mux:1; + u64 offset:5; + u64 bitsel:5; + u64 offdly:6; + u64 dllfrc:1; + u64 dlldis:1; +#else + u64 dlldis:1; + u64 dllfrc:1; + u64 offdly:6; + u64 bitsel:5; + u64 offset:5; + u64 mux:1; + u64 inc:1; + u64 dec:1; + u64 clrdly:1; + u64 reserved_22_23:2; + u64 sstep:1; + u64 sstep_go:1; + u64 reserved_26_27:2; + u64 fall8:1; + u64 fallnop:1; + u64 reserved_30_63:34; +#endif + } s; +}; + +union cvmx_spxx_dbg_deskew_state { + u64 u64; + struct cvmx_spxx_dbg_deskew_state_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 testres:1; + u64 unxterm:1; + u64 muxsel:2; + u64 offset:5; +#else + u64 offset:5; + u64 muxsel:2; + u64 unxterm:1; + u64 testres:1; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_spxx_drv_ctl { + u64 u64; + struct cvmx_spxx_drv_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_0_63:64; +#else + u64 reserved_0_63:64; +#endif + } s; + struct cvmx_spxx_drv_ctl_cn38xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 stx4ncmp:4; + u64 stx4pcmp:4; + u64 srx4cmp:8; +#else + u64 srx4cmp:8; + u64 stx4pcmp:4; + u64 stx4ncmp:4; + u64 reserved_16_63:48; +#endif + } cn38xx; + struct cvmx_spxx_drv_ctl_cn58xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_24_63:40; + u64 stx4ncmp:4; + u64 stx4pcmp:4; + u64 reserved_10_15:6; + u64 srx4cmp:10; +#else + u64 srx4cmp:10; + u64 reserved_10_15:6; + u64 stx4pcmp:4; + u64 stx4ncmp:4; + u64 reserved_24_63:40; +#endif + } cn58xx; +}; + +union cvmx_spxx_err_ctl { + u64 u64; + struct cvmx_spxx_err_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 prtnxa:1; + u64 dipcls:1; + u64 dippay:1; + u64 reserved_4_5:2; + u64 errcnt:4; +#else + u64 errcnt:4; + u64 reserved_4_5:2; + u64 dippay:1; + u64 dipcls:1; + u64 prtnxa:1; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_spxx_int_dat { + u64 u64; + struct cvmx_spxx_int_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 mul:1; + u64 reserved_14_30:17; + u64 calbnk:2; + u64 rsvop:4; + u64 prt:8; +#else + u64 prt:8; + u64 rsvop:4; + u64 calbnk:2; + u64 reserved_14_30:17; + u64 mul:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_spxx_int_msk { + u64 u64; + struct cvmx_spxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 calerr:1; + u64 syncerr:1; + u64 diperr:1; + u64 tpaovr:1; + u64 rsverr:1; + u64 drwnng:1; + u64 clserr:1; + u64 spiovr:1; + u64 reserved_2_3:2; + u64 abnorm:1; + u64 prtnxa:1; +#else + u64 prtnxa:1; + u64 abnorm:1; + u64 reserved_2_3:2; + u64 spiovr:1; + u64 clserr:1; + u64 drwnng:1; + u64 rsverr:1; + u64 tpaovr:1; + u64 diperr:1; + u64 syncerr:1; + u64 calerr:1; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_spxx_int_reg { + u64 u64; + struct cvmx_spxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 spf:1; + u64 reserved_12_30:19; + u64 calerr:1; + u64 syncerr:1; + u64 diperr:1; + u64 tpaovr:1; + u64 rsverr:1; + u64 drwnng:1; + u64 clserr:1; + u64 spiovr:1; + u64 reserved_2_3:2; + u64 abnorm:1; + u64 prtnxa:1; +#else + u64 prtnxa:1; + u64 abnorm:1; + u64 reserved_2_3:2; + u64 spiovr:1; + u64 clserr:1; + u64 drwnng:1; + u64 rsverr:1; + u64 tpaovr:1; + u64 diperr:1; + u64 syncerr:1; + u64 calerr:1; + u64 reserved_12_30:19; + u64 spf:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_spxx_int_sync { + u64 u64; + struct cvmx_spxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_12_63:52; + u64 calerr:1; + u64 syncerr:1; + u64 diperr:1; + u64 tpaovr:1; + u64 rsverr:1; + u64 drwnng:1; + u64 clserr:1; + u64 spiovr:1; + u64 reserved_2_3:2; + u64 abnorm:1; + u64 prtnxa:1; +#else + u64 prtnxa:1; + u64 abnorm:1; + u64 reserved_2_3:2; + u64 spiovr:1; + u64 clserr:1; + u64 drwnng:1; + u64 rsverr:1; + u64 tpaovr:1; + u64 diperr:1; + u64 syncerr:1; + u64 calerr:1; + u64 reserved_12_63:52; +#endif + } s; +}; + +union cvmx_spxx_tpa_acc { + u64 u64; + struct cvmx_spxx_tpa_acc_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_spxx_tpa_max { + u64 u64; + struct cvmx_spxx_tpa_max_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 max:32; +#else + u64 max:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_spxx_tpa_sel { + u64 u64; + struct cvmx_spxx_tpa_sel_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 prtsel:4; +#else + u64 prtsel:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_spxx_trn4_ctl { + u64 u64; + struct cvmx_spxx_trn4_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_13_63:51; + u64 trntest:1; + u64 jitter:3; + u64 clr_boot:1; + u64 set_boot:1; + u64 maxdist:5; + u64 macro_en:1; + u64 mux_en:1; +#else + u64 mux_en:1; + u64 macro_en:1; + u64 maxdist:5; + u64 set_boot:1; + u64 clr_boot:1; + u64 jitter:3; + u64 trntest:1; + u64 reserved_13_63:51; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-sriox-defs.h b/drivers/staging/octeon/cvmx-sriox-defs.h new file mode 100644 index 000000000000..d8ea6ee0f93f --- /dev/null +++ b/drivers/staging/octeon/cvmx-sriox-defs.h @@ -0,0 +1,1613 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SRIOX_DEFS_H__ +#define __CVMX_SRIOX_DEFS_H__ + +#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) +#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) +#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) +#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) + +union cvmx_sriox_acc_ctrl { + u64 u64; + struct cvmx_sriox_acc_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_7_63:57; + u64 deny_adr2:1; + u64 deny_adr1:1; + u64 deny_adr0:1; + u64 reserved_3_3:1; + u64 deny_bar2:1; + u64 deny_bar1:1; + u64 deny_bar0:1; +#else + u64 deny_bar0:1; + u64 deny_bar1:1; + u64 deny_bar2:1; + u64 reserved_3_3:1; + u64 deny_adr0:1; + u64 deny_adr1:1; + u64 deny_adr2:1; + u64 reserved_7_63:57; +#endif + } s; + struct cvmx_sriox_acc_ctrl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_3_63:61; + u64 deny_bar2:1; + u64 deny_bar1:1; + u64 deny_bar0:1; +#else + u64 deny_bar0:1; + u64 deny_bar1:1; + u64 deny_bar2:1; + u64 reserved_3_63:61; +#endif + } cn63xx; +}; + +union cvmx_sriox_asmbly_id { + u64 u64; + struct cvmx_sriox_asmbly_id_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 assy_id:16; + u64 assy_ven:16; +#else + u64 assy_ven:16; + u64 assy_id:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_asmbly_info { + u64 u64; + struct cvmx_sriox_asmbly_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 assy_rev:16; + u64 reserved_0_15:16; +#else + u64 reserved_0_15:16; + u64 assy_rev:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_bell_resp_ctrl { + u64 u64; + struct cvmx_sriox_bell_resp_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 rp1_sid:1; + u64 rp0_sid:2; + u64 rp1_pid:1; + u64 rp0_pid:2; +#else + u64 rp0_pid:2; + u64 rp1_pid:1; + u64 rp0_sid:2; + u64 rp1_sid:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_sriox_bist_status { + u64 u64; + struct cvmx_sriox_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_45_63:19; + u64 lram:1; + u64 mram:2; + u64 cram:2; + u64 bell:2; + u64 otag:2; + u64 itag:1; + u64 ofree:1; + u64 rtn:2; + u64 obulk:4; + u64 optrs:4; + u64 oarb2:2; + u64 rxbuf2:2; + u64 oarb:2; + u64 ispf:1; + u64 ospf:1; + u64 txbuf:2; + u64 rxbuf:2; + u64 imsg:5; + u64 omsg:7; +#else + u64 omsg:7; + u64 imsg:5; + u64 rxbuf:2; + u64 txbuf:2; + u64 ospf:1; + u64 ispf:1; + u64 oarb:2; + u64 rxbuf2:2; + u64 oarb2:2; + u64 optrs:4; + u64 obulk:4; + u64 rtn:2; + u64 ofree:1; + u64 itag:1; + u64 otag:2; + u64 bell:2; + u64 cram:2; + u64 mram:2; + u64 lram:1; + u64 reserved_45_63:19; +#endif + } s; + struct cvmx_sriox_bist_status_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 mram:2; + u64 cram:2; + u64 bell:2; + u64 otag:2; + u64 itag:1; + u64 ofree:1; + u64 rtn:2; + u64 obulk:4; + u64 optrs:4; + u64 oarb2:2; + u64 rxbuf2:2; + u64 oarb:2; + u64 ispf:1; + u64 ospf:1; + u64 txbuf:2; + u64 rxbuf:2; + u64 imsg:5; + u64 omsg:7; +#else + u64 omsg:7; + u64 imsg:5; + u64 rxbuf:2; + u64 txbuf:2; + u64 ospf:1; + u64 ispf:1; + u64 oarb:2; + u64 rxbuf2:2; + u64 oarb2:2; + u64 optrs:4; + u64 obulk:4; + u64 rtn:2; + u64 ofree:1; + u64 itag:1; + u64 otag:2; + u64 bell:2; + u64 cram:2; + u64 mram:2; + u64 reserved_44_63:20; +#endif + } cn63xx; + struct cvmx_sriox_bist_status_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_44_63:20; + u64 mram:2; + u64 cram:2; + u64 bell:2; + u64 otag:2; + u64 itag:1; + u64 ofree:1; + u64 rtn:2; + u64 obulk:4; + u64 optrs:4; + u64 reserved_20_23:4; + u64 oarb:2; + u64 ispf:1; + u64 ospf:1; + u64 txbuf:2; + u64 rxbuf:2; + u64 imsg:5; + u64 omsg:7; +#else + u64 omsg:7; + u64 imsg:5; + u64 rxbuf:2; + u64 txbuf:2; + u64 ospf:1; + u64 ispf:1; + u64 oarb:2; + u64 reserved_20_23:4; + u64 optrs:4; + u64 obulk:4; + u64 rtn:2; + u64 ofree:1; + u64 itag:1; + u64 otag:2; + u64 bell:2; + u64 cram:2; + u64 mram:2; + u64 reserved_44_63:20; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_imsg_ctrl { + u64 u64; + struct cvmx_sriox_imsg_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 to_mode:1; + u64 reserved_30_30:1; + u64 rsp_thr:6; + u64 reserved_22_23:2; + u64 rp1_sid:1; + u64 rp0_sid:2; + u64 rp1_pid:1; + u64 rp0_pid:2; + u64 reserved_15_15:1; + u64 prt_sel:3; + u64 lttr:4; + u64 prio:4; + u64 mbox:4; +#else + u64 mbox:4; + u64 prio:4; + u64 lttr:4; + u64 prt_sel:3; + u64 reserved_15_15:1; + u64 rp0_pid:2; + u64 rp1_pid:1; + u64 rp0_sid:2; + u64 rp1_sid:1; + u64 reserved_22_23:2; + u64 rsp_thr:6; + u64 reserved_30_30:1; + u64 to_mode:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_imsg_inst_hdrx { + u64 u64; + struct cvmx_sriox_imsg_inst_hdrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 r:1; + u64 reserved_58_62:5; + u64 pm:2; + u64 reserved_55_55:1; + u64 sl:7; + u64 reserved_46_47:2; + u64 nqos:1; + u64 ngrp:1; + u64 ntt:1; + u64 ntag:1; + u64 reserved_35_41:7; + u64 rs:1; + u64 tt:2; + u64 tag:32; +#else + u64 tag:32; + u64 tt:2; + u64 rs:1; + u64 reserved_35_41:7; + u64 ntag:1; + u64 ntt:1; + u64 ngrp:1; + u64 nqos:1; + u64 reserved_46_47:2; + u64 sl:7; + u64 reserved_55_55:1; + u64 pm:2; + u64 reserved_58_62:5; + u64 r:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_qos_grpx { + u64 u64; + struct cvmx_sriox_imsg_qos_grpx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_63_63:1; + u64 qos7:3; + u64 grp7:4; + u64 reserved_55_55:1; + u64 qos6:3; + u64 grp6:4; + u64 reserved_47_47:1; + u64 qos5:3; + u64 grp5:4; + u64 reserved_39_39:1; + u64 qos4:3; + u64 grp4:4; + u64 reserved_31_31:1; + u64 qos3:3; + u64 grp3:4; + u64 reserved_23_23:1; + u64 qos2:3; + u64 grp2:4; + u64 reserved_15_15:1; + u64 qos1:3; + u64 grp1:4; + u64 reserved_7_7:1; + u64 qos0:3; + u64 grp0:4; +#else + u64 grp0:4; + u64 qos0:3; + u64 reserved_7_7:1; + u64 grp1:4; + u64 qos1:3; + u64 reserved_15_15:1; + u64 grp2:4; + u64 qos2:3; + u64 reserved_23_23:1; + u64 grp3:4; + u64 qos3:3; + u64 reserved_31_31:1; + u64 grp4:4; + u64 qos4:3; + u64 reserved_39_39:1; + u64 grp5:4; + u64 qos5:3; + u64 reserved_47_47:1; + u64 grp6:4; + u64 qos6:3; + u64 reserved_55_55:1; + u64 grp7:4; + u64 qos7:3; + u64 reserved_63_63:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_statusx { + u64 u64; + struct cvmx_sriox_imsg_statusx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 val1:1; + u64 err1:1; + u64 toe1:1; + u64 toc1:1; + u64 prt1:1; + u64 reserved_58_58:1; + u64 tt1:1; + u64 dis1:1; + u64 seg1:4; + u64 mbox1:2; + u64 lttr1:2; + u64 sid1:16; + u64 val0:1; + u64 err0:1; + u64 toe0:1; + u64 toc0:1; + u64 prt0:1; + u64 reserved_26_26:1; + u64 tt0:1; + u64 dis0:1; + u64 seg0:4; + u64 mbox0:2; + u64 lttr0:2; + u64 sid0:16; +#else + u64 sid0:16; + u64 lttr0:2; + u64 mbox0:2; + u64 seg0:4; + u64 dis0:1; + u64 tt0:1; + u64 reserved_26_26:1; + u64 prt0:1; + u64 toc0:1; + u64 toe0:1; + u64 err0:1; + u64 val0:1; + u64 sid1:16; + u64 lttr1:2; + u64 mbox1:2; + u64 seg1:4; + u64 dis1:1; + u64 tt1:1; + u64 reserved_58_58:1; + u64 prt1:1; + u64 toc1:1; + u64 toe1:1; + u64 err1:1; + u64 val1:1; +#endif + } s; +}; + +union cvmx_sriox_imsg_vport_thr { + u64 u64; + struct cvmx_sriox_imsg_vport_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_54_63:10; + u64 max_tot:6; + u64 reserved_46_47:2; + u64 max_s1:6; + u64 reserved_38_39:2; + u64 max_s0:6; + u64 sp_vport:1; + u64 reserved_20_30:11; + u64 buf_thr:4; + u64 reserved_14_15:2; + u64 max_p1:6; + u64 reserved_6_7:2; + u64 max_p0:6; +#else + u64 max_p0:6; + u64 reserved_6_7:2; + u64 max_p1:6; + u64 reserved_14_15:2; + u64 buf_thr:4; + u64 reserved_20_30:11; + u64 sp_vport:1; + u64 max_s0:6; + u64 reserved_38_39:2; + u64 max_s1:6; + u64 reserved_46_47:2; + u64 max_tot:6; + u64 reserved_54_63:10; +#endif + } s; +}; + +union cvmx_sriox_imsg_vport_thr2 { + u64 u64; + struct cvmx_sriox_imsg_vport_thr2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_46_63:18; + u64 max_s3:6; + u64 reserved_38_39:2; + u64 max_s2:6; + u64 reserved_0_31:32; +#else + u64 reserved_0_31:32; + u64 max_s2:6; + u64 reserved_38_39:2; + u64 max_s3:6; + u64 reserved_46_63:18; +#endif + } s; +}; + +union cvmx_sriox_int2_enable { + u64 u64; + struct cvmx_sriox_int2_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 pko_rst:1; +#else + u64 pko_rst:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_sriox_int2_reg { + u64 u64; + struct cvmx_sriox_int2_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 int_sum:1; + u64 reserved_1_30:30; + u64 pko_rst:1; +#else + u64 pko_rst:1; + u64 reserved_1_30:30; + u64 int_sum:1; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_int_enable { + u64 u64; + struct cvmx_sriox_int_enable_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_27_63:37; + u64 zero_pkt:1; + u64 ttl_tout:1; + u64 fail:1; + u64 degrade:1; + u64 mac_buf:1; + u64 f_error:1; + u64 rtry_err:1; + u64 pko_err:1; + u64 omsg_err:1; + u64 omsg1:1; + u64 omsg0:1; + u64 link_up:1; + u64 link_dwn:1; + u64 phy_erb:1; + u64 log_erb:1; + u64 soft_rx:1; + u64 soft_tx:1; + u64 mce_rx:1; + u64 mce_tx:1; + u64 wr_done:1; + u64 sli_err:1; + u64 deny_wr:1; + u64 bar_err:1; + u64 maint_op:1; + u64 rxbell:1; + u64 bell_err:1; + u64 txbell:1; +#else + u64 txbell:1; + u64 bell_err:1; + u64 rxbell:1; + u64 maint_op:1; + u64 bar_err:1; + u64 deny_wr:1; + u64 sli_err:1; + u64 wr_done:1; + u64 mce_tx:1; + u64 mce_rx:1; + u64 soft_tx:1; + u64 soft_rx:1; + u64 log_erb:1; + u64 phy_erb:1; + u64 link_dwn:1; + u64 link_up:1; + u64 omsg0:1; + u64 omsg1:1; + u64 omsg_err:1; + u64 pko_err:1; + u64 rtry_err:1; + u64 f_error:1; + u64 mac_buf:1; + u64 degrade:1; + u64 fail:1; + u64 ttl_tout:1; + u64 zero_pkt:1; + u64 reserved_27_63:37; +#endif + } s; + struct cvmx_sriox_int_enable_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 f_error:1; + u64 rtry_err:1; + u64 pko_err:1; + u64 omsg_err:1; + u64 omsg1:1; + u64 omsg0:1; + u64 link_up:1; + u64 link_dwn:1; + u64 phy_erb:1; + u64 log_erb:1; + u64 soft_rx:1; + u64 soft_tx:1; + u64 mce_rx:1; + u64 mce_tx:1; + u64 wr_done:1; + u64 sli_err:1; + u64 deny_wr:1; + u64 bar_err:1; + u64 maint_op:1; + u64 rxbell:1; + u64 bell_err:1; + u64 txbell:1; +#else + u64 txbell:1; + u64 bell_err:1; + u64 rxbell:1; + u64 maint_op:1; + u64 bar_err:1; + u64 deny_wr:1; + u64 sli_err:1; + u64 wr_done:1; + u64 mce_tx:1; + u64 mce_rx:1; + u64 soft_tx:1; + u64 soft_rx:1; + u64 log_erb:1; + u64 phy_erb:1; + u64 link_dwn:1; + u64 link_up:1; + u64 omsg0:1; + u64 omsg1:1; + u64 omsg_err:1; + u64 pko_err:1; + u64 rtry_err:1; + u64 f_error:1; + u64 reserved_22_63:42; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_int_info0 { + u64 u64; + struct cvmx_sriox_int_info0_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 cmd:4; + u64 type:4; + u64 tag:8; + u64 reserved_42_47:6; + u64 length:10; + u64 status:3; + u64 reserved_16_28:13; + u64 be0:8; + u64 be1:8; +#else + u64 be1:8; + u64 be0:8; + u64 reserved_16_28:13; + u64 status:3; + u64 length:10; + u64 reserved_42_47:6; + u64 tag:8; + u64 type:4; + u64 cmd:4; +#endif + } s; +}; + +union cvmx_sriox_int_info1 { + u64 u64; + struct cvmx_sriox_int_info1_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 info1:64; +#else + u64 info1:64; +#endif + } s; +}; + +union cvmx_sriox_int_info2 { + u64 u64; + struct cvmx_sriox_int_info2_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 prio:2; + u64 tt:1; + u64 sis:1; + u64 ssize:4; + u64 did:16; + u64 xmbox:4; + u64 mbox:2; + u64 letter:2; + u64 rsrvd:30; + u64 lns:1; + u64 intr:1; +#else + u64 intr:1; + u64 lns:1; + u64 rsrvd:30; + u64 letter:2; + u64 mbox:2; + u64 xmbox:4; + u64 did:16; + u64 ssize:4; + u64 sis:1; + u64 tt:1; + u64 prio:2; +#endif + } s; +}; + +union cvmx_sriox_int_info3 { + u64 u64; + struct cvmx_sriox_int_info3_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 prio:2; + u64 tt:2; + u64 type:4; + u64 other:48; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 other:48; + u64 type:4; + u64 tt:2; + u64 prio:2; +#endif + } s; +}; + +union cvmx_sriox_int_reg { + u64 u64; + struct cvmx_sriox_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 int2_sum:1; + u64 reserved_27_30:4; + u64 zero_pkt:1; + u64 ttl_tout:1; + u64 fail:1; + u64 degrad:1; + u64 mac_buf:1; + u64 f_error:1; + u64 rtry_err:1; + u64 pko_err:1; + u64 omsg_err:1; + u64 omsg1:1; + u64 omsg0:1; + u64 link_up:1; + u64 link_dwn:1; + u64 phy_erb:1; + u64 log_erb:1; + u64 soft_rx:1; + u64 soft_tx:1; + u64 mce_rx:1; + u64 mce_tx:1; + u64 wr_done:1; + u64 sli_err:1; + u64 deny_wr:1; + u64 bar_err:1; + u64 maint_op:1; + u64 rxbell:1; + u64 bell_err:1; + u64 txbell:1; +#else + u64 txbell:1; + u64 bell_err:1; + u64 rxbell:1; + u64 maint_op:1; + u64 bar_err:1; + u64 deny_wr:1; + u64 sli_err:1; + u64 wr_done:1; + u64 mce_tx:1; + u64 mce_rx:1; + u64 soft_tx:1; + u64 soft_rx:1; + u64 log_erb:1; + u64 phy_erb:1; + u64 link_dwn:1; + u64 link_up:1; + u64 omsg0:1; + u64 omsg1:1; + u64 omsg_err:1; + u64 pko_err:1; + u64 rtry_err:1; + u64 f_error:1; + u64 mac_buf:1; + u64 degrad:1; + u64 fail:1; + u64 ttl_tout:1; + u64 zero_pkt:1; + u64 reserved_27_30:4; + u64 int2_sum:1; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_sriox_int_reg_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_22_63:42; + u64 f_error:1; + u64 rtry_err:1; + u64 pko_err:1; + u64 omsg_err:1; + u64 omsg1:1; + u64 omsg0:1; + u64 link_up:1; + u64 link_dwn:1; + u64 phy_erb:1; + u64 log_erb:1; + u64 soft_rx:1; + u64 soft_tx:1; + u64 mce_rx:1; + u64 mce_tx:1; + u64 wr_done:1; + u64 sli_err:1; + u64 deny_wr:1; + u64 bar_err:1; + u64 maint_op:1; + u64 rxbell:1; + u64 bell_err:1; + u64 txbell:1; +#else + u64 txbell:1; + u64 bell_err:1; + u64 rxbell:1; + u64 maint_op:1; + u64 bar_err:1; + u64 deny_wr:1; + u64 sli_err:1; + u64 wr_done:1; + u64 mce_tx:1; + u64 mce_rx:1; + u64 soft_tx:1; + u64 soft_rx:1; + u64 log_erb:1; + u64 phy_erb:1; + u64 link_dwn:1; + u64 link_up:1; + u64 omsg0:1; + u64 omsg1:1; + u64 omsg_err:1; + u64 pko_err:1; + u64 rtry_err:1; + u64 f_error:1; + u64 reserved_22_63:42; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_ip_feature { + u64 u64; + struct cvmx_sriox_ip_feature_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ops:32; + u64 reserved_15_31:17; + u64 no_vmin:1; + u64 a66:1; + u64 a50:1; + u64 reserved_11_11:1; + u64 tx_flow:1; + u64 pt_width:2; + u64 tx_pol:4; + u64 rx_pol:4; +#else + u64 rx_pol:4; + u64 tx_pol:4; + u64 pt_width:2; + u64 tx_flow:1; + u64 reserved_11_11:1; + u64 a50:1; + u64 a66:1; + u64 no_vmin:1; + u64 reserved_15_31:17; + u64 ops:32; +#endif + } s; + struct cvmx_sriox_ip_feature_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 ops:32; + u64 reserved_14_31:18; + u64 a66:1; + u64 a50:1; + u64 reserved_11_11:1; + u64 tx_flow:1; + u64 pt_width:2; + u64 tx_pol:4; + u64 rx_pol:4; +#else + u64 rx_pol:4; + u64 tx_pol:4; + u64 pt_width:2; + u64 tx_flow:1; + u64 reserved_11_11:1; + u64 a50:1; + u64 a66:1; + u64 reserved_14_31:18; + u64 ops:32; +#endif + } cn63xx; +}; + +union cvmx_sriox_mac_buffers { + u64 u64; + struct cvmx_sriox_mac_buffers_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_56_63:8; + u64 tx_enb:8; + u64 reserved_44_47:4; + u64 tx_inuse:4; + u64 tx_stat:8; + u64 reserved_24_31:8; + u64 rx_enb:8; + u64 reserved_12_15:4; + u64 rx_inuse:4; + u64 rx_stat:8; +#else + u64 rx_stat:8; + u64 rx_inuse:4; + u64 reserved_12_15:4; + u64 rx_enb:8; + u64 reserved_24_31:8; + u64 tx_stat:8; + u64 tx_inuse:4; + u64 reserved_44_47:4; + u64 tx_enb:8; + u64 reserved_56_63:8; +#endif + } s; +}; + +union cvmx_sriox_maint_op { + u64 u64; + struct cvmx_sriox_maint_op_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 wr_data:32; + u64 reserved_27_31:5; + u64 fail:1; + u64 pending:1; + u64 op:1; + u64 addr:24; +#else + u64 addr:24; + u64 op:1; + u64 pending:1; + u64 fail:1; + u64 reserved_27_31:5; + u64 wr_data:32; +#endif + } s; +}; + +union cvmx_sriox_maint_rd_data { + u64 u64; + struct cvmx_sriox_maint_rd_data_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_33_63:31; + u64 valid:1; + u64 rd_data:32; +#else + u64 rd_data:32; + u64 valid:1; + u64 reserved_33_63:31; +#endif + } s; +}; + +union cvmx_sriox_mce_tx_ctl { + u64 u64; + struct cvmx_sriox_mce_tx_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 mce:1; +#else + u64 mce:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_sriox_mem_op_ctrl { + u64 u64; + struct cvmx_sriox_mem_op_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 rr_ro:1; + u64 w_ro:1; + u64 reserved_6_7:2; + u64 rp1_sid:1; + u64 rp0_sid:2; + u64 rp1_pid:1; + u64 rp0_pid:2; +#else + u64 rp0_pid:2; + u64 rp1_pid:1; + u64 rp0_sid:2; + u64 rp1_sid:1; + u64 reserved_6_7:2; + u64 w_ro:1; + u64 rr_ro:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_sriox_omsg_ctrlx { + u64 u64; + struct cvmx_sriox_omsg_ctrlx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 testmode:1; + u64 reserved_37_62:26; + u64 silo_max:5; + u64 rtry_thr:16; + u64 rtry_en:1; + u64 reserved_11_14:4; + u64 idm_tt:1; + u64 idm_sis:1; + u64 idm_did:1; + u64 lttr_sp:4; + u64 lttr_mp:4; +#else + u64 lttr_mp:4; + u64 lttr_sp:4; + u64 idm_did:1; + u64 idm_sis:1; + u64 idm_tt:1; + u64 reserved_11_14:4; + u64 rtry_en:1; + u64 rtry_thr:16; + u64 silo_max:5; + u64 reserved_37_62:26; + u64 testmode:1; +#endif + } s; + struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD + u64 testmode:1; + u64 reserved_32_62:31; + u64 rtry_thr:16; + u64 rtry_en:1; + u64 reserved_11_14:4; + u64 idm_tt:1; + u64 idm_sis:1; + u64 idm_did:1; + u64 lttr_sp:4; + u64 lttr_mp:4; +#else + u64 lttr_mp:4; + u64 lttr_sp:4; + u64 idm_did:1; + u64 idm_sis:1; + u64 idm_tt:1; + u64 reserved_11_14:4; + u64 rtry_en:1; + u64 rtry_thr:16; + u64 reserved_32_62:31; + u64 testmode:1; +#endif + } cn63xxp1; +}; + +union cvmx_sriox_omsg_done_countsx { + u64 u64; + struct cvmx_sriox_omsg_done_countsx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bad:16; + u64 good:16; +#else + u64 good:16; + u64 bad:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_omsg_fmp_mrx { + u64 u64; + struct cvmx_sriox_omsg_fmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 ctlr_sp:1; + u64 ctlr_fmp:1; + u64 ctlr_nmp:1; + u64 id_sp:1; + u64 id_fmp:1; + u64 id_nmp:1; + u64 id_psd:1; + u64 mbox_sp:1; + u64 mbox_fmp:1; + u64 mbox_nmp:1; + u64 mbox_psd:1; + u64 all_sp:1; + u64 all_fmp:1; + u64 all_nmp:1; + u64 all_psd:1; +#else + u64 all_psd:1; + u64 all_nmp:1; + u64 all_fmp:1; + u64 all_sp:1; + u64 mbox_psd:1; + u64 mbox_nmp:1; + u64 mbox_fmp:1; + u64 mbox_sp:1; + u64 id_psd:1; + u64 id_nmp:1; + u64 id_fmp:1; + u64 id_sp:1; + u64 ctlr_nmp:1; + u64 ctlr_fmp:1; + u64 ctlr_sp:1; + u64 reserved_15_63:49; +#endif + } s; +}; + +union cvmx_sriox_omsg_nmp_mrx { + u64 u64; + struct cvmx_sriox_omsg_nmp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_15_63:49; + u64 ctlr_sp:1; + u64 ctlr_fmp:1; + u64 ctlr_nmp:1; + u64 id_sp:1; + u64 id_fmp:1; + u64 id_nmp:1; + u64 reserved_8_8:1; + u64 mbox_sp:1; + u64 mbox_fmp:1; + u64 mbox_nmp:1; + u64 reserved_4_4:1; + u64 all_sp:1; + u64 all_fmp:1; + u64 all_nmp:1; + u64 reserved_0_0:1; +#else + u64 reserved_0_0:1; + u64 all_nmp:1; + u64 all_fmp:1; + u64 all_sp:1; + u64 reserved_4_4:1; + u64 mbox_nmp:1; + u64 mbox_fmp:1; + u64 mbox_sp:1; + u64 reserved_8_8:1; + u64 id_nmp:1; + u64 id_fmp:1; + u64 id_sp:1; + u64 ctlr_nmp:1; + u64 ctlr_fmp:1; + u64 ctlr_sp:1; + u64 reserved_15_63:49; +#endif + } s; +}; + +union cvmx_sriox_omsg_portx { + u64 u64; + struct cvmx_sriox_omsg_portx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enable:1; + u64 reserved_3_30:28; + u64 port:3; +#else + u64 port:3; + u64 reserved_3_30:28; + u64 enable:1; + u64 reserved_32_63:32; +#endif + } s; + struct cvmx_sriox_omsg_portx_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 enable:1; + u64 reserved_2_30:29; + u64 port:2; +#else + u64 port:2; + u64 reserved_2_30:29; + u64 enable:1; + u64 reserved_32_63:32; +#endif + } cn63xx; +}; + +union cvmx_sriox_omsg_silo_thr { + u64 u64; + struct cvmx_sriox_omsg_silo_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 tot_silo:5; +#else + u64 tot_silo:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_sriox_omsg_sp_mrx { + u64 u64; + struct cvmx_sriox_omsg_sp_mrx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 xmbox_sp:1; + u64 ctlr_sp:1; + u64 ctlr_fmp:1; + u64 ctlr_nmp:1; + u64 id_sp:1; + u64 id_fmp:1; + u64 id_nmp:1; + u64 id_psd:1; + u64 mbox_sp:1; + u64 mbox_fmp:1; + u64 mbox_nmp:1; + u64 mbox_psd:1; + u64 all_sp:1; + u64 all_fmp:1; + u64 all_nmp:1; + u64 all_psd:1; +#else + u64 all_psd:1; + u64 all_nmp:1; + u64 all_fmp:1; + u64 all_sp:1; + u64 mbox_psd:1; + u64 mbox_nmp:1; + u64 mbox_fmp:1; + u64 mbox_sp:1; + u64 id_psd:1; + u64 id_nmp:1; + u64 id_fmp:1; + u64 id_sp:1; + u64 ctlr_nmp:1; + u64 ctlr_fmp:1; + u64 ctlr_sp:1; + u64 xmbox_sp:1; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_sriox_priox_in_use { + u64 u64; + struct cvmx_sriox_priox_in_use_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 end_cnt:16; + u64 start_cnt:16; +#else + u64 start_cnt:16; + u64 end_cnt:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_rx_bell { + u64 u64; + struct cvmx_sriox_rx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 data:16; + u64 src_id:16; + u64 count:8; + u64 reserved_5_7:3; + u64 dest_id:1; + u64 id16:1; + u64 reserved_2_2:1; + u64 priority:2; +#else + u64 priority:2; + u64 reserved_2_2:1; + u64 id16:1; + u64 dest_id:1; + u64 reserved_5_7:3; + u64 count:8; + u64 src_id:16; + u64 data:16; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_rx_bell_seq { + u64 u64; + struct cvmx_sriox_rx_bell_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_40_63:24; + u64 count:8; + u64 seq:32; +#else + u64 seq:32; + u64 count:8; + u64 reserved_40_63:24; +#endif + } s; +}; + +union cvmx_sriox_rx_status { + u64 u64; + struct cvmx_sriox_rx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 rtn_pr3:8; + u64 rtn_pr2:8; + u64 rtn_pr1:8; + u64 reserved_28_39:12; + u64 mbox:4; + u64 comp:8; + u64 reserved_13_15:3; + u64 n_post:5; + u64 post:8; +#else + u64 post:8; + u64 n_post:5; + u64 reserved_13_15:3; + u64 comp:8; + u64 mbox:4; + u64 reserved_28_39:12; + u64 rtn_pr1:8; + u64 rtn_pr2:8; + u64 rtn_pr3:8; +#endif + } s; +}; + +union cvmx_sriox_s2m_typex { + u64 u64; + struct cvmx_sriox_s2m_typex_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 wr_op:3; + u64 reserved_15_15:1; + u64 rd_op:3; + u64 wr_prior:2; + u64 rd_prior:2; + u64 reserved_6_7:2; + u64 src_id:1; + u64 id16:1; + u64 reserved_2_3:2; + u64 iaow_sel:2; +#else + u64 iaow_sel:2; + u64 reserved_2_3:2; + u64 id16:1; + u64 src_id:1; + u64 reserved_6_7:2; + u64 rd_prior:2; + u64 wr_prior:2; + u64 rd_op:3; + u64 reserved_15_15:1; + u64 wr_op:3; + u64 reserved_19_63:45; +#endif + } s; +}; + +union cvmx_sriox_seq { + u64 u64; + struct cvmx_sriox_seq_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 seq:32; +#else + u64 seq:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_status_reg { + u64 u64; + struct cvmx_sriox_status_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_2_63:62; + u64 access:1; + u64 srio:1; +#else + u64 srio:1; + u64 access:1; + u64 reserved_2_63:62; +#endif + } s; +}; + +union cvmx_sriox_tag_ctrl { + u64 u64; + struct cvmx_sriox_tag_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 o_clr:1; + u64 reserved_13_15:3; + u64 otag:5; + u64 reserved_5_7:3; + u64 itag:5; +#else + u64 itag:5; + u64 reserved_5_7:3; + u64 otag:5; + u64 reserved_13_15:3; + u64 o_clr:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_sriox_tlp_credits { + u64 u64; + struct cvmx_sriox_tlp_credits_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_28_63:36; + u64 mbox:4; + u64 comp:8; + u64 reserved_13_15:3; + u64 n_post:5; + u64 post:8; +#else + u64 post:8; + u64 n_post:5; + u64 reserved_13_15:3; + u64 comp:8; + u64 mbox:4; + u64 reserved_28_63:36; +#endif + } s; +}; + +union cvmx_sriox_tx_bell { + u64 u64; + struct cvmx_sriox_tx_bell_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 data:16; + u64 dest_id:16; + u64 reserved_9_15:7; + u64 pending:1; + u64 reserved_5_7:3; + u64 src_id:1; + u64 id16:1; + u64 reserved_2_2:1; + u64 priority:2; +#else + u64 priority:2; + u64 reserved_2_2:1; + u64 id16:1; + u64 src_id:1; + u64 reserved_5_7:3; + u64 pending:1; + u64 reserved_9_15:7; + u64 dest_id:16; + u64 data:16; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_tx_bell_info { + u64 u64; + struct cvmx_sriox_tx_bell_info_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_48_63:16; + u64 data:16; + u64 dest_id:16; + u64 reserved_8_15:8; + u64 timeout:1; + u64 error:1; + u64 retry:1; + u64 src_id:1; + u64 id16:1; + u64 reserved_2_2:1; + u64 priority:2; +#else + u64 priority:2; + u64 reserved_2_2:1; + u64 id16:1; + u64 src_id:1; + u64 retry:1; + u64 error:1; + u64 timeout:1; + u64 reserved_8_15:8; + u64 dest_id:16; + u64 data:16; + u64 reserved_48_63:16; +#endif + } s; +}; + +union cvmx_sriox_tx_ctrl { + u64 u64; + struct cvmx_sriox_tx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_53_63:11; + u64 tag_th2:5; + u64 reserved_45_47:3; + u64 tag_th1:5; + u64 reserved_37_39:3; + u64 tag_th0:5; + u64 reserved_20_31:12; + u64 tx_th2:4; + u64 reserved_12_15:4; + u64 tx_th1:4; + u64 reserved_4_7:4; + u64 tx_th0:4; +#else + u64 tx_th0:4; + u64 reserved_4_7:4; + u64 tx_th1:4; + u64 reserved_12_15:4; + u64 tx_th2:4; + u64 reserved_20_31:12; + u64 tag_th0:5; + u64 reserved_37_39:3; + u64 tag_th1:5; + u64 reserved_45_47:3; + u64 tag_th2:5; + u64 reserved_53_63:11; +#endif + } s; +}; + +union cvmx_sriox_tx_emphasis { + u64 u64; + struct cvmx_sriox_tx_emphasis_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 emph:4; +#else + u64 emph:4; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_sriox_tx_status { + u64 u64; + struct cvmx_sriox_tx_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 s2m_pr3:8; + u64 s2m_pr2:8; + u64 s2m_pr1:8; + u64 s2m_pr0:8; +#else + u64 s2m_pr0:8; + u64 s2m_pr1:8; + u64 s2m_pr2:8; + u64 s2m_pr3:8; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_sriox_wr_done_counts { + u64 u64; + struct cvmx_sriox_wr_done_counts_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 bad:16; + u64 good:16; +#else + u64 good:16; + u64 bad:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/drivers/staging/octeon/cvmx-srxx-defs.h new file mode 100644 index 000000000000..0926dd77bc0f --- /dev/null +++ b/drivers/staging/octeon/cvmx-srxx-defs.h @@ -0,0 +1,139 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SRXX_DEFS_H__ +#define __CVMX_SRXX_DEFS_H__ + +#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) + +union cvmx_srxx_com_ctl { + u64 u64; + struct cvmx_srxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 prts:4; + u64 st_en:1; + u64 reserved_1_2:2; + u64 inf_en:1; +#else + u64 inf_en:1; + u64 reserved_1_2:2; + u64 st_en:1; + u64 prts:4; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_srxx_ign_rx_full { + u64 u64; + struct cvmx_srxx_ign_rx_full_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 ignore:16; +#else + u64 ignore:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_srxx_spi4_calx { + u64 u64; + struct cvmx_srxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 oddpar:1; + u64 prt3:4; + u64 prt2:4; + u64 prt1:4; + u64 prt0:4; +#else + u64 prt0:4; + u64 prt1:4; + u64 prt2:4; + u64 prt3:4; + u64 oddpar:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_srxx_spi4_stat { + u64 u64; + struct cvmx_srxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 m:8; + u64 reserved_7_7:1; + u64 len:7; +#else + u64 len:7; + u64 reserved_7_7:1; + u64 m:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_srxx_sw_tick_ctl { + u64 u64; + struct cvmx_srxx_sw_tick_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_14_63:50; + u64 eop:1; + u64 sop:1; + u64 mod:4; + u64 opc:4; + u64 adr:4; +#else + u64 adr:4; + u64 opc:4; + u64 mod:4; + u64 sop:1; + u64 eop:1; + u64 reserved_14_63:50; +#endif + } s; +}; + +union cvmx_srxx_sw_tick_dat { + u64 u64; + struct cvmx_srxx_sw_tick_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 dat:64; +#else + u64 dat:64; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/drivers/staging/octeon/cvmx-stxx-defs.h new file mode 100644 index 000000000000..fddf14554176 --- /dev/null +++ b/drivers/staging/octeon/cvmx-stxx-defs.h @@ -0,0 +1,329 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (C) 2003-2018 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_STXX_DEFS_H__ +#define __CVMX_STXX_DEFS_H__ + +#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) +#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) +#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) + +void __cvmx_interrupt_stxx_int_msk_enable(int index); + +union cvmx_stxx_arb_ctl { + u64 u64; + struct cvmx_stxx_arb_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 mintrn:1; + u64 reserved_4_4:1; + u64 igntpa:1; + u64 reserved_0_2:3; +#else + u64 reserved_0_2:3; + u64 igntpa:1; + u64 reserved_4_4:1; + u64 mintrn:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_stxx_bckprs_cnt { + u64 u64; + struct cvmx_stxx_bckprs_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_stxx_com_ctl { + u64 u64; + struct cvmx_stxx_com_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_4_63:60; + u64 st_en:1; + u64 reserved_1_2:2; + u64 inf_en:1; +#else + u64 inf_en:1; + u64 reserved_1_2:2; + u64 st_en:1; + u64 reserved_4_63:60; +#endif + } s; +}; + +union cvmx_stxx_dip_cnt { + u64 u64; + struct cvmx_stxx_dip_cnt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 frmmax:4; + u64 dipmax:4; +#else + u64 dipmax:4; + u64 frmmax:4; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_stxx_ign_cal { + u64 u64; + struct cvmx_stxx_ign_cal_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 igntpa:16; +#else + u64 igntpa:16; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_stxx_int_msk { + u64 u64; + struct cvmx_stxx_int_msk_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 frmerr:1; + u64 unxfrm:1; + u64 nosync:1; + u64 diperr:1; + u64 datovr:1; + u64 ovrbst:1; + u64 calpar1:1; + u64 calpar0:1; +#else + u64 calpar0:1; + u64 calpar1:1; + u64 ovrbst:1; + u64 datovr:1; + u64 diperr:1; + u64 nosync:1; + u64 unxfrm:1; + u64 frmerr:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_stxx_int_reg { + u64 u64; + struct cvmx_stxx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 syncerr:1; + u64 frmerr:1; + u64 unxfrm:1; + u64 nosync:1; + u64 diperr:1; + u64 datovr:1; + u64 ovrbst:1; + u64 calpar1:1; + u64 calpar0:1; +#else + u64 calpar0:1; + u64 calpar1:1; + u64 ovrbst:1; + u64 datovr:1; + u64 diperr:1; + u64 nosync:1; + u64 unxfrm:1; + u64 frmerr:1; + u64 syncerr:1; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_stxx_int_sync { + u64 u64; + struct cvmx_stxx_int_sync_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 frmerr:1; + u64 unxfrm:1; + u64 nosync:1; + u64 diperr:1; + u64 datovr:1; + u64 ovrbst:1; + u64 calpar1:1; + u64 calpar0:1; +#else + u64 calpar0:1; + u64 calpar1:1; + u64 ovrbst:1; + u64 datovr:1; + u64 diperr:1; + u64 nosync:1; + u64 unxfrm:1; + u64 frmerr:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_stxx_min_bst { + u64 u64; + struct cvmx_stxx_min_bst_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_9_63:55; + u64 minb:9; +#else + u64 minb:9; + u64 reserved_9_63:55; +#endif + } s; +}; + +union cvmx_stxx_spi4_calx { + u64 u64; + struct cvmx_stxx_spi4_calx_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_17_63:47; + u64 oddpar:1; + u64 prt3:4; + u64 prt2:4; + u64 prt1:4; + u64 prt0:4; +#else + u64 prt0:4; + u64 prt1:4; + u64 prt2:4; + u64 prt3:4; + u64 oddpar:1; + u64 reserved_17_63:47; +#endif + } s; +}; + +union cvmx_stxx_spi4_dat { + u64 u64; + struct cvmx_stxx_spi4_dat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 alpha:16; + u64 max_t:16; +#else + u64 max_t:16; + u64 alpha:16; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_stxx_spi4_stat { + u64 u64; + struct cvmx_stxx_spi4_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_16_63:48; + u64 m:8; + u64 reserved_7_7:1; + u64 len:7; +#else + u64 len:7; + u64 reserved_7_7:1; + u64 m:8; + u64 reserved_16_63:48; +#endif + } s; +}; + +union cvmx_stxx_stat_bytes_hi { + u64 u64; + struct cvmx_stxx_stat_bytes_hi_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_stxx_stat_bytes_lo { + u64 u64; + struct cvmx_stxx_stat_bytes_lo_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_stxx_stat_ctl { + u64 u64; + struct cvmx_stxx_stat_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 clr:1; + u64 bckprs:4; +#else + u64 bckprs:4; + u64 clr:1; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_stxx_stat_pkt_xmt { + u64 u64; + struct cvmx_stxx_stat_pkt_xmt_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 cnt:32; +#else + u64 cnt:32; + u64 reserved_32_63:32; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-sysinfo.h b/drivers/staging/octeon/cvmx-sysinfo.h new file mode 100644 index 000000000000..3229648265c6 --- /dev/null +++ b/drivers/staging/octeon/cvmx-sysinfo.h @@ -0,0 +1,123 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2016 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * This module provides system/board information obtained by the bootloader. + */ + +#ifndef __CVMX_SYSINFO_H__ +#define __CVMX_SYSINFO_H__ + +#include "cvmx-coremask.h" + +#define OCTEON_SERIAL_LEN 20 +/** + * Structure describing application specific information. + * __cvmx_app_init() populates this from the cvmx boot descriptor. + * This structure is private to simple executive applications, so + * no versioning is required. + * + * This structure must be provided with some fields set in order to + * use simple executive functions in other applications (Linux kernel, + * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is + * provided to set the required values in these cases. + */ +struct cvmx_sysinfo { + /* System wide variables */ + /* installed DRAM in system, in bytes */ + u64 system_dram_size; + + /* ptr to memory descriptor block */ + u64 phy_mem_desc_addr; + + /* Application image specific variables */ + /* stack top address (virtual) */ + u64 stack_top; + /* heap base address (virtual) */ + u64 heap_base; + /* stack size in bytes */ + u32 stack_size; + /* heap size in bytes */ + u32 heap_size; + /* coremask defining cores running application */ + struct cvmx_coremask core_mask; + /* Deprecated, use cvmx_coremask_first_core() to select init core */ + u32 init_core; + + /* exception base address, as set by bootloader */ + u64 exception_base_addr; + + /* cpu clock speed in hz */ + u32 cpu_clock_hz; + + /* dram data rate in hz (data rate = 2 * clock rate */ + u32 dram_data_rate_hz; + + u16 board_type; + u8 board_rev_major; + u8 board_rev_minor; + u8 mac_addr_base[6]; + u8 mac_addr_count; + char board_serial_number[OCTEON_SERIAL_LEN]; + /* + * Several boards support compact flash on the Octeon boot + * bus. The CF memory spaces may be mapped to different + * addresses on different boards. These values will be 0 if + * CF is not present. Note that these addresses are physical + * addresses, and it is up to the application to use the + * proper addressing mode (XKPHYS, KSEG0, etc.) + */ + u64 compact_flash_common_base_addr; + u64 compact_flash_attribute_base_addr; + /* + * Base address of the LED display (as on EBT3000 board) This + * will be 0 if LED display not present. Note that this + * address is a physical address, and it is up to the + * application to use the proper addressing mode (XKPHYS, + * KSEG0, etc.) + */ + u64 led_display_base_addr; + /* DFA reference clock in hz (if applicable)*/ + u32 dfa_ref_clock_hz; + /* configuration flags from bootloader */ + u32 bootloader_config_flags; + + /* Uart number used for console */ + u8 console_uart_num; +}; + +/** + * This function returns the system/board information as obtained + * by the bootloader. + * + * + * Returns Pointer to the boot information structure + * + */ + +struct cvmx_sysinfo *cvmx_sysinfo_get(void); + +#endif /* __CVMX_SYSINFO_H__ */ diff --git a/drivers/staging/octeon/cvmx-uctlx-defs.h b/drivers/staging/octeon/cvmx-uctlx-defs.h new file mode 100644 index 000000000000..d02a3579ae25 --- /dev/null +++ b/drivers/staging/octeon/cvmx-uctlx-defs.h @@ -0,0 +1,385 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2012 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_UCTLX_DEFS_H__ +#define __CVMX_UCTLX_DEFS_H__ + +#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) +#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) +#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull)) +#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull)) +#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull)) +#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull)) +#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull)) +#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull)) +#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull)) +#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull)) +#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull)) +#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull)) +#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) + +union cvmx_uctlx_bist_status { + u64 u64; + struct cvmx_uctlx_bist_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 data_bis:1; + u64 desc_bis:1; + u64 erbm_bis:1; + u64 orbm_bis:1; + u64 wrbm_bis:1; + u64 ppaf_bis:1; +#else + u64 ppaf_bis:1; + u64 wrbm_bis:1; + u64 orbm_bis:1; + u64 erbm_bis:1; + u64 desc_bis:1; + u64 data_bis:1; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_uctlx_clk_rst_ctl { + u64 u64; + struct cvmx_uctlx_clk_rst_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_25_63:39; + u64 clear_bist:1; + u64 start_bist:1; + u64 ehci_sm:1; + u64 ohci_clkcktrst:1; + u64 ohci_sm:1; + u64 ohci_susp_lgcy:1; + u64 app_start_clk:1; + u64 o_clkdiv_rst:1; + u64 h_clkdiv_byp:1; + u64 h_clkdiv_rst:1; + u64 h_clkdiv_en:1; + u64 o_clkdiv_en:1; + u64 h_div:4; + u64 p_refclk_sel:2; + u64 p_refclk_div:2; + u64 reserved_4_4:1; + u64 p_com_on:1; + u64 p_por:1; + u64 p_prst:1; + u64 hrst:1; +#else + u64 hrst:1; + u64 p_prst:1; + u64 p_por:1; + u64 p_com_on:1; + u64 reserved_4_4:1; + u64 p_refclk_div:2; + u64 p_refclk_sel:2; + u64 h_div:4; + u64 o_clkdiv_en:1; + u64 h_clkdiv_en:1; + u64 h_clkdiv_rst:1; + u64 h_clkdiv_byp:1; + u64 o_clkdiv_rst:1; + u64 app_start_clk:1; + u64 ohci_susp_lgcy:1; + u64 ohci_sm:1; + u64 ohci_clkcktrst:1; + u64 ehci_sm:1; + u64 start_bist:1; + u64 clear_bist:1; + u64 reserved_25_63:39; +#endif + } s; +}; + +union cvmx_uctlx_ehci_ctl { + u64 u64; + struct cvmx_uctlx_ehci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_20_63:44; + u64 desc_rbm:1; + u64 reg_nb:1; + u64 l2c_dc:1; + u64 l2c_bc:1; + u64 l2c_0pag:1; + u64 l2c_stt:1; + u64 l2c_buff_emod:2; + u64 l2c_desc_emod:2; + u64 inv_reg_a2:1; + u64 ehci_64b_addr_en:1; + u64 l2c_addr_msb:8; +#else + u64 l2c_addr_msb:8; + u64 ehci_64b_addr_en:1; + u64 inv_reg_a2:1; + u64 l2c_desc_emod:2; + u64 l2c_buff_emod:2; + u64 l2c_stt:1; + u64 l2c_0pag:1; + u64 l2c_bc:1; + u64 l2c_dc:1; + u64 reg_nb:1; + u64 desc_rbm:1; + u64 reserved_20_63:44; +#endif + } s; +}; + +union cvmx_uctlx_ehci_fla { + u64 u64; + struct cvmx_uctlx_ehci_fla_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_6_63:58; + u64 fla:6; +#else + u64 fla:6; + u64 reserved_6_63:58; +#endif + } s; +}; + +union cvmx_uctlx_erto_ctl { + u64 u64; + struct cvmx_uctlx_erto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 to_val:27; + u64 reserved_0_4:5; +#else + u64 reserved_0_4:5; + u64 to_val:27; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_uctlx_if_ena { + u64 u64; + struct cvmx_uctlx_if_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_1_63:63; + u64 en:1; +#else + u64 en:1; + u64 reserved_1_63:63; +#endif + } s; +}; + +union cvmx_uctlx_int_ena { + u64 u64; + struct cvmx_uctlx_int_ena_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ec_ovf_e:1; + u64 oc_ovf_e:1; + u64 wb_pop_e:1; + u64 wb_psh_f:1; + u64 cf_psh_f:1; + u64 or_psh_f:1; + u64 er_psh_f:1; + u64 pp_psh_f:1; +#else + u64 pp_psh_f:1; + u64 er_psh_f:1; + u64 or_psh_f:1; + u64 cf_psh_f:1; + u64 wb_psh_f:1; + u64 wb_pop_e:1; + u64 oc_ovf_e:1; + u64 ec_ovf_e:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_uctlx_int_reg { + u64 u64; + struct cvmx_uctlx_int_reg_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_8_63:56; + u64 ec_ovf_e:1; + u64 oc_ovf_e:1; + u64 wb_pop_e:1; + u64 wb_psh_f:1; + u64 cf_psh_f:1; + u64 or_psh_f:1; + u64 er_psh_f:1; + u64 pp_psh_f:1; +#else + u64 pp_psh_f:1; + u64 er_psh_f:1; + u64 or_psh_f:1; + u64 cf_psh_f:1; + u64 wb_psh_f:1; + u64 wb_pop_e:1; + u64 oc_ovf_e:1; + u64 ec_ovf_e:1; + u64 reserved_8_63:56; +#endif + } s; +}; + +union cvmx_uctlx_ohci_ctl { + u64 u64; + struct cvmx_uctlx_ohci_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_19_63:45; + u64 reg_nb:1; + u64 l2c_dc:1; + u64 l2c_bc:1; + u64 l2c_0pag:1; + u64 l2c_stt:1; + u64 l2c_buff_emod:2; + u64 l2c_desc_emod:2; + u64 inv_reg_a2:1; + u64 reserved_8_8:1; + u64 l2c_addr_msb:8; +#else + u64 l2c_addr_msb:8; + u64 reserved_8_8:1; + u64 inv_reg_a2:1; + u64 l2c_desc_emod:2; + u64 l2c_buff_emod:2; + u64 l2c_stt:1; + u64 l2c_0pag:1; + u64 l2c_bc:1; + u64 l2c_dc:1; + u64 reg_nb:1; + u64 reserved_19_63:45; +#endif + } s; +}; + +union cvmx_uctlx_orto_ctl { + u64 u64; + struct cvmx_uctlx_orto_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_32_63:32; + u64 to_val:24; + u64 reserved_0_7:8; +#else + u64 reserved_0_7:8; + u64 to_val:24; + u64 reserved_32_63:32; +#endif + } s; +}; + +union cvmx_uctlx_ppaf_wm { + u64 u64; + struct cvmx_uctlx_ppaf_wm_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_5_63:59; + u64 wm:5; +#else + u64 wm:5; + u64 reserved_5_63:59; +#endif + } s; +}; + +union cvmx_uctlx_uphy_ctl_status { + u64 u64; + struct cvmx_uctlx_uphy_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_10_63:54; + u64 bist_done:1; + u64 bist_err:1; + u64 hsbist:1; + u64 fsbist:1; + u64 lsbist:1; + u64 siddq:1; + u64 vtest_en:1; + u64 uphy_bist:1; + u64 bist_en:1; + u64 ate_reset:1; +#else + u64 ate_reset:1; + u64 bist_en:1; + u64 uphy_bist:1; + u64 vtest_en:1; + u64 siddq:1; + u64 lsbist:1; + u64 fsbist:1; + u64 hsbist:1; + u64 bist_err:1; + u64 bist_done:1; + u64 reserved_10_63:54; +#endif + } s; +}; + +union cvmx_uctlx_uphy_portx_ctl_status { + u64 u64; + struct cvmx_uctlx_uphy_portx_ctl_status_s { +#ifdef __BIG_ENDIAN_BITFIELD + u64 reserved_43_63:21; + u64 tdata_out:4; + u64 txbiststuffenh:1; + u64 txbiststuffen:1; + u64 dmpulldown:1; + u64 dppulldown:1; + u64 vbusvldext:1; + u64 portreset:1; + u64 txhsvxtune:2; + u64 txvreftune:4; + u64 txrisetune:1; + u64 txpreemphasistune:1; + u64 txfslstune:4; + u64 sqrxtune:3; + u64 compdistune:3; + u64 loop_en:1; + u64 tclk:1; + u64 tdata_sel:1; + u64 taddr_in:4; + u64 tdata_in:8; +#else + u64 tdata_in:8; + u64 taddr_in:4; + u64 tdata_sel:1; + u64 tclk:1; + u64 loop_en:1; + u64 compdistune:3; + u64 sqrxtune:3; + u64 txfslstune:4; + u64 txpreemphasistune:1; + u64 txrisetune:1; + u64 txvreftune:4; + u64 txhsvxtune:2; + u64 portreset:1; + u64 vbusvldext:1; + u64 dppulldown:1; + u64 dmpulldown:1; + u64 txbiststuffen:1; + u64 txbiststuffenh:1; + u64 tdata_out:4; + u64 reserved_43_63:21; +#endif + } s; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-wqe.h b/drivers/staging/octeon/cvmx-wqe.h new file mode 100644 index 000000000000..4dfe8e131d5c --- /dev/null +++ b/drivers/staging/octeon/cvmx-wqe.h @@ -0,0 +1,655 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * This header file defines the work queue entry (wqe) data structure. + * Since this is a commonly used structure that depends on structures + * from several hardware blocks, those definitions have been placed + * in this file to create a single point of definition of the wqe + * format. + * Data structures are still named according to the block that they + * relate to. + * + */ + +#ifndef __CVMX_WQE_H__ +#define __CVMX_WQE_H__ + +#include "cvmx-packet.h" + +#define OCT_TAG_TYPE_STRING(x) \ + (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ + (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ + (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ + "NULL_NULL"))) + +/** + * HW decode / err_code in work queue entry + */ +typedef union { + u64 u64; + + /* Use this struct if the hardware determines that the packet is IP */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* HW sets this to the number of buffers used by this packet */ + u64 bufs:8; + /* HW sets to the number of L2 bytes prior to the IP */ + u64 ip_offset:8; + /* set to 1 if we found DSA/VLAN in the L2 */ + u64 vlan_valid:1; + /* Set to 1 if the DSA/VLAN tag is stacked */ + u64 vlan_stacked:1; + u64 unassigned:1; + /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ + u64 vlan_cfi:1; + /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ + u64 vlan_id:12; + /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ + u64 pr:4; + u64 unassigned2:8; + /* the packet needs to be decompressed */ + u64 dec_ipcomp:1; + /* the packet is either TCP or UDP */ + u64 tcp_or_udp:1; + /* the packet needs to be decrypted (ESP or AH) */ + u64 dec_ipsec:1; + /* the packet is IPv6 */ + u64 is_v6:1; + + /* + * (rcv_error, not_IP, IP_exc, is_frag, L4_error, + * software, etc.). + */ + + /* + * reserved for software use, hardware will clear on + * packet creation. + */ + u64 software:1; + /* exceptional conditions below */ + /* the receive interface hardware detected an L4 error + * (only applies if !is_frag) (only applies if + * !rcv_error && !not_IP && !IP_exc && !is_frag) + * failure indicated in err_code below, decode: + * + * - 1 = Malformed L4 + * - 2 = L4 Checksum Error: the L4 checksum value is + * - 3 = UDP Length Error: The UDP length field would + * make the UDP data longer than what remains in + * the IP packet (as defined by the IP header + * length field). + * - 4 = Bad L4 Port: either the source or destination + * TCP/UDP port is 0. + * - 8 = TCP FIN Only: the packet is TCP and only the + * FIN flag set. + * - 9 = TCP No Flags: the packet is TCP and no flags + * are set. + * - 10 = TCP FIN RST: the packet is TCP and both FIN + * and RST are set. + * - 11 = TCP SYN URG: the packet is TCP and both SYN + * and URG are set. + * - 12 = TCP SYN RST: the packet is TCP and both SYN + * and RST are set. + * - 13 = TCP SYN FIN: the packet is TCP and both SYN + * and FIN are set. + */ + u64 L4_error:1; + /* set if the packet is a fragment */ + u64 is_frag:1; + /* the receive interface hardware detected an IP error + * / exception (only applies if !rcv_error && !not_IP) + * failure indicated in err_code below, decode: + * + * - 1 = Not IP: the IP version field is neither 4 nor + * 6. + * - 2 = IPv4 Header Checksum Error: the IPv4 header + * has a checksum violation. + * - 3 = IP Malformed Header: the packet is not long + * enough to contain the IP header. + * - 4 = IP Malformed: the packet is not long enough + * to contain the bytes indicated by the IP + * header. Pad is allowed. + * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 + * Hop Count field are zero. + * - 6 = IP Options + */ + u64 IP_exc:1; + /* + * Set if the hardware determined that the packet is a + * broadcast. + */ + u64 is_bcast:1; + /* + * St if the hardware determined that the packet is a + * multi-cast. + */ + u64 is_mcast:1; + /* + * Set if the packet may not be IP (must be zero in + * this case). + */ + u64 not_IP:1; + /* + * The receive interface hardware detected a receive + * error (must be zero in this case). + */ + u64 rcv_error:1; + /* lower err_code = first-level descriptor of the + * work */ + /* zero for packet submitted by hardware that isn't on + * the slow path */ + /* type is cvmx_pip_err_t */ + u64 err_code:8; +#else + u64 err_code:8; + u64 rcv_error:1; + u64 not_IP:1; + u64 is_mcast:1; + u64 is_bcast:1; + u64 IP_exc:1; + u64 is_frag:1; + u64 L4_error:1; + u64 software:1; + u64 is_v6:1; + u64 dec_ipsec:1; + u64 tcp_or_udp:1; + u64 dec_ipcomp:1; + u64 unassigned2:4; + u64 unassigned2a:4; + u64 pr:4; + u64 vlan_id:12; + u64 vlan_cfi:1; + u64 unassigned:1; + u64 vlan_stacked:1; + u64 vlan_valid:1; + u64 ip_offset:8; + u64 bufs:8; +#endif + } s; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 bufs:8; + u64 ip_offset:8; + u64 vlan_valid:1; + u64 vlan_stacked:1; + u64 unassigned:1; + u64 vlan_cfi:1; + u64 vlan_id:12; + u64 port:12; /* MAC/PIP port number. */ + u64 dec_ipcomp:1; + u64 tcp_or_udp:1; + u64 dec_ipsec:1; + u64 is_v6:1; + u64 software:1; + u64 L4_error:1; + u64 is_frag:1; + u64 IP_exc:1; + u64 is_bcast:1; + u64 is_mcast:1; + u64 not_IP:1; + u64 rcv_error:1; + u64 err_code:8; +#else + u64 err_code:8; + u64 rcv_error:1; + u64 not_IP:1; + u64 is_mcast:1; + u64 is_bcast:1; + u64 IP_exc:1; + u64 is_frag:1; + u64 L4_error:1; + u64 software:1; + u64 is_v6:1; + u64 dec_ipsec:1; + u64 tcp_or_udp:1; + u64 dec_ipcomp:1; + u64 port:12; + u64 vlan_id:12; + u64 vlan_cfi:1; + u64 unassigned:1; + u64 vlan_stacked:1; + u64 vlan_valid:1; + u64 ip_offset:8; + u64 bufs:8; +#endif + } s_cn68xx; + + /* use this to get at the 16 vlan bits */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 unused1:16; + u64 vlan:16; + u64 unused2:32; +#else + u64 unused2:32; + u64 vlan:16; + u64 unused1:16; + +#endif + } svlan; + + /* + * use this struct if the hardware could not determine that + * the packet is ip. + */ + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /* + * HW sets this to the number of buffers used by this + * packet. + */ + u64 bufs:8; + u64 unused:8; + /* set to 1 if we found DSA/VLAN in the L2 */ + u64 vlan_valid:1; + /* Set to 1 if the DSA/VLAN tag is stacked */ + u64 vlan_stacked:1; + u64 unassigned:1; + /* + * HW sets to the DSA/VLAN CFI flag (valid when + * vlan_valid) + */ + u64 vlan_cfi:1; + /* + * HW sets to the DSA/VLAN_ID field (valid when + * vlan_valid). + */ + u64 vlan_id:12; + /* + * Ring Identifier (if PCIe). Requires + * PIP_GBL_CTL[RING_EN]=1 + */ + u64 pr:4; + u64 unassigned2:12; + /* + * reserved for software use, hardware will clear on + * packet creation. + */ + u64 software:1; + u64 unassigned3:1; + /* + * set if the hardware determined that the packet is + * rarp. + */ + u64 is_rarp:1; + /* + * set if the hardware determined that the packet is + * arp + */ + u64 is_arp:1; + /* + * set if the hardware determined that the packet is a + * broadcast. + */ + u64 is_bcast:1; + /* + * set if the hardware determined that the packet is a + * multi-cast + */ + u64 is_mcast:1; + /* + * set if the packet may not be IP (must be one in + * this case) + */ + u64 not_IP:1; + /* The receive interface hardware detected a receive + * error. Failure indicated in err_code below, + * decode: + * + * - 1 = partial error: a packet was partially + * received, but internal buffering / bandwidth + * was not adequate to receive the entire + * packet. + * - 2 = jabber error: the RGMII packet was too large + * and is truncated. + * - 3 = overrun error: the RGMII packet is longer + * than allowed and had an FCS error. + * - 4 = oversize error: the RGMII packet is longer + * than allowed. + * - 5 = alignment error: the RGMII packet is not an + * integer number of bytes + * and had an FCS error (100M and 10M only). + * - 6 = fragment error: the RGMII packet is shorter + * than allowed and had an FCS error. + * - 7 = GMX FCS error: the RGMII packet had an FCS + * error. + * - 8 = undersize error: the RGMII packet is shorter + * than allowed. + * - 9 = extend error: the RGMII packet had an extend + * error. + * - 10 = length mismatch error: the RGMII packet had + * a length that did not match the length field + * in the L2 HDR. + * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII + * packet had one or more data reception errors + * (RXERR) or the SPI4 packet had one or more + * DIP4 errors. + * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII + * packet was not large enough to cover the + * skipped bytes or the SPI4 packet was + * terminated with an About EOPS. + * - 13 = RGMII nibble error/SPI4 Port NXA Error: the + * RGMII packet had a studder error (data not + * repeated - 10/100M only) or the SPI4 packet + * was sent to an NXA. + * - 16 = FCS error: a SPI4.2 packet had an FCS error. + * - 17 = Skip error: a packet was not large enough to + * cover the skipped bytes. + * - 18 = L2 header malformed: the packet is not long + * enough to contain the L2. + */ + + u64 rcv_error:1; + /* + * lower err_code = first-level descriptor of the + * work + */ + /* + * zero for packet submitted by hardware that isn't on + * the slow path + */ + /* type is cvmx_pip_err_t (union, so can't use directly */ + u64 err_code:8; +#else + u64 err_code:8; + u64 rcv_error:1; + u64 not_IP:1; + u64 is_mcast:1; + u64 is_bcast:1; + u64 is_arp:1; + u64 is_rarp:1; + u64 unassigned3:1; + u64 software:1; + u64 unassigned2:4; + u64 unassigned2a:8; + u64 pr:4; + u64 vlan_id:12; + u64 vlan_cfi:1; + u64 unassigned:1; + u64 vlan_stacked:1; + u64 vlan_valid:1; + u64 unused:8; + u64 bufs:8; +#endif + } snoip; + +} cvmx_pip_wqe_word2; + +union cvmx_pip_wqe_word0 { + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /** + * raw chksum result generated by the HW + */ + u16 hw_chksum; + /** + * Field unused by hardware - available for software + */ + u8 unused; + /** + * Next pointer used by hardware for list maintenance. + * May be written/read by HW before the work queue + * entry is scheduled to a PP (Only 36 bits used in + * Octeon 1) + */ + u64 next_ptr:40; +#else + u64 next_ptr:40; + u8 unused; + u16 hw_chksum; +#endif + } cn38xx; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 l4ptr:8; /* 56..63 */ + u64 unused0:8; /* 48..55 */ + u64 l3ptr:8; /* 40..47 */ + u64 l2ptr:8; /* 32..39 */ + u64 unused1:18; /* 14..31 */ + u64 bpid:6; /* 8..13 */ + u64 unused2:2; /* 6..7 */ + u64 pknd:6; /* 0..5 */ +#else + u64 pknd:6; /* 0..5 */ + u64 unused2:2; /* 6..7 */ + u64 bpid:6; /* 8..13 */ + u64 unused1:18; /* 14..31 */ + u64 l2ptr:8; /* 32..39 */ + u64 l3ptr:8; /* 40..47 */ + u64 unused0:8; /* 48..55 */ + u64 l4ptr:8; /* 56..63 */ +#endif + } cn68xx; +}; + +union cvmx_wqe_word0 { + u64 u64; + union cvmx_pip_wqe_word0 pip; +}; + +union cvmx_wqe_word1 { + u64 u64; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 len:16; + u64 varies:14; + /** + * the type of the tag (ORDERED, ATOMIC, NULL) + */ + u64 tag_type:2; + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 varies:14; + u64 len:16; +#endif + }; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + u64 len:16; + u64 zero_0:1; + /** + * HW sets this to what it thought the priority of + * the input packet was + */ + u64 qos:3; + + u64 zero_1:1; + /** + * the group that the work queue entry will be scheduled to + */ + u64 grp:6; + u64 zero_2:3; + u64 tag_type:2; + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 zero_2:3; + u64 grp:6; + u64 zero_1:1; + u64 qos:3; + u64 zero_0:1; + u64 len:16; +#endif + } cn68xx; + struct { +#ifdef __BIG_ENDIAN_BITFIELD + /** + * HW sets to the total number of bytes in the packet + */ + u64 len:16; + /** + * HW sets this to input physical port + */ + u64 ipprt:6; + + /** + * HW sets this to what it thought the priority of + * the input packet was + */ + u64 qos:3; + + /** + * the group that the work queue entry will be scheduled to + */ + u64 grp:4; + /** + * the type of the tag (ORDERED, ATOMIC, NULL) + */ + u64 tag_type:3; + /** + * the synchronization/ordering tag + */ + u64 tag:32; +#else + u64 tag:32; + u64 tag_type:2; + u64 zero_2:1; + u64 grp:4; + u64 qos:3; + u64 ipprt:6; + u64 len:16; +#endif + } cn38xx; +}; + +/** + * Work queue entry format + * + * must be 8-byte aligned + */ +struct cvmx_wqe { + /***************************************************************** + * WORD 0 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives + */ + union cvmx_wqe_word0 word0; + + /***************************************************************** + * WORD 1 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives + */ + union cvmx_wqe_word1 word1; + + /** + * WORD 2 HW WRITE: the following 64-bits are filled in by + * hardware when a packet arrives This indicates a variety of + * status and error conditions. + */ + cvmx_pip_wqe_word2 word2; + + /** + * Pointer to the first segment of the packet. + */ + union cvmx_buf_ptr packet_ptr; + + /** + * HW WRITE: octeon will fill in a programmable amount from the + * packet, up to (at most, but perhaps less) the amount + * needed to fill the work queue entry to 128 bytes + * + * If the packet is recognized to be IP, the hardware starts + * (except that the IPv4 header is padded for appropriate + * alignment) writing here where the IP header starts. If the + * packet is not recognized to be IP, the hardware starts + * writing the beginning of the packet here. + */ + u8 packet_data[96]; + + /** + * If desired, SW can make the work Q entry any length. For the + * purposes of discussion here, Assume 128B always, as this is all that + * the hardware deals with. + * + */ + +} CVMX_CACHE_LINE_ALIGNED; + +static inline int cvmx_wqe_get_port(struct cvmx_wqe *work) +{ + int port; + + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + port = work->word2.s_cn68xx.port; + else + port = work->word1.cn38xx.ipprt; + + return port; +} + +static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port) +{ + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + work->word2.s_cn68xx.port = port; + else + work->word1.cn38xx.ipprt = port; +} + +static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work) +{ + int grp; + + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + grp = work->word1.cn68xx.grp; + else + grp = work->word1.cn38xx.grp; + + return grp; +} + +static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp) +{ + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + work->word1.cn68xx.grp = grp; + else + work->word1.cn38xx.grp = grp; +} + +static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work) +{ + int qos; + + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + qos = work->word1.cn68xx.qos; + else + qos = work->word1.cn38xx.qos; + + return qos; +} + +static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos) +{ + if (octeon_has_feature(OCTEON_FEATURE_CN68XX_WQE)) + work->word1.cn68xx.qos = qos; + else + work->word1.cn38xx.qos = qos; +} + +#endif /* __CVMX_WQE_H__ */ diff --git a/drivers/staging/octeon/cvmx.h b/drivers/staging/octeon/cvmx.h new file mode 100644 index 000000000000..ba4c0d470788 --- /dev/null +++ b/drivers/staging/octeon/cvmx.h @@ -0,0 +1,496 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2017 Cavium, Inc. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_H__ +#define __CVMX_H__ + +#include +#include +#include + +enum cvmx_mips_space { + CVMX_MIPS_SPACE_XKSEG = 3LL, + CVMX_MIPS_SPACE_XKPHYS = 2LL, + CVMX_MIPS_SPACE_XSSEG = 1LL, + CVMX_MIPS_SPACE_XUSEG = 0LL +}; + +/* These macros for use when using 32 bit pointers. */ +#define CVMX_MIPS32_SPACE_KSEG0 1l +#define CVMX_ADD_SEG32(segment, add) \ + (((int32_t)segment << 31) | (int32_t)(add)) + +#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS + +/* These macros simplify the process of creating common IO addresses */ +#define CVMX_ADD_SEG(segment, add) \ + ((((u64)segment) << 62) | (add)) +#ifndef CVMX_ADD_IO_SEG +#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) +#endif + +#include "cvmx-asm.h" +#include "cvmx-packet.h" +#include "cvmx-sysinfo.h" + +#include "cvmx-ciu-defs.h" +#include "cvmx-ciu3-defs.h" +#include "cvmx-gpio-defs.h" +#include "cvmx-iob-defs.h" +#include "cvmx-ipd-defs.h" +#include "cvmx-l2c-defs.h" +#include "cvmx-l2d-defs.h" +#include "cvmx-l2t-defs.h" +#include "cvmx-led-defs.h" +#include "cvmx-mio-defs.h" +#include "cvmx-pow-defs.h" + +#include "cvmx-bootinfo.h" +#include "cvmx-bootmem.h" +#include "cvmx-l2c.h" + +#ifndef CVMX_ENABLE_DEBUG_PRINTS +#define CVMX_ENABLE_DEBUG_PRINTS 1 +#endif + +#if CVMX_ENABLE_DEBUG_PRINTS +#define cvmx_dprintf printk +#else +#define cvmx_dprintf(...) {} +#endif + +#define CVMX_MAX_CORES (16) +#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ +#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ +#define CVMX_CACHE_LINE_ALIGNED __aligned(CVMX_CACHE_LINE_SIZE) +#define CAST64(v) ((long long)(long)(v)) +#define CASTPTR(type, v) ((type *)(long)(v)) + +/* + * Returns processor ID, different Linux and simple exec versions + * provided in the cvmx-app-init*.c files. + */ +static inline u32 cvmx_get_proc_id(void) __pure; +static inline u32 cvmx_get_proc_id(void) +{ + u32 id; + + asm("mfc0 %0, $15,0" : "=r"(id)); + return id; +} + +/* turn the variable name into a string */ +#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) +#define CVMX_TMP_STR2(x) #x + +/** + * Builds a bit mask given the required size in bits. + * + * @bits: Number of bits in the mask + * Returns The mask + */ static inline u64 cvmx_build_mask(u64 bits) +{ + return ~((~0x0ull) << bits); +} + +/** + * Builds a memory address for I/O based on the Major and Sub DID. + * + * @major_did: 5 bit major did + * @sub_did: 3 bit sub did + * Returns I/O base address + */ +static inline u64 cvmx_build_io_address(u64 major_did, + u64 sub_did) +{ + return (0x1ull << 48) | (major_did << 43) | (sub_did << 40); +} + +/** + * Perform mask and shift to place the supplied value into + * the supplied bit rage. + * + * Example: cvmx_build_bits(39,24,value) + * 
+	* 6	   5	   4	   3	   3	   2	   1
+	* 3	   5	   7	   9	   1	   3	   5	   7	  0
+	* +-------+-------+-------+-------+-------+-------+-------+------+
+	* 000000000000000000000000___________value000000000000000000000000
+	*
+ * + * @high_bit: Highest bit value can occupy (inclusive) 0-63 + * @low_bit: Lowest bit value can occupy inclusive 0-high_bit + * @value: Value to use + * Returns Value masked and shifted + */ +static inline u64 cvmx_build_bits(u64 high_bit, + u64 low_bit, u64 value) +{ + return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; +} + +/** + * Convert a memory pointer (void*) into a hardware compatible + * memory address (phys_addr_t). Octeon hardware widgets don't + * understand logical addresses. + * + * @ptr: C style memory pointer + * Returns Hardware physical address + */ +static inline phys_addr_t cvmx_ptr_to_phys(void *ptr) +{ + if (sizeof(void *) == 8) { + /* + * We're running in 64 bit mode. Normally this means + * that we can use 40 bits of address space (the + * hardware limit). Unfortunately there is one case + * were we need to limit this to 30 bits, sign + * extended 32 bit. Although these are 64 bits wide, + * only 30 bits can be used. + */ + if ((CAST64(ptr) >> 62) == 3) + return CAST64(ptr) & cvmx_build_mask(30); + else + return CAST64(ptr) & cvmx_build_mask(40); + } else { + return (long)(ptr) & 0x1fffffff; + } +} + +/** + * Convert a hardware physical address (u64) into a + * memory pointer (void *). + * + * @physical_address: + * Hardware physical address to memory + * Returns Pointer to memory + */ +static inline void *cvmx_phys_to_ptr(u64 physical_address) +{ + if (sizeof(void *) == 8) { + /* Just set the top bit, avoiding any TLB ugliness */ + return CASTPTR(void, + CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, + physical_address)); + } else { + return CASTPTR(void, + CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, + physical_address)); + } +} + +/* The following #if controls the definition of the macro + CVMX_BUILD_WRITE64. This macro is used to build a store operation to + a full 64bit address. With a 64bit ABI, this can be done with a simple + pointer access. 32bit ABIs require more complicated assembly */ + +/* We have a full 64bit ABI. Writing to a 64bit address can be done with + a simple volatile pointer */ +#define CVMX_BUILD_WRITE64(TYPE, ST) \ +static inline void cvmx_write64_##TYPE(u64 addr, TYPE##_t val) \ +{ \ + *CASTPTR(volatile TYPE##_t, addr) = val; \ +} + +/* The following #if controls the definition of the macro + CVMX_BUILD_READ64. This macro is used to build a load operation from + a full 64bit address. With a 64bit ABI, this can be done with a simple + pointer access. 32bit ABIs require more complicated assembly */ + +/* We have a full 64bit ABI. Writing to a 64bit address can be done with + a simple volatile pointer */ +#define CVMX_BUILD_READ64(TYPE, LT) \ +static inline TYPE##_t cvmx_read64_##TYPE(u64 addr) \ +{ \ + return *CASTPTR(volatile TYPE##_t, addr); \ +} + +/* The following defines 8 functions for writing to a 64bit address. Each + takes two arguments, the address and the value to write. + cvmx_write64_int64 cvmx_write64_uint64 + cvmx_write64_int32 cvmx_write64_uint32 + cvmx_write64_int16 cvmx_write64_uint16 + cvmx_write64_int8 cvmx_write64_uint8 */ +CVMX_BUILD_WRITE64(int64, "sd"); +CVMX_BUILD_WRITE64(int32, "sw"); +CVMX_BUILD_WRITE64(int16, "sh"); +CVMX_BUILD_WRITE64(int8, "sb"); +CVMX_BUILD_WRITE64(uint64, "sd"); +CVMX_BUILD_WRITE64(uint32, "sw"); +CVMX_BUILD_WRITE64(uint16, "sh"); +CVMX_BUILD_WRITE64(uint8, "sb"); +#define cvmx_write64 cvmx_write64_uint64 + +/* The following defines 8 functions for reading from a 64bit address. Each + takes the address as the only argument + cvmx_read64_int64 cvmx_read64_uint64 + cvmx_read64_int32 cvmx_read64_uint32 + cvmx_read64_int16 cvmx_read64_uint16 + cvmx_read64_int8 cvmx_read64_uint8 */ +CVMX_BUILD_READ64(int64, "ld"); +CVMX_BUILD_READ64(int32, "lw"); +CVMX_BUILD_READ64(int16, "lh"); +CVMX_BUILD_READ64(int8, "lb"); +CVMX_BUILD_READ64(uint64, "ld"); +CVMX_BUILD_READ64(uint32, "lw"); +CVMX_BUILD_READ64(uint16, "lhu"); +CVMX_BUILD_READ64(uint8, "lbu"); +#define cvmx_read64 cvmx_read64_uint64 + +static inline void cvmx_write_csr(u64 csr_addr, u64 val) +{ + cvmx_write64(csr_addr, val); + + /* + * Perform an immediate read after every write to an RSL + * register to force the write to complete. It doesn't matter + * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT + * because it is fast and harmless. + */ + if (((csr_addr >> 40) & 0x7ffff) == (0x118)) + cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); +} + +static inline void cvmx_writeq_csr(void __iomem *csr_addr, u64 val) +{ + cvmx_write_csr((__force u64)csr_addr, val); +} + +static inline void cvmx_write_io(u64 io_addr, u64 val) +{ + cvmx_write64(io_addr, val); +} + +static inline u64 cvmx_read_csr(u64 csr_addr) +{ + u64 val = cvmx_read64(csr_addr); + return val; +} + +static inline u64 cvmx_readq_csr(void __iomem *csr_addr) +{ + return cvmx_read_csr((__force u64)csr_addr); +} + +static inline void cvmx_send_single(u64 data) +{ + const u64 CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull; + + cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data); +} + +static inline void cvmx_read_csr_async(u64 scraddr, u64 csr_addr) +{ + union { + u64 u64; + struct { + u64 scraddr:8; + u64 len:8; + u64 addr:48; + } s; + } addr; + addr.u64 = csr_addr; + addr.s.scraddr = scraddr >> 3; + addr.s.len = 1; + cvmx_send_single(addr.u64); +} + +/* Return true if Octeon is CN38XX pass 1 */ +static inline int cvmx_octeon_is_pass1(void) +{ +#if OCTEON_IS_COMMON_BINARY() + return 0; /* Pass 1 isn't supported for common binaries */ +#else +/* Now that we know we're built for a specific model, only check CN38XX */ +#if OCTEON_IS_MODEL(OCTEON_CN38XX) + return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1; +#else + return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */ +#endif +#endif +} + +static inline unsigned int cvmx_get_core_num(void) +{ + unsigned int core_num; + + CVMX_RDHWRNV(core_num, 0); + return core_num; +} + +/* Maximum # of bits to define core in node */ +#define CVMX_NODE_NO_SHIFT 7 +#define CVMX_NODE_MASK 0x3 +static inline unsigned int cvmx_get_node_num(void) +{ + unsigned int core_num = cvmx_get_core_num(); + + return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK; +} + +static inline unsigned int cvmx_get_local_core_num(void) +{ + return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1); +} + +#define CVMX_NODE_BITS (2) /* Number of bits to define a node */ +#define CVMX_MAX_NODES BIT(CVMX_NODE_BITS) +#define CVMX_NODE_IO_SHIFT (36) +#define CVMX_NODE_MEM_SHIFT (40) +#define CVMX_NODE_IO_MASK ((u64)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT) + +static inline void cvmx_write_csr_node(u64 node, u64 csr_addr, + u64 val) +{ + u64 composite_csr_addr, node_addr; + + node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT; + composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr; + + cvmx_write64_uint64(composite_csr_addr, val); + if (((csr_addr >> 40) & 0x7ffff) == (0x118)) + cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr); +} + +static inline u64 cvmx_read_csr_node(u64 node, u64 csr_addr) +{ + u64 node_addr; + + node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | + (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT; + return cvmx_read_csr(node_addr); +} + +/** + * Returns the number of bits set in the provided value. + * Simple wrapper for POP instruction. + * + * @val: 32 bit value to count set bits in + * + * Returns Number of bits set + */ +static inline u32 cvmx_pop(u32 val) +{ + u32 pop; + + CVMX_POP(pop, val); + return pop; +} + +/** + * Returns the number of bits set in the provided value. + * Simple wrapper for DPOP instruction. + * + * @val: 64 bit value to count set bits in + * + * Returns Number of bits set + */ +static inline int cvmx_dpop(u64 val) +{ + int pop; + + CVMX_DPOP(pop, val); + return pop; +} + +/** + * Provide current cycle counter as a return value + * + * Returns current cycle counter + */ + +static inline u64 cvmx_get_cycle(void) +{ + u64 cycle; + + CVMX_RDHWR(cycle, 31); + return cycle; +} + +/** + * Reads a chip global cycle counter. This counts CPU cycles since + * chip reset. The counter is 64 bit. + * This register does not exist on CN38XX pass 1 silicion + * + * Returns Global chip cycle count since chip reset. + */ +static inline u64 cvmx_get_cycle_global(void) +{ + if (cvmx_octeon_is_pass1()) + return 0; + else + return cvmx_read64(CVMX_IPD_CLK_COUNT); +} + +/** + * This macro spins on a field waiting for it to reach a value. It + * is common in code to need to wait for a specific field in a CSR + * to match a specific value. Conceptually this macro expands to: + * + * 1) read csr at "address" with a csr typedef of "type" + * 2) Check if ("type".s."field" "op" "value") + * 3) If #2 isn't true loop to #1 unless too much time has passed. + */ +#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\ + ( \ +{ \ + int result; \ + do { \ + u64 done = cvmx_get_cycle() + (u64)timeout_usec * \ + cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \ + type c; \ + while (1) { \ + c.u64 = cvmx_read_csr(address); \ + if ((c.s.field) op(value)) { \ + result = 0; \ + break; \ + } else if (cvmx_get_cycle() > done) { \ + result = -1; \ + break; \ + } else \ + __delay(100); \ + } \ + } while (0); \ + result; \ +}) + +/***************************************************************************/ + +/* Return the number of cores available in the chip */ +static inline u32 cvmx_octeon_num_cores(void) +{ + u64 ciu_fuse_reg; + u64 ciu_fuse; + + if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) + ciu_fuse_reg = CVMX_CIU3_FUSE; + else + ciu_fuse_reg = CVMX_CIU_FUSE; + ciu_fuse = cvmx_read_csr(ciu_fuse_reg); + return cvmx_dpop(ciu_fuse); +} + +#endif /* __CVMX_H__ */ diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index c060374a3da2..554f731c6210 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -1,23 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ /* - * A few defines are used to control the operation of this driver: - * USE_ASYNC_IOBDMA - * Use asynchronous IO access to hardware. This uses Octeon's asynchronous - * IOBDMAs to issue IO accesses without stalling. Set this to zero - * to disable this. Note that IOBDMAs require CVMSEG. - * REUSE_SKBUFFS_WITHOUT_FREE - * Allows the TX path to free an skbuff into the FPA hardware pool. This - * can significantly improve performance for forwarding and bridging, but - * may be somewhat dangerous. Checks are made, but if any buffer is reused - * without the proper Linux cleanup, the networking stack may have very - * bizarre bugs. - */ + * A few defines are used to control the operation of this driver: + * USE_ASYNC_IOBDMA + * Use asynchronous IO access to hardware. This uses Octeon's asynchronous + * IOBDMAs to issue IO accesses without stalling. Set this to zero + * to disable this. Note that IOBDMAs require CVMSEG. + * REUSE_SKBUFFS_WITHOUT_FREE + * Allows the TX path to free an skbuff into the FPA hardware pool. This + * can significantly improve performance for forwarding and bridging, but + * may be somewhat dangerous. Checks are made, but if any buffer is reused + * without the proper Linux cleanup, the networking stack may have very + * bizarre bugs. + */ #ifndef __ETHERNET_DEFINES_H__ #define __ETHERNET_DEFINES_H__ diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 211423059e30..e5669407700d 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include @@ -44,13 +44,13 @@ const struct ethtool_ops cvm_oct_ethtool_ops = { }; /** - * cvm_oct_ioctl - IOCTL support for PHY control - * @dev: Device to change - * @rq: the request - * @cmd: the command - * - * Returns Zero on success - */ + * cvm_oct_ioctl - IOCTL support for PHY control + * @dev: Device to change + * @rq: the request + * @cmd: the command + * + * Returns Zero on success + */ int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { if (!netif_running(dev)) @@ -128,12 +128,12 @@ int cvm_oct_common_stop(struct net_device *dev) } /** - * cvm_oct_phy_setup_device - setup the PHY - * - * @dev: Device to setup - * - * Returns Zero on success, negative on failure - */ + * cvm_oct_phy_setup_device - setup the PHY + * + * @dev: Device to setup + * + * Returns Zero on success, negative on failure + */ int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h index 7f6716e3fad4..0a8060dd9268 100644 --- a/drivers/staging/octeon/ethernet-mdio.h +++ b/drivers/staging/octeon/ethernet-mdio.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 532594957ebc..43abf428db99 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2010 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2010 Cavium Networks + */ #include #include @@ -14,13 +14,13 @@ #include "ethernet-defines.h" /** - * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs - * @pool: Pool to allocate an skbuff for - * @size: Size of the buffer needed for the pool - * @elements: Number of buffers to allocate - * - * Returns the actual number of buffers allocated. - */ + * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs + * @pool: Pool to allocate an skbuff for + * @size: Size of the buffer needed for the pool + * @elements: Number of buffers to allocate + * + * Returns the actual number of buffers allocated. + */ static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) { int freed = elements; @@ -39,11 +39,11 @@ static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) } /** - * cvm_oct_free_hw_skbuff- free hardware pool skbuffs - * @pool: Pool to allocate an skbuff for - * @size: Size of the buffer needed for the pool - * @elements: Number of buffers to allocate - */ + * cvm_oct_free_hw_skbuff- free hardware pool skbuffs + * @pool: Pool to allocate an skbuff for + * @size: Size of the buffer needed for the pool + * @elements: Number of buffers to allocate + */ static void cvm_oct_free_hw_skbuff(int pool, int size, int elements) { char *memory; @@ -67,13 +67,13 @@ static void cvm_oct_free_hw_skbuff(int pool, int size, int elements) } /** - * cvm_oct_fill_hw_memory - fill a hardware pool with memory. - * @pool: Pool to populate - * @size: Size of each buffer in the pool - * @elements: Number of buffers to allocate - * - * Returns the actual number of buffers allocated. - */ + * cvm_oct_fill_hw_memory - fill a hardware pool with memory. + * @pool: Pool to populate + * @size: Size of each buffer in the pool + * @elements: Number of buffers to allocate + * + * Returns the actual number of buffers allocated. + */ static int cvm_oct_fill_hw_memory(int pool, int size, int elements) { char *memory; @@ -106,11 +106,11 @@ static int cvm_oct_fill_hw_memory(int pool, int size, int elements) } /** - * cvm_oct_free_hw_memory - Free memory allocated by cvm_oct_fill_hw_memory - * @pool: FPA pool to free - * @size: Size of each buffer in the pool - * @elements: Number of buffers that should be in the pool - */ + * cvm_oct_free_hw_memory - Free memory allocated by cvm_oct_fill_hw_memory + * @pool: FPA pool to free + * @size: Size of each buffer in the pool + * @elements: Number of buffers that should be in the pool + */ static void cvm_oct_free_hw_memory(int pool, int size, int elements) { char *memory; diff --git a/drivers/staging/octeon/ethernet-mem.h b/drivers/staging/octeon/ethernet-mem.h index 692dcdb7154d..789cf58a3163 100644 --- a/drivers/staging/octeon/ethernet-mem.h +++ b/drivers/staging/octeon/ethernet-mem.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ int cvm_oct_mem_fill_fpa(int pool, int size, int elements); void cvm_oct_mem_empty_fpa(int pool, int size, int elements); diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index 0c4fac31540a..42295017c3f1 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index 965330eec80a..c495b559c2d7 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2010 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2010 Cavium Networks + */ #include #include @@ -38,13 +38,13 @@ static struct oct_rx_group { } oct_rx_group[16]; /** - * cvm_oct_do_interrupt - interrupt handler. - * @irq: Interrupt number. - * @napi_id: Cookie to identify the NAPI instance. - * - * The interrupt occurs whenever the POW has packets in our group. - * - */ + * cvm_oct_do_interrupt - interrupt handler. + * @irq: Interrupt number. + * @napi_id: Cookie to identify the NAPI instance. + * + * The interrupt occurs whenever the POW has packets in our group. + * + */ static irqreturn_t cvm_oct_do_interrupt(int irq, void *napi_id) { /* Disable the IRQ and start napi_poll. */ @@ -55,11 +55,11 @@ static irqreturn_t cvm_oct_do_interrupt(int irq, void *napi_id) } /** - * cvm_oct_check_rcv_error - process receive errors - * @work: Work queue entry pointing to the packet. - * - * Returns Non-zero if the packet can be dropped, zero otherwise. - */ + * cvm_oct_check_rcv_error - process receive errors + * @work: Work queue entry pointing to the packet. + * + * Returns Non-zero if the packet can be dropped, zero otherwise. + */ static inline int cvm_oct_check_rcv_error(struct cvmx_wqe *work) { int port; @@ -403,12 +403,12 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int budget) } /** - * cvm_oct_napi_poll - the NAPI poll function. - * @napi: The NAPI instance. - * @budget: Maximum number of packets to receive. - * - * Returns the number of packets processed. - */ + * cvm_oct_napi_poll - the NAPI poll function. + * @napi: The NAPI instance. + * @budget: Maximum number of packets to receive. + * + * Returns the number of packets processed. + */ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget) { struct oct_rx_group *rx_group = container_of(napi, struct oct_rx_group, @@ -427,11 +427,11 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget) #ifdef CONFIG_NET_POLL_CONTROLLER /** - * cvm_oct_poll_controller - poll for receive packets - * device. - * - * @dev: Device to poll. Unused - */ + * cvm_oct_poll_controller - poll for receive packets + * device. + * + * @dev: Device to poll. Unused + */ void cvm_oct_poll_controller(struct net_device *dev) { int i; diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h index ff6482fa20d6..2cbe45d2e728 100644 --- a/drivers/staging/octeon/ethernet-rx.h +++ b/drivers/staging/octeon/ethernet-rx.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ void cvm_oct_poll_controller(struct net_device *dev); void cvm_oct_rx_initialize(void); diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index d7fbd9159302..0442f0390d68 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index 699c98c5ec13..e131beb84008 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index f5bbedac6a65..7c6cb51d586f 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2010 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2010 Cavium Networks + */ #include #include @@ -30,12 +30,12 @@ #define CVM_OCT_SKB_CB(skb) ((u64 *)((skb)->cb)) /* - * You can define GET_SKBUFF_QOS() to override how the skbuff output - * function determines which output queue is used. The default - * implementation always uses the base queue for the port. If, for - * example, you wanted to use the skb->priority field, define - * GET_SKBUFF_QOS as: #define GET_SKBUFF_QOS(skb) ((skb)->priority) - */ + * You can define GET_SKBUFF_QOS() to override how the skbuff output + * function determines which output queue is used. The default + * implementation always uses the base queue for the port. If, for + * example, you wanted to use the skb->priority field, define + * GET_SKBUFF_QOS as: #define GET_SKBUFF_QOS(skb) ((skb)->priority) + */ #ifndef GET_SKBUFF_QOS #define GET_SKBUFF_QOS(skb) 0 #endif @@ -117,12 +117,12 @@ static void cvm_oct_free_tx_skbs(struct net_device *dev) } /** - * cvm_oct_xmit - transmit a packet - * @skb: Packet to send - * @dev: Device info structure - * - * Returns Always returns NETDEV_TX_OK - */ + * cvm_oct_xmit - transmit a packet + * @skb: Packet to send + * @dev: Device info structure + * + * Returns Always returns NETDEV_TX_OK + */ netdev_tx_t cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) { union cvmx_pko_command_word0 pko_command; @@ -498,11 +498,11 @@ netdev_tx_t cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) } /** - * cvm_oct_xmit_pow - transmit a packet to the POW - * @skb: Packet to send - * @dev: Device info structure - * Returns Always returns zero - */ + * cvm_oct_xmit_pow - transmit a packet to the POW + * @skb: Packet to send + * @dev: Device info structure + * Returns Always returns zero + */ netdev_tx_t cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); @@ -610,10 +610,10 @@ netdev_tx_t cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) } /** - * cvm_oct_tx_shutdown_dev - free all skb that are currently queued for TX. - * @dev: Device being shutdown - * - */ + * cvm_oct_tx_shutdown_dev - free all skb that are currently queued for TX. + * @dev: Device being shutdown + * + */ void cvm_oct_tx_shutdown_dev(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); diff --git a/drivers/staging/octeon/ethernet-tx.h b/drivers/staging/octeon/ethernet-tx.h index 6c524668f65a..5e07a7f70877 100644 --- a/drivers/staging/octeon/ethernet-tx.h +++ b/drivers/staging/octeon/ethernet-tx.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ netdev_tx_t cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev); netdev_tx_t cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev); diff --git a/drivers/staging/octeon/ethernet-util.h b/drivers/staging/octeon/ethernet-util.h index 2af83a12ca78..7beb09cab8be 100644 --- a/drivers/staging/octeon/ethernet-util.h +++ b/drivers/staging/octeon/ethernet-util.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ /** - * cvm_oct_get_buffer_ptr - convert packet data address to pointer - * @packet_ptr: Packet data hardware address - * - * Returns Packet buffer pointer - */ + * cvm_oct_get_buffer_ptr - convert packet data address to pointer + * @packet_ptr: Packet data hardware address + * + * Returns Packet buffer pointer + */ static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr) { return cvmx_phys_to_ptr(((packet_ptr.s.addr >> 7) - packet_ptr.s.back) @@ -18,11 +18,11 @@ static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr) } /** - * INTERFACE - convert IPD port to logical interface - * @ipd_port: Port to check - * - * Returns Logical interface - */ + * INTERFACE - convert IPD port to logical interface + * @ipd_port: Port to check + * + * Returns Logical interface + */ static inline int INTERFACE(int ipd_port) { int interface; @@ -36,11 +36,11 @@ static inline int INTERFACE(int ipd_port) } /** - * INDEX - convert IPD/PKO port number to the port's interface index - * @ipd_port: Port to check - * - * Returns Index into interface port list - */ + * INDEX - convert IPD/PKO port number to the port's interface index + * @ipd_port: Port to check + * + * Returns Index into interface port list + */ static inline int INDEX(int ipd_port) { return cvmx_helper_get_interface_index_num(ipd_port); diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index eadb74fc14c8..01bc85d713c5 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2007 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2007 Cavium Networks + */ #include #include @@ -90,16 +90,16 @@ MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); int pow_receive_groups; /* - * cvm_oct_poll_queue_stopping - flag to indicate polling should stop. - * - * Set to one right before cvm_oct_poll_queue is destroyed. - */ + * cvm_oct_poll_queue_stopping - flag to indicate polling should stop. + * + * Set to one right before cvm_oct_poll_queue is destroyed. + */ atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0); /* - * Array of every ethernet device owned by this driver indexed by - * the ipd input port number. - */ + * Array of every ethernet device owned by this driver indexed by + * the ipd input port number. + */ struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; u64 cvm_oct_tx_poll_interval; @@ -165,12 +165,12 @@ static void cvm_oct_configure_common_hw(void) } /** - * cvm_oct_free_work- Free a work queue entry - * - * @work_queue_entry: Work queue entry to free - * - * Returns Zero on success, Negative on failure. - */ + * cvm_oct_free_work- Free a work queue entry + * + * @work_queue_entry: Work queue entry to free + * + * Returns Zero on success, Negative on failure. + */ int cvm_oct_free_work(void *work_queue_entry) { struct cvmx_wqe *work = work_queue_entry; @@ -194,11 +194,11 @@ int cvm_oct_free_work(void *work_queue_entry) EXPORT_SYMBOL(cvm_oct_free_work); /** - * cvm_oct_common_get_stats - get the low level ethernet statistics - * @dev: Device to get the statistics from - * - * Returns Pointer to the statistics - */ + * cvm_oct_common_get_stats - get the low level ethernet statistics + * @dev: Device to get the statistics from + * + * Returns Pointer to the statistics + */ static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev) { cvmx_pip_port_status_t rx_status; @@ -229,12 +229,12 @@ static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev) } /** - * cvm_oct_common_change_mtu - change the link MTU - * @dev: Device to change - * @new_mtu: The new MTU - * - * Returns Zero on success - */ + * cvm_oct_common_change_mtu - change the link MTU + * @dev: Device to change + * @new_mtu: The new MTU + * + * Returns Zero on success + */ static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu) { struct octeon_ethernet *priv = netdev_priv(dev); @@ -285,9 +285,9 @@ static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu) } /** - * cvm_oct_common_set_multicast_list - set the multicast list - * @dev: Device to work on - */ + * cvm_oct_common_set_multicast_list - set the multicast list + * @dev: Device to work on + */ static void cvm_oct_common_set_multicast_list(struct net_device *dev) { union cvmx_gmxx_prtx_cfg gmx_cfg; @@ -383,12 +383,12 @@ static int cvm_oct_set_mac_filter(struct net_device *dev) } /** - * cvm_oct_common_set_mac_address - set the hardware MAC address for a device - * @dev: The device in question. - * @addr: Socket address. - * - * Returns Zero on success - */ + * cvm_oct_common_set_mac_address - set the hardware MAC address for a device + * @dev: The device in question. + * @addr: Socket address. + * + * Returns Zero on success + */ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) { int r = eth_mac_addr(dev, addr); @@ -399,11 +399,11 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) } /** - * cvm_oct_common_init - per network device initialization - * @dev: Device to initialize - * - * Returns Zero on success - */ + * cvm_oct_common_init - per network device initialization + * @dev: Device to initialize + * + * Returns Zero on success + */ int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index a6140705706f..3ad51e88317d 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is based on code from OCTEON SDK by Cavium Networks. - * - * Copyright (c) 2003-2010 Cavium Networks - */ + * This file is based on code from OCTEON SDK by Cavium Networks. + * + * Copyright (c) 2003-2010 Cavium Networks + */ /* - * External interface for the Cavium Octeon ethernet driver. - */ + * External interface for the Cavium Octeon ethernet driver. + */ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H @@ -16,25 +16,25 @@ #ifdef CONFIG_CAVIUM_OCTEON_SOC -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "octeon.h" + +#include "cvmx-asxx-defs.h" +#include "cvmx-config.h" +#include "cvmx-fau.h" +#include "cvmx-gmxx-defs.h" +#include "cvmx-helper.h" +#include "cvmx-helper-util.h" +#include "cvmx-ipd.h" +#include "cvmx-ipd-defs.h" +#include "cvmx-npi-defs.h" +#include "cvmx-pip.h" +#include "cvmx-pko.h" +#include "cvmx-pow.h" +#include "cvmx-scratch.h" +#include "cvmx-spi.h" +#include "cvmx-spxx-defs.h" +#include "cvmx-stxx-defs.h" +#include "cvmx-wqe.h" #else @@ -43,9 +43,9 @@ #endif /** - * This is the definition of the Ethernet driver's private - * driver state stored in netdev_priv(dev). - */ + * This is the definition of the Ethernet driver's private + * driver state stored in netdev_priv(dev). + */ struct octeon_ethernet { /* PKO hardware output port */ int port; diff --git a/drivers/staging/octeon/octeon-feature.h b/drivers/staging/octeon/octeon-feature.h new file mode 100644 index 000000000000..2ca0356658a4 --- /dev/null +++ b/drivers/staging/octeon/octeon-feature.h @@ -0,0 +1,212 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * File defining checks for different Octeon features. + */ + +#ifndef __OCTEON_FEATURE_H__ +#define __OCTEON_FEATURE_H__ +#include "cvmx-mio-defs.h" +#include "cvmx-rnm-defs.h" + +enum octeon_feature { + /* CN68XX uses port kinds for packet interface */ + OCTEON_FEATURE_PKND, + /* CN68XX has different fields in word0 - word2 */ + OCTEON_FEATURE_CN68XX_WQE, + /* + * Octeon models in the CN5XXX family and higher support + * atomic add instructions to memory (saa/saad). + */ + OCTEON_FEATURE_SAAD, + /* Does this Octeon support the ZIP offload engine? */ + OCTEON_FEATURE_ZIP, + OCTEON_FEATURE_DORM_CRYPTO, + /* Does this Octeon support PCI express? */ + OCTEON_FEATURE_PCIE, + /* Does this Octeon support SRIOs */ + OCTEON_FEATURE_SRIO, + /* Does this Octeon support Interlaken */ + OCTEON_FEATURE_ILK, + /* Some Octeon models support internal memory for storing + * cryptographic keys */ + OCTEON_FEATURE_KEY_MEMORY, + /* Octeon has a LED controller for banks of external LEDs */ + OCTEON_FEATURE_LED_CONTROLLER, + /* Octeon has a trace buffer */ + OCTEON_FEATURE_TRA, + /* Octeon has a management port */ + OCTEON_FEATURE_MGMT_PORT, + /* Octeon has a raid unit */ + OCTEON_FEATURE_RAID, + /* Octeon has a builtin USB */ + OCTEON_FEATURE_USB, + /* Octeon IPD can run without using work queue entries */ + OCTEON_FEATURE_NO_WPTR, + /* Octeon has DFA state machines */ + OCTEON_FEATURE_DFA, + /* Octeon MDIO block supports clause 45 transactions for 10 + * Gig support */ + OCTEON_FEATURE_MDIO_CLAUSE_45, + /* + * CN52XX and CN56XX used a block named NPEI for PCIe + * access. Newer chips replaced this with SLI+DPI. + */ + OCTEON_FEATURE_NPEI, + OCTEON_FEATURE_HFA, + OCTEON_FEATURE_DFM, + OCTEON_FEATURE_CIU2, + OCTEON_FEATURE_CIU3, + /* Octeon has FPA first seen on 78XX */ + OCTEON_FEATURE_FPA3, + OCTEON_FEATURE_FAU, + OCTEON_MAX_FEATURE +}; + +enum octeon_feature_bits { + OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */ +}; +extern enum octeon_feature_bits __octeon_feature_bits; + +/** + * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support. + * + * Returns: Non-zero if the feature exists. Zero if the feature does not exist. + */ +static inline int octeon_has_crypto(void) +{ + return __octeon_feature_bits & OCTEON_HAS_CRYPTO; +} + +/** + * Determine if the current Octeon supports a specific feature. These + * checks have been optimized to be fairly quick, but they should still + * be kept out of fast path code. + * + * @feature: Feature to check for. This should always be a constant so the + * compiler can remove the switch statement through optimization. + * + * Returns Non zero if the feature exists. Zero if the feature does not + * exist. + */ +static inline bool octeon_has_feature(enum octeon_feature feature) +{ + switch (feature) { + case OCTEON_FEATURE_SAAD: + return !OCTEON_IS_MODEL(OCTEON_CN3XXX); + + case OCTEON_FEATURE_DORM_CRYPTO: + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat2 fus_2; + fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); + return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto; + } else { + return false; + } + + case OCTEON_FEATURE_PCIE: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX) + || OCTEON_IS_MODEL(OCTEON_CN7XXX); + + case OCTEON_FEATURE_SRIO: + return OCTEON_IS_MODEL(OCTEON_CN63XX) + || OCTEON_IS_MODEL(OCTEON_CN66XX); + + case OCTEON_FEATURE_ILK: + return (OCTEON_IS_MODEL(OCTEON_CN68XX)); + + case OCTEON_FEATURE_KEY_MEMORY: + return OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_LED_CONTROLLER: + return OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN56XX); + + case OCTEON_FEATURE_TRA: + return !(OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)); + case OCTEON_FEATURE_MGMT_PORT: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_RAID: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_USB: + return !(OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)); + + case OCTEON_FEATURE_NO_WPTR: + return (OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX)) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + + case OCTEON_FEATURE_MDIO_CLAUSE_45: + return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)); + + case OCTEON_FEATURE_NPEI: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX); + + case OCTEON_FEATURE_PKND: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CN68XX_WQE: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CIU2: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + case OCTEON_FEATURE_CIU3: + case OCTEON_FEATURE_FPA3: + return OCTEON_IS_MODEL(OCTEON_CN78XX) + || OCTEON_IS_MODEL(OCTEON_CNF75XX) + || OCTEON_IS_MODEL(OCTEON_CN73XX); + case OCTEON_FEATURE_FAU: + return !(OCTEON_IS_MODEL(OCTEON_CN78XX) + || OCTEON_IS_MODEL(OCTEON_CNF75XX) + || OCTEON_IS_MODEL(OCTEON_CN73XX)); + + default: + break; + } + return false; +} + +#endif /* __OCTEON_FEATURE_H__ */ diff --git a/drivers/staging/octeon/octeon-model.h b/drivers/staging/octeon/octeon-model.h new file mode 100644 index 000000000000..f6150199d136 --- /dev/null +++ b/drivers/staging/octeon/octeon-model.h @@ -0,0 +1,408 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2010 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ +#ifndef __OCTEON_MODEL_H__ +#define __OCTEON_MODEL_H__ + +/* + * The defines below should be used with the OCTEON_IS_MODEL() macro + * to determine what model of chip the software is running on. Models + * ending in 'XX' match multiple models (families), while specific + * models match only that model. If a pass (revision) is specified, + * then only that revision will be matched. Care should be taken when + * checking for both specific models and families that the specific + * models are checked for first. While these defines are similar to + * the processor ID, they are not intended to be used by anything + * other that the OCTEON_IS_MODEL framework, and the values are + * subject to change at anytime without notice. + * + * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* + * macros should be used outside of this file. All other macros are + * for internal use only, and may change without notice. + */ + +#define OCTEON_FAMILY_MASK 0x00ffff00 +#define OCTEON_PRID_MASK 0x00ffffff + +/* Flag bits in top byte */ +/* Ignores revision in model checks */ +#define OM_IGNORE_REVISION 0x01000000 +/* Check submodels */ +#define OM_CHECK_SUBMODEL 0x02000000 +/* Match all models previous than the one specified */ +#define OM_MATCH_PREVIOUS_MODELS 0x04000000 +/* Ignores the minor revision on newer parts */ +#define OM_IGNORE_MINOR_REVISION 0x08000000 +#define OM_FLAG_MASK 0xff000000 + +/* Match all cn5XXX Octeon models. */ +#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 +/* Match all cn6XXX Octeon models. */ +#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 +/* Match all cnf7XXX Octeon models. */ +#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 +/* Match all cn7XXX Octeon models. */ +#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000 +#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \ + OM_MATCH_6XXX_FAMILY_MODELS | \ + OM_MATCH_F7XXX_FAMILY_MODELS | \ + OM_MATCH_7XXX_FAMILY_MODELS) +/* + * CN7XXX models with new revision encoding + */ + +#define OCTEON_CNF75XX_PASS1_0 0x000d9800 +#define OCTEON_CNF75XX (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF75XX_PASS1_X (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN73XX_PASS1_0 0x000d9700 +#define OCTEON_CN73XX_PASS1_1 0x000d9701 +#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \ + OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN70XX_PASS1_0 0x000d9600 +#define OCTEON_CN70XX_PASS1_1 0x000d9601 +#define OCTEON_CN70XX_PASS1_2 0x000d9602 + +#define OCTEON_CN70XX_PASS2_0 0x000d9608 + +#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \ + OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \ + OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN71XX OCTEON_CN70XX + +#define OCTEON_CN78XX_PASS1_0 0x000d9500 +#define OCTEON_CN78XX_PASS1_1 0x000d9501 +#define OCTEON_CN78XX_PASS2_0 0x000d9508 + +#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \ + OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \ + OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL) + +/* + * CNF7XXX models with new revision encoding + */ +#define OCTEON_CNF71XX_PASS1_0 0x000d9400 +#define OCTEON_CNF71XX_PASS1_1 0x000d9401 + +#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +/* + * CN6XXX models with new revision encoding + */ +#define OCTEON_CN68XX_PASS1_0 0x000d9100 +#define OCTEON_CN68XX_PASS1_1 0x000d9101 +#define OCTEON_CN68XX_PASS1_2 0x000d9102 +#define OCTEON_CN68XX_PASS2_0 0x000d9108 +#define OCTEON_CN68XX_PASS2_1 0x000d9109 +#define OCTEON_CN68XX_PASS2_2 0x000d910a + +#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X +#define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X + +#define OCTEON_CN66XX_PASS1_0 0x000d9200 +#define OCTEON_CN66XX_PASS1_2 0x000d9202 + +#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +#define OCTEON_CN63XX_PASS1_0 0x000d9000 +#define OCTEON_CN63XX_PASS1_1 0x000d9001 +#define OCTEON_CN63XX_PASS1_2 0x000d9002 +#define OCTEON_CN63XX_PASS2_0 0x000d9008 +#define OCTEON_CN63XX_PASS2_1 0x000d9009 +#define OCTEON_CN63XX_PASS2_2 0x000d900a + +#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) + +/* CN62XX is same as CN63XX with 1 MB cache */ +#define OCTEON_CN62XX OCTEON_CN63XX + +#define OCTEON_CN61XX_PASS1_0 0x000d9300 +#define OCTEON_CN61XX_PASS1_1 0x000d9301 + +#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) + +/* CN60XX is same as CN61XX with 512 KB cache */ +#define OCTEON_CN60XX OCTEON_CN61XX + +/* + * CN5XXX models with new revision encoding + */ +#define OCTEON_CN58XX_PASS1_0 0x000d0300 +#define OCTEON_CN58XX_PASS1_1 0x000d0301 +#define OCTEON_CN58XX_PASS1_2 0x000d0303 +#define OCTEON_CN58XX_PASS2_0 0x000d0308 +#define OCTEON_CN58XX_PASS2_1 0x000d0309 +#define OCTEON_CN58XX_PASS2_2 0x000d030a +#define OCTEON_CN58XX_PASS2_3 0x000d030b + +#define OCTEON_CN58XX (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X +#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X + +#define OCTEON_CN56XX_PASS1_0 0x000d0400 +#define OCTEON_CN56XX_PASS1_1 0x000d0401 +#define OCTEON_CN56XX_PASS2_0 0x000d0408 +#define OCTEON_CN56XX_PASS2_1 0x000d0409 + +#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X +#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X + +#define OCTEON_CN57XX OCTEON_CN56XX +#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN55XX OCTEON_CN56XX +#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN54XX OCTEON_CN56XX +#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 +#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 + +#define OCTEON_CN50XX_PASS1_0 0x000d0600 + +#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) +#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X + +/* + * NOTE: Octeon CN5000F model is not identifiable using the + * OCTEON_IS_MODEL() functions, but are treated as CN50XX. + */ + +#define OCTEON_CN52XX_PASS1_0 0x000d0700 +#define OCTEON_CN52XX_PASS2_0 0x000d0708 + +#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) +#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) +#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X +#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X + +/* + * CN3XXX models with old revision encoding + */ +#define OCTEON_CN38XX_PASS1 0x000d0000 +#define OCTEON_CN38XX_PASS2 0x000d0001 +#define OCTEON_CN38XX_PASS3 0x000d0003 +#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) + +#define OCTEON_CN36XX OCTEON_CN38XX +#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 +#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 + +/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */ +#define OCTEON_CN31XX_PASS1 0x000d0100 +#define OCTEON_CN31XX_PASS1_1 0x000d0102 +#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) + +/* + * This model is only used for internal checks, it is not a valid + * model for the OCTEON_MODEL environment variable. This matches the + * CN3010 and CN3005 but NOT the CN3020. + */ +#define OCTEON_CN30XX_PASS1 0x000d0200 +#define OCTEON_CN30XX_PASS1_1 0x000d0202 +#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) + +#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) + +#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) + +#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) +#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL) + +/* + * This matches the complete family of CN3xxx CPUs, and not subsequent + * models + */ +#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) +#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) +#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) +#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \ + OM_MATCH_F7XXX_FAMILY_MODELS) +#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \ + OM_MATCH_7XXX_FAMILY_MODELS) + +/* The revision byte (low byte) has two different encodings. + * CN3XXX: + * + * bits + * <7:5>: reserved (0) + * <4>: alternate package + * <3:0>: revision + * + * CN5XXX and older models: + * + * bits + * <7>: reserved (0) + * <6>: alternate package + * <5:3>: major revision + * <2:0>: minor revision + * + */ + +/* Masks used for the various types of model/family/revision matching */ +#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 +#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f +#define OCTEON_38XX_MODEL_MASK 0x00ffff10 +#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK) + +/* CN5XXX and later use different layout of bits in the revision ID field */ +#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK +#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f +#define OCTEON_58XX_MODEL_MASK 0x00ffff40 +#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK) +#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00ffff38) +#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 + +static inline u32 cvmx_get_proc_id(void) __attribute__ ((pure)); +static inline u64 cvmx_read_csr(u64 csr_addr); + +#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) + +/* + * __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) + * returns true if chip_model is identical or belong to the OCTEON + * model group specified in arg_model. + */ +/* NOTE: This for internal use only! */ +#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \ +((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ + ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == 0) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \ + ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ + && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \ + )) || \ + (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \ + ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == 0) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \ + ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \ + ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \ + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \ + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \ + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \ + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \ + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \ + && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \ + && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ + && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \ + ))) + +/* NOTE: This for internal use only!!!!! */ +static inline int __octeon_is_model_runtime__(u32 model) +{ + u32 cpuid = cvmx_get_proc_id(); + + return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); +} + +/* + * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done + * in a program. + * This should be kept runtime if at all possible and must be conditionalized + * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required. + * + * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) ) + * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR() + * I.e.: + * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX) + */ +#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) +#define OCTEON_IS_COMMON_BINARY() 1 +#undef OCTEON_MODEL + +#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX) +#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX) +#define OCTEON_IS_OCTEON2() \ + (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)) + +#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX) + +#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS()) + +const char *__init octeon_model_get_string(u32 chip_id); + +/* + * Return the octeon family, i.e., ProcessorID of the PrID register. + * + * @return the octeon family on success, ((unint32_t)-1) on error. + */ +static inline u32 cvmx_get_octeon_family(void) +{ + return cvmx_get_proc_id() & OCTEON_FAMILY_MASK; +} + +#include + +#endif /* __OCTEON_MODEL_H__ */ diff --git a/drivers/staging/octeon/octeon-stubs.h b/drivers/staging/octeon/octeon-stubs.h deleted file mode 100644 index 35b5078ba51e..000000000000 --- a/drivers/staging/octeon/octeon-stubs.h +++ /dev/null @@ -1,1435 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 512 - -#ifndef XKPHYS_TO_PHYS -# define XKPHYS_TO_PHYS(p) (p) -#endif - -#define OCTEON_IRQ_WORKQ0 0 -#define OCTEON_IRQ_RML 0 -#define OCTEON_IRQ_TIMER1 0 -#define OCTEON_IS_MODEL(x) 0 -#define octeon_has_feature(x) 0 -#define octeon_get_clock_rate() 0 - -#define CVMX_SYNCIOBDMA do { } while (0) - -#define CVMX_HELPER_INPUT_TAG_TYPE 0 -#define CVMX_HELPER_FIRST_MBUFF_SKIP 7 -#define CVMX_FAU_REG_END (2048) -#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) -#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 16 -#define CVMX_FPA_PACKET_POOL (0) -#define CVMX_FPA_PACKET_POOL_SIZE 16 -#define CVMX_FPA_WQE_POOL (1) -#define CVMX_FPA_WQE_POOL_SIZE 16 -#define CVMX_GMXX_RXX_ADR_CAM_EN(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CTL(a, b) ((a) + (b)) -#define CVMX_GMXX_PRTX_CFG(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_FRM_MAX(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_JABBER(a, b) ((a) + (b)) -#define CVMX_IPD_CTL_STATUS 0 -#define CVMX_PIP_FRM_LEN_CHKX(a) (a) -#define CVMX_PIP_NUM_INPUT_PORTS 1 -#define CVMX_SCR_SCRATCH 0 -#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 2 -#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 2 -#define CVMX_IPD_SUB_PORT_FCS 0 -#define CVMX_SSO_WQ_IQ_DIS 0 -#define CVMX_SSO_WQ_INT 0 -#define CVMX_POW_WQ_INT 0 -#define CVMX_SSO_WQ_INT_PC 0 -#define CVMX_NPI_RSL_INT_BLOCKS 0 -#define CVMX_POW_WQ_INT_PC 0 - -union cvmx_pip_wqe_word2 { - u64 u64; - - struct { - u64 bufs : 8; - u64 ip_offset : 8; - u64 vlan_valid : 1; - u64 vlan_stacked : 1; - u64 unassigned : 1; - u64 vlan_cfi : 1; - u64 vlan_id : 12; - u64 pr : 4; - u64 unassigned2 : 8; - u64 dec_ipcomp : 1; - u64 tcp_or_udp : 1; - u64 dec_ipsec : 1; - u64 is_v6 : 1; - u64 software : 1; - u64 L4_error : 1; - u64 is_frag : 1; - u64 IP_exc : 1; - u64 is_bcast : 1; - u64 is_mcast : 1; - u64 not_IP : 1; - u64 rcv_error : 1; - u64 err_code : 8; - } s; - - struct { - u64 bufs : 8; - u64 ip_offset : 8; - u64 vlan_valid : 1; - u64 vlan_stacked : 1; - u64 unassigned : 1; - u64 vlan_cfi : 1; - u64 vlan_id : 12; - u64 port : 12; - u64 dec_ipcomp : 1; - u64 tcp_or_udp : 1; - u64 dec_ipsec : 1; - u64 is_v6 : 1; - u64 software : 1; - u64 L4_error : 1; - u64 is_frag : 1; - u64 IP_exc : 1; - u64 is_bcast : 1; - u64 is_mcast : 1; - u64 not_IP : 1; - u64 rcv_error : 1; - u64 err_code : 8; - } s_cn68xx; - - struct { - u64 unused1 : 16; - u64 vlan : 16; - u64 unused2 : 32; - } svlan; - - struct { - u64 bufs : 8; - u64 unused : 8; - u64 vlan_valid : 1; - u64 vlan_stacked : 1; - u64 unassigned : 1; - u64 vlan_cfi : 1; - u64 vlan_id : 12; - u64 pr : 4; - u64 unassigned2 : 12; - u64 software : 1; - u64 unassigned3 : 1; - u64 is_rarp : 1; - u64 is_arp : 1; - u64 is_bcast : 1; - u64 is_mcast : 1; - u64 not_IP : 1; - u64 rcv_error : 1; - u64 err_code : 8; - } snoip; -}; - -union cvmx_pip_wqe_word0 { - struct { - uint64_t next_ptr:40; - uint8_t unused; - __wsum hw_chksum; - } cn38xx; - struct { - uint64_t pknd:6; /* 0..5 */ - uint64_t unused2:2; /* 6..7 */ - uint64_t bpid:6; /* 8..13 */ - uint64_t unused1:18; /* 14..31 */ - uint64_t l2ptr:8; /* 32..39 */ - uint64_t l3ptr:8; /* 40..47 */ - uint64_t unused0:8; /* 48..55 */ - uint64_t l4ptr:8; /* 56..63 */ - } cn68xx; -}; - -union cvmx_wqe_word0 { - uint64_t u64; - union cvmx_pip_wqe_word0 pip; -}; - -union cvmx_wqe_word1 { - uint64_t u64; - struct { - uint64_t tag:32; - uint64_t tag_type:2; - uint64_t varies:14; - uint64_t len:16; - }; - struct { - uint64_t tag:32; - uint64_t tag_type:2; - uint64_t zero_2:3; - uint64_t grp:6; - uint64_t zero_1:1; - uint64_t qos:3; - uint64_t zero_0:1; - uint64_t len:16; - } cn68xx; - struct { - uint64_t tag:32; - uint64_t tag_type:2; - uint64_t zero_2:1; - uint64_t grp:4; - uint64_t qos:3; - uint64_t ipprt:6; - uint64_t len:16; - } cn38xx; -}; - -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t addr:40; - } s; -}; - -struct cvmx_wqe { - union cvmx_wqe_word0 word0; - union cvmx_wqe_word1 word1; - union cvmx_pip_wqe_word2 word2; - union cvmx_buf_ptr packet_ptr; - uint8_t packet_data[96]; -}; - -union cvmx_helper_link_info { - uint64_t u64; - struct { - uint64_t reserved_20_63:44; - uint64_t link_up:1; /**< Is the physical link up? */ - uint64_t full_duplex:1; /**< 1 if the link is full duplex */ - uint64_t speed:18; /**< Speed of the link in Mbps */ - } s; -}; - -enum cvmx_fau_reg_32 { - CVMX_FAU_REG_32_START = 0, -}; - -enum cvmx_fau_op_size { - CVMX_FAU_OP_SIZE_8 = 0, - CVMX_FAU_OP_SIZE_16 = 1, - CVMX_FAU_OP_SIZE_32 = 2, - CVMX_FAU_OP_SIZE_64 = 3 -}; - -typedef enum { - CVMX_SPI_MODE_UNKNOWN = 0, - CVMX_SPI_MODE_TX_HALFPLEX = 1, - CVMX_SPI_MODE_RX_HALFPLEX = 2, - CVMX_SPI_MODE_DUPLEX = 3 -} cvmx_spi_mode_t; - -typedef enum { - CVMX_HELPER_INTERFACE_MODE_DISABLED, - CVMX_HELPER_INTERFACE_MODE_RGMII, - CVMX_HELPER_INTERFACE_MODE_GMII, - CVMX_HELPER_INTERFACE_MODE_SPI, - CVMX_HELPER_INTERFACE_MODE_PCIE, - CVMX_HELPER_INTERFACE_MODE_XAUI, - CVMX_HELPER_INTERFACE_MODE_SGMII, - CVMX_HELPER_INTERFACE_MODE_PICMG, - CVMX_HELPER_INTERFACE_MODE_NPI, - CVMX_HELPER_INTERFACE_MODE_LOOP, -} cvmx_helper_interface_mode_t; - -typedef enum { - CVMX_POW_WAIT = 1, - CVMX_POW_NO_WAIT = 0, -} cvmx_pow_wait_t; - -typedef enum { - CVMX_PKO_LOCK_NONE = 0, - CVMX_PKO_LOCK_ATOMIC_TAG = 1, - CVMX_PKO_LOCK_CMD_QUEUE = 2, -} cvmx_pko_lock_t; - -typedef enum { - CVMX_PKO_SUCCESS, - CVMX_PKO_INVALID_PORT, - CVMX_PKO_INVALID_QUEUE, - CVMX_PKO_INVALID_PRIORITY, - CVMX_PKO_NO_MEMORY, - CVMX_PKO_PORT_ALREADY_SETUP, - CVMX_PKO_CMD_QUEUE_INIT_ERROR -} cvmx_pko_status_t; - -enum cvmx_pow_tag_type { - CVMX_POW_TAG_TYPE_ORDERED = 0L, - CVMX_POW_TAG_TYPE_ATOMIC = 1L, - CVMX_POW_TAG_TYPE_NULL = 2L, - CVMX_POW_TAG_TYPE_NULL_NULL = 3L -}; - -union cvmx_ipd_ctl_status { - uint64_t u64; - struct cvmx_ipd_ctl_status_s { - uint64_t reserved_18_63:46; - uint64_t use_sop:1; - uint64_t rst_done:1; - uint64_t clken:1; - uint64_t no_wptr:1; - uint64_t pq_apkt:1; - uint64_t pq_nabuf:1; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } s; - struct cvmx_ipd_ctl_status_cn30xx { - uint64_t reserved_10_63:54; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn30xx; - struct cvmx_ipd_ctl_status_cn38xxp2 { - uint64_t reserved_9_63:55; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn38xxp2; - struct cvmx_ipd_ctl_status_cn50xx { - uint64_t reserved_15_63:49; - uint64_t no_wptr:1; - uint64_t pq_apkt:1; - uint64_t pq_nabuf:1; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn50xx; - struct cvmx_ipd_ctl_status_cn58xx { - uint64_t reserved_12_63:52; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn58xx; - struct cvmx_ipd_ctl_status_cn63xxp1 { - uint64_t reserved_16_63:48; - uint64_t clken:1; - uint64_t no_wptr:1; - uint64_t pq_apkt:1; - uint64_t pq_nabuf:1; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn63xxp1; -}; - -union cvmx_ipd_sub_port_fcs { - uint64_t u64; - struct cvmx_ipd_sub_port_fcs_s { - uint64_t port_bit:32; - uint64_t reserved_32_35:4; - uint64_t port_bit2:4; - uint64_t reserved_40_63:24; - } s; - struct cvmx_ipd_sub_port_fcs_cn30xx { - uint64_t port_bit:3; - uint64_t reserved_3_63:61; - } cn30xx; - struct cvmx_ipd_sub_port_fcs_cn38xx { - uint64_t port_bit:32; - uint64_t reserved_32_63:32; - } cn38xx; -}; - -union cvmx_ipd_sub_port_qos_cnt { - uint64_t u64; - struct cvmx_ipd_sub_port_qos_cnt_s { - uint64_t cnt:32; - uint64_t port_qos:9; - uint64_t reserved_41_63:23; - } s; -}; - -typedef struct { - uint32_t dropped_octets; - uint32_t dropped_packets; - uint32_t pci_raw_packets; - uint32_t octets; - uint32_t packets; - uint32_t multicast_packets; - uint32_t broadcast_packets; - uint32_t len_64_packets; - uint32_t len_65_127_packets; - uint32_t len_128_255_packets; - uint32_t len_256_511_packets; - uint32_t len_512_1023_packets; - uint32_t len_1024_1518_packets; - uint32_t len_1519_max_packets; - uint32_t fcs_align_err_packets; - uint32_t runt_packets; - uint32_t runt_crc_packets; - uint32_t oversize_packets; - uint32_t oversize_crc_packets; - uint32_t inb_packets; - uint64_t inb_octets; - uint16_t inb_errors; -} cvmx_pip_port_status_t; - -typedef struct { - uint32_t packets; - uint64_t octets; - uint64_t doorbell; -} cvmx_pko_port_status_t; - -union cvmx_pip_frm_len_chkx { - uint64_t u64; - struct cvmx_pip_frm_len_chkx_s { - uint64_t reserved_32_63:32; - uint64_t maxlen:16; - uint64_t minlen:16; - } s; -}; - -union cvmx_gmxx_rxx_frm_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_frm_ctl_s { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_11:1; - uint64_t ptp_mode:1; - uint64_t reserved_13_63:51; - } s; - struct cvmx_gmxx_rxx_frm_ctl_cn30xx { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t reserved_9_63:55; - } cn30xx; - struct cvmx_gmxx_rxx_frm_ctl_cn31xx { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t reserved_8_63:56; - } cn31xx; - struct cvmx_gmxx_rxx_frm_ctl_cn50xx { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_63:53; - } cn50xx; - struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t reserved_10_63:54; - } cn56xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn58xx { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t vlan_len:1; - uint64_t pad_len:1; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_63:53; - } cn58xx; - struct cvmx_gmxx_rxx_frm_ctl_cn61xx { - uint64_t pre_chk:1; - uint64_t pre_strp:1; - uint64_t ctl_drp:1; - uint64_t ctl_bck:1; - uint64_t ctl_mcst:1; - uint64_t ctl_smac:1; - uint64_t pre_free:1; - uint64_t reserved_7_8:2; - uint64_t pre_align:1; - uint64_t null_dis:1; - uint64_t reserved_11_11:1; - uint64_t ptp_mode:1; - uint64_t reserved_13_63:51; - } cn61xx; -}; - -union cvmx_gmxx_rxx_int_reg { - uint64_t u64; - struct cvmx_gmxx_rxx_int_reg_s { - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; - } s; - struct cvmx_gmxx_rxx_int_reg_cn30xx { - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t reserved_19_63:45; - } cn30xx; - struct cvmx_gmxx_rxx_int_reg_cn50xx { - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t reserved_6_6:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; - } cn50xx; - struct cvmx_gmxx_rxx_int_reg_cn52xx { - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; - } cn52xx; - struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { - uint64_t reserved_0_0:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t reserved_27_63:37; - } cn56xxp1; - struct cvmx_gmxx_rxx_int_reg_cn58xx { - uint64_t minerr:1; - uint64_t carext:1; - uint64_t maxerr:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t alnerr:1; - uint64_t lenerr:1; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t niberr:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t phy_link:1; - uint64_t phy_spd:1; - uint64_t phy_dupx:1; - uint64_t pause_drp:1; - uint64_t reserved_20_63:44; - } cn58xx; - struct cvmx_gmxx_rxx_int_reg_cn61xx { - uint64_t minerr:1; - uint64_t carext:1; - uint64_t reserved_2_2:1; - uint64_t jabber:1; - uint64_t fcserr:1; - uint64_t reserved_5_6:2; - uint64_t rcverr:1; - uint64_t skperr:1; - uint64_t reserved_9_9:1; - uint64_t ovrerr:1; - uint64_t pcterr:1; - uint64_t rsverr:1; - uint64_t falerr:1; - uint64_t coldet:1; - uint64_t ifgerr:1; - uint64_t reserved_16_18:3; - uint64_t pause_drp:1; - uint64_t loc_fault:1; - uint64_t rem_fault:1; - uint64_t bad_seq:1; - uint64_t bad_term:1; - uint64_t unsop:1; - uint64_t uneop:1; - uint64_t undat:1; - uint64_t hg2fld:1; - uint64_t hg2cc:1; - uint64_t reserved_29_63:35; - } cn61xx; -}; - -union cvmx_gmxx_prtx_cfg { - uint64_t u64; - struct cvmx_gmxx_prtx_cfg_s { - uint64_t reserved_22_63:42; - uint64_t pknd:6; - uint64_t reserved_14_15:2; - uint64_t tx_idle:1; - uint64_t rx_idle:1; - uint64_t reserved_9_11:3; - uint64_t speed_msb:1; - uint64_t reserved_4_7:4; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } s; - struct cvmx_gmxx_prtx_cfg_cn30xx { - uint64_t reserved_4_63:60; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } cn30xx; - struct cvmx_gmxx_prtx_cfg_cn52xx { - uint64_t reserved_14_63:50; - uint64_t tx_idle:1; - uint64_t rx_idle:1; - uint64_t reserved_9_11:3; - uint64_t speed_msb:1; - uint64_t reserved_4_7:4; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } cn52xx; -}; - -union cvmx_gmxx_rxx_adr_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_ctl_s { - uint64_t reserved_4_63:60; - uint64_t cam_mode:1; - uint64_t mcst:2; - uint64_t bcst:1; - } s; -}; - -union cvmx_pip_prt_tagx { - uint64_t u64; - struct cvmx_pip_prt_tagx_s { - uint64_t reserved_54_63:10; - uint64_t portadd_en:1; - uint64_t inc_hwchk:1; - uint64_t reserved_50_51:2; - uint64_t grptagbase_msb:2; - uint64_t reserved_46_47:2; - uint64_t grptagmask_msb:2; - uint64_t reserved_42_43:2; - uint64_t grp_msb:2; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t grptag_mskip:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; - } s; - struct cvmx_pip_prt_tagx_cn30xx { - uint64_t reserved_40_63:24; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t reserved_30_30:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; - } cn30xx; - struct cvmx_pip_prt_tagx_cn50xx { - uint64_t reserved_40_63:24; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t grptag_mskip:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; - } cn50xx; -}; - -union cvmx_spxx_int_reg { - uint64_t u64; - struct cvmx_spxx_int_reg_s { - uint64_t reserved_32_63:32; - uint64_t spf:1; - uint64_t reserved_12_30:19; - uint64_t calerr:1; - uint64_t syncerr:1; - uint64_t diperr:1; - uint64_t tpaovr:1; - uint64_t rsverr:1; - uint64_t drwnng:1; - uint64_t clserr:1; - uint64_t spiovr:1; - uint64_t reserved_2_3:2; - uint64_t abnorm:1; - uint64_t prtnxa:1; - } s; -}; - -union cvmx_spxx_int_msk { - uint64_t u64; - struct cvmx_spxx_int_msk_s { - uint64_t reserved_12_63:52; - uint64_t calerr:1; - uint64_t syncerr:1; - uint64_t diperr:1; - uint64_t tpaovr:1; - uint64_t rsverr:1; - uint64_t drwnng:1; - uint64_t clserr:1; - uint64_t spiovr:1; - uint64_t reserved_2_3:2; - uint64_t abnorm:1; - uint64_t prtnxa:1; - } s; -}; - -union cvmx_pow_wq_int { - uint64_t u64; - struct cvmx_pow_wq_int_s { - uint64_t wq_int:16; - uint64_t iq_dis:16; - uint64_t reserved_32_63:32; - } s; -}; - -union cvmx_sso_wq_int_thrx { - uint64_t u64; - struct { - uint64_t iq_thr:12; - uint64_t reserved_12_13:2; - uint64_t ds_thr:12; - uint64_t reserved_26_27:2; - uint64_t tc_thr:4; - uint64_t tc_en:1; - uint64_t reserved_33_63:31; - } s; -}; - -union cvmx_stxx_int_reg { - uint64_t u64; - struct cvmx_stxx_int_reg_s { - uint64_t reserved_9_63:55; - uint64_t syncerr:1; - uint64_t frmerr:1; - uint64_t unxfrm:1; - uint64_t nosync:1; - uint64_t diperr:1; - uint64_t datovr:1; - uint64_t ovrbst:1; - uint64_t calpar1:1; - uint64_t calpar0:1; - } s; -}; - -union cvmx_stxx_int_msk { - uint64_t u64; - struct cvmx_stxx_int_msk_s { - uint64_t reserved_8_63:56; - uint64_t frmerr:1; - uint64_t unxfrm:1; - uint64_t nosync:1; - uint64_t diperr:1; - uint64_t datovr:1; - uint64_t ovrbst:1; - uint64_t calpar1:1; - uint64_t calpar0:1; - } s; -}; - -union cvmx_pow_wq_int_pc { - uint64_t u64; - struct cvmx_pow_wq_int_pc_s { - uint64_t reserved_0_7:8; - uint64_t pc_thr:20; - uint64_t reserved_28_31:4; - uint64_t pc:28; - uint64_t reserved_60_63:4; - } s; -}; - -union cvmx_pow_wq_int_thrx { - uint64_t u64; - struct cvmx_pow_wq_int_thrx_s { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_23_23:1; - uint64_t ds_thr:11; - uint64_t reserved_11_11:1; - uint64_t iq_thr:11; - } s; - struct cvmx_pow_wq_int_thrx_cn30xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_18_23:6; - uint64_t ds_thr:6; - uint64_t reserved_6_11:6; - uint64_t iq_thr:6; - } cn30xx; - struct cvmx_pow_wq_int_thrx_cn31xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_20_23:4; - uint64_t ds_thr:8; - uint64_t reserved_8_11:4; - uint64_t iq_thr:8; - } cn31xx; - struct cvmx_pow_wq_int_thrx_cn52xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_21_23:3; - uint64_t ds_thr:9; - uint64_t reserved_9_11:3; - uint64_t iq_thr:9; - } cn52xx; - struct cvmx_pow_wq_int_thrx_cn63xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_22_23:2; - uint64_t ds_thr:10; - uint64_t reserved_10_11:2; - uint64_t iq_thr:10; - } cn63xx; -}; - -union cvmx_npi_rsl_int_blocks { - uint64_t u64; - struct cvmx_npi_rsl_int_blocks_s { - uint64_t reserved_32_63:32; - uint64_t rint_31:1; - uint64_t iob:1; - uint64_t reserved_28_29:2; - uint64_t rint_27:1; - uint64_t rint_26:1; - uint64_t rint_25:1; - uint64_t rint_24:1; - uint64_t asx1:1; - uint64_t asx0:1; - uint64_t rint_21:1; - uint64_t pip:1; - uint64_t spx1:1; - uint64_t spx0:1; - uint64_t lmc:1; - uint64_t l2c:1; - uint64_t rint_15:1; - uint64_t reserved_13_14:2; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t rint_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t npi:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; - } s; - struct cvmx_npi_rsl_int_blocks_cn30xx { - uint64_t reserved_32_63:32; - uint64_t rint_31:1; - uint64_t iob:1; - uint64_t rint_29:1; - uint64_t rint_28:1; - uint64_t rint_27:1; - uint64_t rint_26:1; - uint64_t rint_25:1; - uint64_t rint_24:1; - uint64_t asx1:1; - uint64_t asx0:1; - uint64_t rint_21:1; - uint64_t pip:1; - uint64_t spx1:1; - uint64_t spx0:1; - uint64_t lmc:1; - uint64_t l2c:1; - uint64_t rint_15:1; - uint64_t rint_14:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t rint_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t npi:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; - } cn30xx; - struct cvmx_npi_rsl_int_blocks_cn38xx { - uint64_t reserved_32_63:32; - uint64_t rint_31:1; - uint64_t iob:1; - uint64_t rint_29:1; - uint64_t rint_28:1; - uint64_t rint_27:1; - uint64_t rint_26:1; - uint64_t rint_25:1; - uint64_t rint_24:1; - uint64_t asx1:1; - uint64_t asx0:1; - uint64_t rint_21:1; - uint64_t pip:1; - uint64_t spx1:1; - uint64_t spx0:1; - uint64_t lmc:1; - uint64_t l2c:1; - uint64_t rint_15:1; - uint64_t rint_14:1; - uint64_t rint_13:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t rint_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t npi:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; - } cn38xx; - struct cvmx_npi_rsl_int_blocks_cn50xx { - uint64_t reserved_31_63:33; - uint64_t iob:1; - uint64_t lmc1:1; - uint64_t agl:1; - uint64_t reserved_24_27:4; - uint64_t asx1:1; - uint64_t asx0:1; - uint64_t reserved_21_21:1; - uint64_t pip:1; - uint64_t spx1:1; - uint64_t spx0:1; - uint64_t lmc:1; - uint64_t l2c:1; - uint64_t reserved_15_15:1; - uint64_t rad:1; - uint64_t usb:1; - uint64_t pow:1; - uint64_t tim:1; - uint64_t pko:1; - uint64_t ipd:1; - uint64_t reserved_8_8:1; - uint64_t zip:1; - uint64_t dfa:1; - uint64_t fpa:1; - uint64_t key:1; - uint64_t npi:1; - uint64_t gmx1:1; - uint64_t gmx0:1; - uint64_t mio:1; - } cn50xx; -}; - -union cvmx_pko_command_word0 { - uint64_t u64; - struct { - uint64_t total_bytes:16; - uint64_t segs:6; - uint64_t dontfree:1; - uint64_t ignore_i:1; - uint64_t ipoffp1:7; - uint64_t gather:1; - uint64_t rsp:1; - uint64_t wqp:1; - uint64_t n2:1; - uint64_t le:1; - uint64_t reg0:11; - uint64_t subone0:1; - uint64_t reg1:11; - uint64_t subone1:1; - uint64_t size0:2; - uint64_t size1:2; - } s; -}; - -union cvmx_ciu_timx { - uint64_t u64; - struct cvmx_ciu_timx_s { - uint64_t reserved_37_63:27; - uint64_t one_shot:1; - uint64_t len:36; - } s; -}; - -union cvmx_gmxx_rxx_rx_inbnd { - uint64_t u64; - struct cvmx_gmxx_rxx_rx_inbnd_s { - uint64_t status:1; - uint64_t speed:2; - uint64_t duplex:1; - uint64_t reserved_4_63:60; - } s; -}; - -static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg, - int32_t value) -{ - return value; -} - -static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg, - int32_t value) -{ } - -static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg, - int32_t value) -{ } - -static inline uint64_t cvmx_scratch_read64(uint64_t address) -{ - return 0; -} - -static inline void cvmx_scratch_write64(uint64_t address, uint64_t value) -{ } - -static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work) -{ - return 0; -} - -static inline void *cvmx_phys_to_ptr(uint64_t physical_address) -{ - return (void *)(uintptr_t)(physical_address); -} - -static inline phys_addr_t cvmx_ptr_to_phys(void *ptr) -{ - return (unsigned long)ptr; -} - -static inline int cvmx_helper_get_interface_num(int ipd_port) -{ - return ipd_port; -} - -static inline int cvmx_helper_get_interface_index_num(int ipd_port) -{ - return ipd_port; -} - -static inline void cvmx_fpa_enable(void) -{ } - -static inline uint64_t cvmx_read_csr(uint64_t csr_addr) -{ - return 0; -} - -static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) -{ } - -static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) -{ - return 0; -} - -static inline void *cvmx_fpa_alloc(uint64_t pool) -{ - return NULL; -} - -static inline void cvmx_fpa_free(void *ptr, uint64_t pool, - uint64_t num_cache_lines) -{ } - -static inline int octeon_is_simulation(void) -{ - return 1; -} - -static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, - cvmx_pip_port_status_t *status) -{ } - -static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, - cvmx_pko_port_status_t *status) -{ } - -static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int - interface) -{ - return 0; -} - -static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port) -{ - union cvmx_helper_link_info ret = { .u64 = 0 }; - - return ret; -} - -static inline int cvmx_helper_link_set(int ipd_port, - union cvmx_helper_link_info link_info) -{ - return 0; -} - -static inline int cvmx_helper_initialize_packet_io_global(void) -{ - return 0; -} - -static inline int cvmx_helper_get_number_of_interfaces(void) -{ - return 2; -} - -static inline int cvmx_helper_ports_on_interface(int interface) -{ - return 1; -} - -static inline int cvmx_helper_get_ipd_port(int interface, int port) -{ - return 0; -} - -static inline int cvmx_helper_ipd_and_packet_input_enable(void) -{ - return 0; -} - -static inline void cvmx_ipd_disable(void) -{ } - -static inline void cvmx_ipd_free_ptr(void) -{ } - -static inline void cvmx_pko_disable(void) -{ } - -static inline void cvmx_pko_shutdown(void) -{ } - -static inline int cvmx_pko_get_base_queue_per_core(int port, int core) -{ - return port; -} - -static inline int cvmx_pko_get_base_queue(int port) -{ - return port; -} - -static inline int cvmx_pko_get_num_queues(int port) -{ - return port; -} - -static inline unsigned int cvmx_get_core_num(void) -{ - return 0; -} - -static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, - cvmx_pow_wait_t wait) -{ } - -static inline void cvmx_pow_work_request_async(int scr_addr, - cvmx_pow_wait_t wait) -{ } - -static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr) -{ - struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr; - - return wqe; -} - -static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) -{ - return (void *)(unsigned long)wait; -} - -static inline int cvmx_spi_restart_interface(int interface, - cvmx_spi_mode_t mode, int timeout) -{ - return 0; -} - -static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, - enum cvmx_fau_reg_32 reg, - int32_t value) -{ } - -static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(int interface, int port) -{ - union cvmx_gmxx_rxx_rx_inbnd r; - - r.u64 = 0; - return r; -} - -static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, - cvmx_pko_lock_t use_locking) -{ } - -static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, - uint64_t queue, union cvmx_pko_command_word0 pko_command, - union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking) -{ - return 0; -} - -static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port) -{ } - -static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos) -{ } - -static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work) -{ - return 0; -} - -static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp) -{ } - -static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t qos, uint64_t grp) -{ } - -#define CVMX_ASXX_RX_CLK_SETX(a, b) ((a) + (b)) -#define CVMX_ASXX_TX_CLK_SETX(a, b) ((a) + (b)) -#define CVMX_CIU_TIMX(a) (a) -#define CVMX_GMXX_RXX_ADR_CAM0(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CAM1(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CAM2(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CAM3(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CAM4(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_ADR_CAM5(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_FRM_CTL(a, b) ((a) + (b)) -#define CVMX_GMXX_RXX_INT_REG(a, b) ((a) + (b)) -#define CVMX_GMXX_SMACX(a, b) ((a) + (b)) -#define CVMX_PIP_PRT_TAGX(a) (a) -#define CVMX_POW_PP_GRP_MSKX(a) (a) -#define CVMX_POW_WQ_INT_THRX(a) (a) -#define CVMX_SPXX_INT_MSK(a) (a) -#define CVMX_SPXX_INT_REG(a) (a) -#define CVMX_SSO_PPX_GRP_MSK(a) (a) -#define CVMX_SSO_WQ_INT_THRX(a) (a) -#define CVMX_STXX_INT_MSK(a) (a) -#define CVMX_STXX_INT_REG(a) (a) diff --git a/drivers/staging/octeon/octeon.h b/drivers/staging/octeon/octeon.h new file mode 100644 index 000000000000..cae46e099ed2 --- /dev/null +++ b/drivers/staging/octeon/octeon.h @@ -0,0 +1,364 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2008 Cavium Networks + */ +#ifndef __ASM_OCTEON_OCTEON_H +#define __ASM_OCTEON_OCTEON_H + +#include "cvmx.h" +#include + +extern u64 octeon_bootmem_alloc_range_phys(u64 size, + u64 alignment, + u64 min_addr, + u64 max_addr, + int do_locking); +extern void *octeon_bootmem_alloc(u64 size, u64 alignment, + int do_locking); +extern void *octeon_bootmem_alloc_range(u64 size, u64 alignment, + u64 min_addr, u64 max_addr, + int do_locking); +extern void *octeon_bootmem_alloc_named(u64 size, u64 alignment, + char *name); +extern void *octeon_bootmem_alloc_named_range(u64 size, u64 min_addr, + u64 max_addr, u64 align, + char *name); +extern void *octeon_bootmem_alloc_named_address(u64 size, u64 address, + char *name); +extern int octeon_bootmem_free_named(char *name); +extern void octeon_bootmem_lock(void); +extern void octeon_bootmem_unlock(void); + +extern int octeon_is_simulation(void); +extern int octeon_is_pci_host(void); +extern int octeon_usb_is_ref_clk(void); +extern u64 octeon_get_clock_rate(void); +extern u64 octeon_get_io_clock_rate(void); +extern const char *octeon_board_type_string(void); +extern const char *octeon_get_pci_interrupts(void); +extern int octeon_get_southbridge_interrupt(void); +extern int octeon_get_boot_coremask(void); +extern int octeon_get_boot_num_arguments(void); +extern const char *octeon_get_boot_argument(int arg); +extern void octeon_user_io_init(void); + +extern void octeon_init_cvmcount(void); +extern void octeon_setup_delays(void); +extern void octeon_io_clk_delay(unsigned long); + +#define OCTEON_ARGV_MAX_ARGS 64 +#define OCTEON_SERIAL_LEN 20 + +struct octeon_boot_descriptor { +#ifdef __BIG_ENDIAN_BITFIELD + /* Start of block referenced by assembly code - do not change! */ + u32 desc_version; + u32 desc_size; + u64 stack_top; + u64 heap_base; + u64 heap_end; + /* Only used by bootloader */ + u64 entry_point; + u64 desc_vaddr; + /* End of This block referenced by assembly code - do not change! */ + u32 exception_base_addr; + u32 stack_size; + u32 heap_size; + /* Argc count for application. */ + u32 argc; + u32 argv[OCTEON_ARGV_MAX_ARGS]; + +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) + /* If set, use uart1 for console */ +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) + /* If set, use PCI console */ +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) + /* Call exit on break on serial port */ +#define OCTEON_BL_FLAG_BREAK (1 << 5) + + u32 flags; + u32 core_mask; + /* DRAM size in megabyes. */ + u32 dram_size; + /* physical address of free memory descriptor block. */ + u32 phy_mem_desc_addr; + /* used to pass flags from app to debugger. */ + u32 debugger_flags_base_addr; + /* CPU clock speed, in hz. */ + u32 eclock_hz; + /* DRAM clock speed, in hz. */ + u32 dclock_hz; + /* SPI4 clock in hz. */ + u32 spi_clock_hz; + u16 board_type; + u8 board_rev_major; + u8 board_rev_minor; + u16 chip_type; + u8 chip_rev_major; + u8 chip_rev_minor; + char board_serial_number[OCTEON_SERIAL_LEN]; + u8 mac_addr_base[6]; + u8 mac_addr_count; + u64 cvmx_desc_vaddr; +#else + u32 desc_size; + u32 desc_version; + u64 stack_top; + u64 heap_base; + u64 heap_end; + /* Only used by bootloader */ + u64 entry_point; + u64 desc_vaddr; + /* End of This block referenced by assembly code - do not change! */ + u32 stack_size; + u32 exception_base_addr; + u32 argc; + u32 heap_size; + /* + * Argc count for application. + * Warning low bit scrambled in little-endian. + */ + u32 argv[OCTEON_ARGV_MAX_ARGS]; + +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) + /* If set, use uart1 for console */ +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) + /* If set, use PCI console */ +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) + /* Call exit on break on serial port */ +#define OCTEON_BL_FLAG_BREAK (1 << 5) + + u32 core_mask; + u32 flags; + /* physical address of free memory descriptor block. */ + u32 phy_mem_desc_addr; + /* DRAM size in megabyes. */ + u32 dram_size; + /* CPU clock speed, in hz. */ + u32 eclock_hz; + /* used to pass flags from app to debugger. */ + u32 debugger_flags_base_addr; + /* SPI4 clock in hz. */ + u32 spi_clock_hz; + /* DRAM clock speed, in hz. */ + u32 dclock_hz; + u8 chip_rev_minor; + u8 chip_rev_major; + u16 chip_type; + u8 board_rev_minor; + u8 board_rev_major; + u16 board_type; + + u64 unused1[4]; /* Not even filled in by bootloader. */ + + u64 cvmx_desc_vaddr; +#endif +}; + +union octeon_cvmemctl { + u64 u64; + struct { + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 tlbbist:1, + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 l1cbist:1, + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 l1dbist:1, + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 dcmbist:1, + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 ptgbist:1, + /* RO 1 = BIST fail, 0 = BIST pass */ + __BITFIELD_FIELD(u64 wbfbist:1, + /* Reserved */ + __BITFIELD_FIELD(u64 reserved:17, + /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU. + * This field selects between the TLB replacement policies: + * bitmask LRU or NLU. Bitmask LRU maintains a mask of + * recently used TLB entries and avoids them as new entries + * are allocated. NLU simply guarantees that the next + * allocation is not the last used TLB entry. */ + __BITFIELD_FIELD(u64 tlbnlu:1, + /* OCTEON II - Selects the bit in the counter used for + * releasing a PAUSE. This counter trips every 2(8+PAUSETIME) + * cycles. If not already released, the cnMIPS II core will + * always release a given PAUSE instruction within + * 2(8+PAUSETIME). If the counter trip happens to line up, + * the cnMIPS II core may release the PAUSE instantly. */ + __BITFIELD_FIELD(u64 pausetime:3, + /* OCTEON II - This field is an extension of + * CvmMemCtl[DIDTTO] */ + __BITFIELD_FIELD(u64 didtto2:1, + /* R/W If set, marked write-buffer entries time out + * the same as other entries; if clear, marked + * write-buffer entries use the maximum timeout. */ + __BITFIELD_FIELD(u64 dismarkwblongto:1, + /* R/W If set, a merged store does not clear the + * write-buffer entry timeout state. */ + __BITFIELD_FIELD(u64 dismrgclrwbto:1, + /* R/W Two bits that are the MSBs of the resultant + * CVMSEG LM word location for an IOBDMA. The other 8 + * bits come from the SCRADDR field of the IOBDMA. */ + __BITFIELD_FIELD(u64 iobdmascrmsb:2, + /* R/W If set, SYNCWS and SYNCS only order marked + * stores; if clear, SYNCWS and SYNCS only order + * unmarked stores. SYNCWSMARKED has no effect when + * DISSYNCWS is set. */ + __BITFIELD_FIELD(u64 syncwsmarked:1, + /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as + * SYNC. */ + __BITFIELD_FIELD(u64 dissyncws:1, + /* R/W If set, no stall happens on write buffer + * full. */ + __BITFIELD_FIELD(u64 diswbfst:1, + /* R/W If set (and SX set), supervisor-level + * loads/stores can use XKPHYS addresses with + * VA<48>==0 */ + __BITFIELD_FIELD(u64 xkmemenas:1, + /* R/W If set (and UX set), user-level loads/stores + * can use XKPHYS addresses with VA<48>==0 */ + __BITFIELD_FIELD(u64 xkmemenau:1, + /* R/W If set (and SX set), supervisor-level + * loads/stores can use XKPHYS addresses with + * VA<48>==1 */ + __BITFIELD_FIELD(u64 xkioenas:1, + /* R/W If set (and UX set), user-level loads/stores + * can use XKPHYS addresses with VA<48>==1 */ + __BITFIELD_FIELD(u64 xkioenau:1, + /* R/W If set, all stores act as SYNCW (NOMERGE must + * be set when this is set) RW, reset to 0. */ + __BITFIELD_FIELD(u64 allsyncw:1, + /* R/W If set, no stores merge, and all stores reach + * the coherent bus in order. */ + __BITFIELD_FIELD(u64 nomerge:1, + /* R/W Selects the bit in the counter used for DID + * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = + * 214. Actual time-out is between 1x and 2x this + * interval. For example, with DIDTTO=3, expiration + * interval is between 16K and 32K. */ + __BITFIELD_FIELD(u64 didtto:2, + /* R/W If set, the (mem) CSR clock never turns off. */ + __BITFIELD_FIELD(u64 csrckalwys:1, + /* R/W If set, mclk never turns off. */ + __BITFIELD_FIELD(u64 mclkalwys:1, + /* R/W Selects the bit in the counter used for write + * buffer flush time-outs (WBFLT+11) is the bit + * position in an internal counter used to determine + * expiration. The write buffer expires between 1x and + * 2x this interval. For example, with WBFLT = 0, a + * write buffer expires between 2K and 4K cycles after + * the write buffer entry is allocated. */ + __BITFIELD_FIELD(u64 wbfltime:3, + /* R/W If set, do not put Istream in the L2 cache. */ + __BITFIELD_FIELD(u64 istrnol2:1, + /* R/W The write buffer threshold. */ + __BITFIELD_FIELD(u64 wbthresh:4, + /* Reserved */ + __BITFIELD_FIELD(u64 reserved2:2, + /* R/W If set, CVMSEG is available for loads/stores in + * kernel/debug mode. */ + __BITFIELD_FIELD(u64 cvmsegenak:1, + /* R/W If set, CVMSEG is available for loads/stores in + * supervisor mode. */ + __BITFIELD_FIELD(u64 cvmsegenas:1, + /* R/W If set, CVMSEG is available for loads/stores in + * user mode. */ + __BITFIELD_FIELD(u64 cvmsegenau:1, + /* R/W Size of local memory in cache blocks, 54 (6912 + * bytes) is max legal value. */ + __BITFIELD_FIELD(u64 lmemsz:6, + ;))))))))))))))))))))))))))))))))) + } s; +}; + +extern void octeon_check_cpu_bist(void); + +int octeon_prune_device_tree(void); +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_68xx_begin; + +/** + * Write a 32bit value to the Octeon NPI register space + * + * @address: Address to write to + * @val: Value to write + */ +static inline void octeon_npi_write32(u64 address, u32 val) +{ + cvmx_write64_uint32(address ^ 4, val); + cvmx_read64_uint32(address ^ 4); +} + +#ifdef CONFIG_SMP +void octeon_setup_smp(void); +#else +static inline void octeon_setup_smp(void) {} +#endif + +struct irq_domain; +struct device_node; +struct irq_data; +struct irq_chip; +void octeon_ciu3_mbox_send(int cpu, unsigned int mbox); +int octeon_irq_ciu3_xlat(struct irq_domain *d, + struct device_node *node, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type); +void octeon_irq_ciu3_enable(struct irq_data *data); +void octeon_irq_ciu3_disable(struct irq_data *data); +void octeon_irq_ciu3_ack(struct irq_data *data); +void octeon_irq_ciu3_mask(struct irq_data *data); +void octeon_irq_ciu3_mask_ack(struct irq_data *data); +int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw, struct irq_chip *chip); + +/* Octeon multiplier save/restore routines from octeon_switch.S */ +void octeon_mult_save(void); +void octeon_mult_restore(void); +void octeon_mult_save_end(void); +void octeon_mult_restore_end(void); +void octeon_mult_save3(void); +void octeon_mult_save3_end(void); +void octeon_mult_save2(void); +void octeon_mult_save2_end(void); +void octeon_mult_restore3(void); +void octeon_mult_restore3_end(void); +void octeon_mult_restore2(void); +void octeon_mult_restore2_end(void); + +/** + * Read a 32bit value from the Octeon NPI register space + * + * @address: Address to read + * Returns The result + */ +static inline u32 octeon_npi_read32(u64 address) +{ + return cvmx_read64_uint32(address ^ 4); +} + +extern struct cvmx_bootinfo *octeon_bootinfo; + +extern u64 octeon_bootloader_entry_addr; + +extern void (*octeon_irq_setup_secondary)(void); + +typedef void (*octeon_irq_ip4_handler_t)(void); +void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); + +extern void octeon_fixup_irqs(void); + +extern struct semaphore octeon_bootbus_sem; + +struct irq_domain *octeon_irq_get_block_domain(int node, u8 block); + +#endif /* __ASM_OCTEON_OCTEON_H */ -- 2.43.0