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Tue, 26 Aug 2025 21:28:27 -0700 (PDT) Date: Wed, 27 Aug 2025 07:28:26 +0300 From: Svyatoslav To: Mikko Perttunen , Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru CC: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v1_02/19=5D_dt-bindings=3A_cloc?= =?US-ASCII?Q?k=3A_tegra20=3A_Add_IDs_for_CSI_PAD_clocks?= User-Agent: K-9 Mail for Android In-Reply-To: <2451218.NG923GbCHz@senjougahara> References: <20250819121631.84280-1-clamor95@gmail.com> <20250819121631.84280-3-clamor95@gmail.com> <2451218.NG923GbCHz@senjougahara> Message-ID: <268A6593-1FAC-4A4D-925A-801FB6FEE9F6@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable 27 =D1=81=D0=B5=D1=80=D0=BF=D0=BD=D1=8F 2025=E2=80=AF=D1=80=2E 07:19:39 GM= T+03:00, Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5= : >On Tuesday, August 19, 2025 9:16=E2=80=AFPM Svyatoslav Ryhel wrote: >> Tegra30 has CSI PAD clock enable bits embedded into PLLD/PLLD2 register= s=2E >> Add ids for these clocks=2E >>=20 >> Signed-off-by: Svyatoslav Ryhel >> --- >> include/dt-bindings/clock/tegra30-car=2Eh | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >>=20 >> diff --git a/include/dt-bindings/clock/tegra30-car=2Eh >> b/include/dt-bindings/clock/tegra30-car=2Eh index f193663e6f28=2E=2E14b= 83e90a0fc >> 100644 >> --- a/include/dt-bindings/clock/tegra30-car=2Eh >> +++ b/include/dt-bindings/clock/tegra30-car=2Eh >> @@ -271,6 +271,8 @@ >> #define TEGRA30_CLK_AUDIO3_MUX 306 >> #define TEGRA30_CLK_AUDIO4_MUX 307 >> #define TEGRA30_CLK_SPDIF_MUX 308 >> -#define TEGRA30_CLK_CLK_MAX 309 >> +#define TEGRA30_CLK_CSIA_PAD 309 >> +#define TEGRA30_CLK_CSIB_PAD 310 >> +#define TEGRA30_CLK_CLK_MAX 311 >>=20 >> #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ > >The commit message refers to tegra20, but contents are tegra30=2E > My, bad, it should be tegra30 >Regarding the CLK_MAX define, I agree that it would be better to get rid = of=20 >it=2E Perhaps you can check if it would be reasonable to calculate it=20 >dynamically in the driver, but a define and sanity check in the driver wo= uld=20 >work too, I think=2E > It is not unreasonable, but moving this elsewhere may cause issues with ad= ding new clocks=2E Addind new clocks would require updating not only header= but also a place where max clocks are moved to and ai am not sure how can = I dinamically calculate amount of clocks in the driver without updating bot= h header and driver with each new clock added=2E Maybe you can propose a me= thod? >Cheers, >Mikko > >