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[2003:e4:1f16:2000:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42127079536sm27841245e9.32.2024.05.30.08.12.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 May 2024 08:12:58 -0700 (PDT) Content-Type: multipart/signed; boundary=a2632c94a24b51b1ce87ba75765e7af51906aa4822f6b0fd9e4b1e0f6638; micalg=pgp-sha256; protocol="application/pgp-signature" Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Date: Thu, 30 May 2024 17:12:58 +0200 Message-Id: Subject: Re: [PATCH] staging: nvec: make i2c controller register writes robust From: "Thierry Reding" To: "Marc Dietrich" , "Ben Dooks" Cc: , , , "Thierry Reding" X-Mailer: aerc 0.16.0-1-0-g560d6168f0ed-dirty References: <20240421104642.25417-1-marvin24@gmx.de> <2338e58b-1ec2-4500-9675-2d8a3aaa107f@codethink.co.uk> <79c10e8e-bf3e-7eca-a0cd-e177a270a517@gmx.de> In-Reply-To: <79c10e8e-bf3e-7eca-a0cd-e177a270a517@gmx.de> --a2632c94a24b51b1ce87ba75765e7af51906aa4822f6b0fd9e4b1e0f6638 Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Wed May 1, 2024 at 9:03 PM CEST, Marc Dietrich wrote: > Hi Ben, > > On Mon, 22 Apr 2024, Ben Dooks wrote: > > > On 21/04/2024 11:46, Marc Dietrich wrote: > >> The i2c controller needs to read back the data written to its register= s. > >> This way we can avoid the long delay in the interrupt handler. > >> > >> Signed-off-by: Marc Dietrich > >> --- > >> drivers/staging/nvec/nvec.c | 41 ++++++++++++++++++++++-------------= -- > >> 1 file changed, 24 insertions(+), 17 deletions(-) > >> > >> diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c > >> index 45df190c2f94..214839f51048 100644 > >> --- a/drivers/staging/nvec/nvec.c > >> +++ b/drivers/staging/nvec/nvec.c > >> @@ -570,6 +570,22 @@ static void nvec_tx_set(struct nvec_chip *nvec) > >> (uint)nvec->tx->size, nvec->tx->data[1]); > >> } > >> > >> +/** > >> + * i2c_writel - safely write to an I2C client controller register > >> + * @val: value to be written > >> + * @reg: register to write to > >> + * > >> + * A write to an I2C controller register needs to be read back to mak= e > >> sure > >> + * that the value has arrived. > >> + */ > >> +static void i2c_writel(u32 val, void *reg) > >> +{ > >> + writel_relaxed(val, reg); > >> + > >> + /* read back register to make sure that register writes completed */ > >> + readl_relaxed(reg); > >> +} > > > > I thought the default behaviour of writel() should be to force writes > > out of any CPU buffers. Are there any bus isuses here causing the code > > to be necessary (and if so, why is there another buffer breaking the > > writel behaviour?) > > if fear that's a question only NVIDIA can answer. Ben, in case you didn't see the discussion on v2 of this patch, it's here: https://lore.kernel.org/all/D1N2OIXAF6QQ.3TCYLBU42CJ3U@gmail.com/ in a nutshell: there's indeed another buffer here that causes these writes to be queued and the read-back flushes that queue. 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