[PATCH 0/3] staging: rtl8723bs: coding style cleanups for rtl8723b_phycfg.c

[PATCH 0/3] staging: rtl8723bs: coding style cleanups for rtl8723b_phycfg.c

[osjin83]

From: tas0dev <osjin83@gmail.com>

This patch series fixes various coding style issues in rtl8723b_phycfg.c
as reported by checkpatch.pl

The changes include:
- Fixing spacing around binary and bitwise operators.
- Formatting type casts and aligning function parameters.
- Removing unnecessary blank lines to improve code readability.

These are purely cosmetic changes to bring the driver closer to the
Linux kernel coding style.

I wanted to contribute to Linux, but in the end, I could only make a small change. I'm sorry.

tas0dev (3):
  staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c
  staging: rtl8723bs: fix casting and alignment spacing in
    rtl8723b_phycfg.c
  staging: rtl8723bs: remove unnecessary blank lines in
    rtl8723b_phycfg.c

 .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   | 65 ++++++++-----------
 1 file changed, 26 insertions(+), 39 deletions(-)

-- 
2.53.0

[PATCH 1/3] staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c

[osjin83]

From: tas0dev <osjin83@gmail.com>

Fix various spacing issues reported by checkpatch.pl to improve code
readability and conform to the Linux kernel coding style.

Specifically, this patch:
- Adds missing spaces around binary operators (| , >> , << , + , &).
- Corrects the spacing in bitwise expressions within function calls.
- Ensures consistent use of whitespace in arithmetic operations.

These changes are purely cosmetic and do not alter the functional
behavior of the driver.

Signed-off-by: tas0dev <osjin83@gmail.com>
---
 .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   | 44 +++++++++----------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
index 7fac1c2ba8e0..cfa00775341b 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
@@ -19,7 +19,7 @@ static	u32 phy_CalculateBitShift(u32 BitMask)
 	u32 i;
 
 	for (i = 0; i <= 31; i++) {
-		if (((BitMask>>i) &  0x1) == 1)
+		if (((BitMask >> i) &  0x1) == 1)
 			break;
 	}
 	return i;
@@ -109,18 +109,18 @@ static u32 phy_RFSerialRead_8723B(
 	NewOffset = Offset;
 
 	if (eRFPath == RF_PATH_A) {
-		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
-		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
-		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
+		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
+		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 	} else {
-		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
-		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
-		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
+		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
+		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 	}
 
-	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
-	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
-	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
+	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
+	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
+	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 
 	udelay(10);
 
@@ -129,16 +129,16 @@ static u32 phy_RFSerialRead_8723B(
 	udelay(10);
 
 	if (eRFPath == RF_PATH_A)
-		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
+		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
 	else if (eRFPath == RF_PATH_B)
-		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
+		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
 
 	if (RfPiEnable) {
 		/*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
-		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
+		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
 	} else {
 		/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
-		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
+		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
 	}
 	return retValue;
 
@@ -203,7 +203,7 @@ static void phy_RFSerialWrite_8723B(
 	/*  */
 	/*  Put write addr in [5:0]  and write data in [31:16] */
 	/*  */
-	DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;	/*  T65 RF */
+	DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;	/*  T65 RF */
 	/*  */
 	/*  Write Operation */
 	/*  */
@@ -266,7 +266,7 @@ void PHY_SetRFReg_8723B(
 	if (BitMask != bRFRegOffsetMask) {
 		Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
 		BitShift =  phy_CalculateBitShift(BitMask);
-		Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
+		Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
 	}
 
 	phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
@@ -385,11 +385,11 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
 
 	/*  Enable BB and RF */
 	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
-	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
+	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1));
 
 	rtw_write32(Adapter, 0x948, 0x280);	/*  Others use Antenna S1 */
 
-	rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
+	rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 
 	msleep(1);
 
@@ -397,7 +397,7 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
 
 	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
 
-	rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
+	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
 
 	/*  */
 	/*  Config BB and AGC */
@@ -631,7 +631,7 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
 
 		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 
-		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
+		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
 		break;
 
 	/* 40 MHz channel*/
@@ -641,11 +641,11 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
 		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 
 		/*  Set Control channel to upper or lower. These settings are required only for 40MHz */
-		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
+		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
 
 		PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
 
-		PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
+		PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 		break;
 	default:
 		break;
-- 
2.53.0

[PATCH 2/3] staging: rtl8723bs: fix casting and alignment spacing in rtl8723b_phycfg.c

[osjin83]

From: tas0dev <osjin83@gmail.com>

Clean up spacing issues related to type casting and function parameter
alignment as flagged by checkpatch.pl.

Specifically, this patch:
- Removes the unnecessary space between a type cast and the variable,
  changing "(u8) value" to "(u8)value".
- Adjusts the alignment of arguments in function calls to match the
  open parenthesis.
- Standardizes the formatting of multi-line function parameters for
  better readability.

These changes are stylistic improvements and have no impact on the
runtime logic of the driver.

Signed-off-by: tas0dev <osjin83@gmail.com>
---
 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
index cfa00775341b..498f7b25a2b5 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
@@ -395,7 +395,8 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
 
 	PHY_SetRFReg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
 
-	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
+	rtw_write8(Adapter, REG_SYS_FUNC_EN,
+		   FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 
 	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
 
@@ -531,7 +532,7 @@ u8 PHY_GetTxPowerIndex(
 	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 	s8 txPower = 0, powerDiffByRate = 0, limit = 0;
 
-	txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
+	txPower = (s8)PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
 	powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, Rate);
 
 	limit = phy_get_tx_pwr_lmt(
@@ -551,7 +552,7 @@ u8 PHY_GetTxPowerIndex(
 	if (txPower > MAX_POWER_INDEX)
 		txPower = MAX_POWER_INDEX;
 
-	return (u8) txPower;
+	return (u8)txPower;
 }
 
 void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)
-- 
2.53.0

[PATCH 3/3] staging: rtl8723bs: remove unnecessary blank lines in rtl8723b_phycfg.c

[osjin83]

From: tas0dev <osjin83@gmail.com>

Remove unnecessary blank lines throughout rtl8723b_phycfg.c to clean
up the code and adhere to the Linux kernel coding style.

Signed-off-by: tas0dev <osjin83@gmail.com>
---
 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
index 498f7b25a2b5..10eb96105f83 100644
--- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
+++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
@@ -25,7 +25,6 @@ static	u32 phy_CalculateBitShift(u32 BitMask)
 	return i;
 }
 
-
 /**
  * PHY_QueryBBReg_8723B - Read "specific bits" from BB register.
  * @Adapter:
@@ -46,10 +45,8 @@ u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
 	BitShift = phy_CalculateBitShift(BitMask);
 
 	return (OriginalValue & BitMask) >> BitShift;
-
 }
 
-
 /**
  * PHY_SetBBReg_8723B - Write "Specific bits" to BB register (page 8~).
  * @Adapter:
@@ -80,10 +77,8 @@ void PHY_SetBBReg_8723B(
 	}
 
 	rtw_write32(Adapter, RegAddr, Data);
-
 }
 
-
 /*  */
 /*  2. RF register R/W API */
 /*  */
@@ -141,7 +136,6 @@ static u32 phy_RFSerialRead_8723B(
 		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
 	}
 	return retValue;
-
 }
 
 /**
@@ -210,7 +204,6 @@ static void phy_RFSerialWrite_8723B(
 	PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 }
 
-
 /**
  * PHY_QueryRFReg_8723B - Query "Specific bits" to RF register (page 8~).
  * @Adapter:
@@ -272,12 +265,10 @@ void PHY_SetRFReg_8723B(
 	phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
 }
 
-
 /*  */
 /*  3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
 /*  */
 
-
 /*-----------------------------------------------------------------------------
  * PHY_MACConfig8192C - Config MAC by header file or parameter file.
  *
@@ -329,7 +320,6 @@ static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
 	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
-
 }
 
 static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
@@ -373,7 +363,6 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
 	return _SUCCESS;
 }
 
-
 int PHY_BBConfig8723B(struct adapter *Adapter)
 {
 	int	rtStatus = _SUCCESS;
@@ -614,7 +603,6 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
 	u8 SubChnlNum = 0;
 	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 
-
 	/* 3 Set Reg668 Reg440 BW */
 	phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
 
@@ -725,13 +713,11 @@ static void PHY_HandleSwChnlAndSetBW8723B(
 	if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
 		return;
 
-
 	if (pHalData->bSwChnl) {
 		pHalData->CurrentChannel = ChannelNum;
 		pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
 	}
 
-
 	if (pHalData->bSetChnlBW) {
 		pHalData->CurrentChannelBW = ChnlWidth;
 		pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
-- 
2.53.0

Re: [PATCH 0/3] staging: rtl8723bs: coding style cleanups for rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@gmail.com>
>
> This patch series fixes various coding style issues in rtl8723b_phycfg.c
> as reported by checkpatch.pl
>
> The changes include:
> - Fixing spacing around binary and bitwise operators.
> - Formatting type casts and aligning function parameters.
> - Removing unnecessary blank lines to improve code readability.
>
> These are purely cosmetic changes to bring the driver closer to the
> Linux kernel coding style.
>
> I wanted to contribute to Linux, but in the end, I could only make a small change. I'm sorry.

All contributions are welcome :)
My reviews will be sent shortly.

>
> tas0dev (3):
>   staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c
>   staging: rtl8723bs: fix casting and alignment spacing in
>     rtl8723b_phycfg.c
>   staging: rtl8723bs: remove unnecessary blank lines in
>     rtl8723b_phycfg.c
>
>  .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   | 65 ++++++++-----------
>  1 file changed, 26 insertions(+), 39 deletions(-)

Re: [PATCH 1/3] staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@gmail.com>
>
> Fix various spacing issues reported by checkpatch.pl to improve code
> readability and conform to the Linux kernel coding style.
>
> Specifically, this patch:
> - Adds missing spaces around binary operators (| , >> , << , + , &).
> - Corrects the spacing in bitwise expressions within function calls.
> - Ensures consistent use of whitespace in arithmetic operations.
>
I think this section above is unnecessary as you have already mentioned 
that this patch handles spacing.
> These changes are purely cosmetic and do not alter the functional
> behavior of the driver.
>
> Signed-off-by: tas0dev <osjin83@gmail.com>
Your Signed-off-by tag must use you real name(First Last) to comply 
with the Developers Certificate of Origin. You should also use your
real name for sending emails.
> ---
>  .../staging/rtl8723bs/hal/rtl8723b_phycfg.c   | 44 +++++++++----------
>  1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> index 7fac1c2ba8e0..cfa00775341b 100644
> --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> @@ -19,7 +19,7 @@ static	u32 phy_CalculateBitShift(u32 BitMask)
>  	u32 i;
>  
>  	for (i = 0; i <= 31; i++) {
> -		if (((BitMask>>i) &  0x1) == 1)
> +		if (((BitMask >> i) &  0x1) == 1)
>  			break;
>  	}
>  	return i;
> @@ -109,18 +109,18 @@ static u32 phy_RFSerialRead_8723B(
>  	NewOffset = Offset;
>  
>  	if (eRFPath == RF_PATH_A) {
> -		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
> -		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
> +		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
> +		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
>  	} else {
> -		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	/* T65 RF */
> -		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
> +		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
> +		PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
>  	}
>  
> -	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
> -	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
> -	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
> +	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
> +	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
> +	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
>  
>  	udelay(10);
>  
> @@ -129,16 +129,16 @@ static u32 phy_RFSerialRead_8723B(
>  	udelay(10);
>  
>  	if (eRFPath == RF_PATH_A)
> -		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
> +		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
>  	else if (eRFPath == RF_PATH_B)
> -		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
> +		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
>  
>  	if (RfPiEnable) {
>  		/*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
> -		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
> +		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
>  	} else {
>  		/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
> -		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
> +		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
>  	}
>  	return retValue;
>  
> @@ -203,7 +203,7 @@ static void phy_RFSerialWrite_8723B(
>  	/*  */
>  	/*  Put write addr in [5:0]  and write data in [31:16] */
>  	/*  */
> -	DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;	/*  T65 RF */
> +	DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;	/*  T65 RF */
>  	/*  */
>  	/*  Write Operation */
>  	/*  */
> @@ -266,7 +266,7 @@ void PHY_SetRFReg_8723B(
>  	if (BitMask != bRFRegOffsetMask) {
>  		Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
>  		BitShift =  phy_CalculateBitShift(BitMask);
> -		Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
> +		Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
>  	}
>  
>  	phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
> @@ -385,11 +385,11 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
>  
>  	/*  Enable BB and RF */
>  	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
> -	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
> +	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1));
>  
>  	rtw_write32(Adapter, 0x948, 0x280);	/*  Others use Antenna S1 */
>  
> -	rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
> +	rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
>  
>  	msleep(1);
>  
> @@ -397,7 +397,7 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
>  
>  	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
>  
> -	rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
> +	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
>  
>  	/*  */
>  	/*  Config BB and AGC */
> @@ -631,7 +631,7 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
>  
>  		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
>  
> -		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
> +		PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
>  		break;
>  
>  	/* 40 MHz channel*/
> @@ -641,11 +641,11 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
>  		PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
>  
>  		/*  Set Control channel to upper or lower. These settings are required only for 40MHz */
> -		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
> +		PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
>  
>  		PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
>  
> -		PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
> +		PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
>  		break;
>  	default:
>  		break;

Re: [PATCH 2/3] staging: rtl8723bs: fix casting and alignment spacing in rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@gmail.com>
>
> Clean up spacing issues related to type casting and function parameter
> alignment as flagged by checkpatch.pl.
>
> Specifically, this patch:
> - Removes the unnecessary space between a type cast and the variable,
>   changing "(u8) value" to "(u8)value".
> - Adjusts the alignment of arguments in function calls to match the
>   open parenthesis.
Also is this above same as thing under this comment as it accounts 
for the same change?
> - Standardizes the formatting of multi-line function parameters for
>   better readability.
You should follow the rule of atomic patch per logical change, which 
means that you should split this patch into multiple patches. One
for unnecessary spaces and one for breaking rtw_write8 line.
>
> These changes are stylistic improvements and have no impact on the
> runtime logic of the driver.
>
> Signed-off-by: tas0dev <osjin83@gmail.com>
Your Signed-off-by tag must use you real name(First Last) to comply 
with the Developers Certificate of Origin. You should also use your
real name for sending emails.
> ---
>  drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> index cfa00775341b..498f7b25a2b5 100644
> --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> @@ -395,7 +395,8 @@ int PHY_BBConfig8723B(struct adapter *Adapter)
>  
>  	PHY_SetRFReg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
>  
> -	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
> +	rtw_write8(Adapter, REG_SYS_FUNC_EN,
> +		   FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
>  
>  	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
>  
> @@ -531,7 +532,7 @@ u8 PHY_GetTxPowerIndex(
>  	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
>  	s8 txPower = 0, powerDiffByRate = 0, limit = 0;
>  
> -	txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
> +	txPower = (s8)PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel);
>  	powerDiffByRate = PHY_GetTxPowerByRate(padapter, RF_PATH_A, Rate);
>  
>  	limit = phy_get_tx_pwr_lmt(
> @@ -551,7 +552,7 @@ u8 PHY_GetTxPowerIndex(
>  	if (txPower > MAX_POWER_INDEX)
>  		txPower = MAX_POWER_INDEX;
>  
> -	return (u8) txPower;
> +	return (u8)txPower;
>  }
>  
>  void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)

Re: [PATCH 3/3] staging: rtl8723bs: remove unnecessary blank lines in rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@gmail.com>
>
> Remove unnecessary blank lines throughout rtl8723b_phycfg.c to clean
> up the code and adhere to the Linux kernel coding style.
>
> Signed-off-by: tas0dev <osjin83@gmail.com>
Your Signed-off-by tag must use you real name(First Last) to comply 
with the Developers Certificate of Origin. You should also use your
real name for sending emails.
> ---
>  drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c | 14 --------------
>  1 file changed, 14 deletions(-)
>
> diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> index 498f7b25a2b5..10eb96105f83 100644
> --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c
> @@ -25,7 +25,6 @@ static	u32 phy_CalculateBitShift(u32 BitMask)
>  	return i;
>  }
>  
> -
>  /**
>   * PHY_QueryBBReg_8723B - Read "specific bits" from BB register.
>   * @Adapter:
> @@ -46,10 +45,8 @@ u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
>  	BitShift = phy_CalculateBitShift(BitMask);
>  
>  	return (OriginalValue & BitMask) >> BitShift;
> -
>  }
>  
> -
>  /**
>   * PHY_SetBBReg_8723B - Write "Specific bits" to BB register (page 8~).
>   * @Adapter:
> @@ -80,10 +77,8 @@ void PHY_SetBBReg_8723B(
>  	}
>  
>  	rtw_write32(Adapter, RegAddr, Data);
> -
>  }
>  
> -
>  /*  */
>  /*  2. RF register R/W API */
>  /*  */
> @@ -141,7 +136,6 @@ static u32 phy_RFSerialRead_8723B(
>  		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
>  	}
>  	return retValue;
> -
>  }
>  
>  /**
> @@ -210,7 +204,6 @@ static void phy_RFSerialWrite_8723B(
>  	PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
>  }
>  
> -
>  /**
>   * PHY_QueryRFReg_8723B - Query "Specific bits" to RF register (page 8~).
>   * @Adapter:
> @@ -272,12 +265,10 @@ void PHY_SetRFReg_8723B(
>  	phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
>  }
>  
> -
>  /*  */
>  /*  3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
>  /*  */
>  
> -
>  /*-----------------------------------------------------------------------------
>   * PHY_MACConfig8192C - Config MAC by header file or parameter file.
>   *
> @@ -329,7 +320,6 @@ static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
>  	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
>  	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
>  	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
> -
>  }
>  
>  static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
> @@ -373,7 +363,6 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
>  	return _SUCCESS;
>  }
>  
> -
>  int PHY_BBConfig8723B(struct adapter *Adapter)
>  {
>  	int	rtStatus = _SUCCESS;
> @@ -614,7 +603,6 @@ static void phy_PostSetBwMode8723B(struct adapter *Adapter)
>  	u8 SubChnlNum = 0;
>  	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
>  
> -
>  	/* 3 Set Reg668 Reg440 BW */
>  	phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
>  
> @@ -725,13 +713,11 @@ static void PHY_HandleSwChnlAndSetBW8723B(
>  	if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
>  		return;
>  
> -
>  	if (pHalData->bSwChnl) {
>  		pHalData->CurrentChannel = ChannelNum;
>  		pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
>  	}
>  
> -
>  	if (pHalData->bSetChnlBW) {
>  		pHalData->CurrentChannelBW = ChnlWidth;
>  		pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;

Re: [PATCH 0/3] staging: rtl8723bs: coding style cleanups for rtl8723b_phycfg.c

[Luka Gejak]

On Wed Apr 8, 2026 at 12:32 PM CEST, osjin83 wrote:
> From: tas0dev <osjin83@gmail.com>
>
> This patch series fixes various coding style issues in rtl8723b_phycfg.c
> as reported by checkpatch.pl
>

...

Also one more thing, when submiting patches make sure that all messages 
are wraped at 70-72 characters.
Best regards,
Luka Gejak