From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A3B2EB5A1 for ; Mon, 5 Jan 2026 15:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767628366; cv=none; b=iV8hNKyVvQ0IeiZhWY9hubsYzm6NsKFoZSUbAlFmEQMPAbdzJwV37hGYkcNKvAXqAgllkJkiebwfX5FypvmqtUJwX2cRip20b2hi59W2QcBIvMrQ4vW+TjrR0qJhvnESU29Gw0UaQqTPgGZZrCTRiSKEnCyRkfiOGb3MwuoSyCc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767628366; c=relaxed/simple; bh=m9e9DIlJ/pYKWW7t8Lu0hofeC3X55rgFKER632Qvmnc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bY+R+KRRAdxIJuce8bS+Xd8I96T+Vx9ZgkPCFgO256XctpTHh1wsiUanfOtzRNLHfyz/T7p3i771pWAbr2KfyyxQxIqlFaRWwKMCL2IghTkIbKHrXS/rLmTwKBdGW9tV+jU08agDuGbK8jzTiwkpHnXtPnReyLXUc7xeE+L68Ik= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iYRC4obx; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iYRC4obx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767628365; x=1799164365; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=m9e9DIlJ/pYKWW7t8Lu0hofeC3X55rgFKER632Qvmnc=; b=iYRC4obxfgumMl3vCctSVzFrWnnfXu2L0udU4EzyThQGQfA3i5i4xJ1k WpLiGBC2gGN61qcpAQfCmxsWSwPxWtHlojdNVv6uWj8+64gGP4LEgheLH Kk8goRABbdHoCv3gKv6NFrFP7Tuw7U6GMygvIytCGFqPYMCYn7nTH9j5B SgxGWUo0AFTlupBARQxlx5qfBp1AYbtH0+oQgXqf2htyDsTBJdYLULFIU qfx4wd/cYH3uc5E/XXwxZLCBroYa57ZUv0JWjzTJ8iH/BgH7KrshC9PAg r9RiThNwRZlAi0SHmPiw0J0FLzl3cQ0+NZvT2OqPcVTrOsSFtdHYXjmbX w==; X-CSE-ConnectionGUID: 5TmZBUgpSP29Uk0vjOBYag== X-CSE-MsgGUID: AQqk3R+KReuIvfk7J6yJYA== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="68005935" X-IronPort-AV: E=Sophos;i="6.21,203,1763452800"; d="scan'208";a="68005935" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2026 07:52:44 -0800 X-CSE-ConnectionGUID: TrkGWDyMQ+mMXGGUmgQFPQ== X-CSE-MsgGUID: vbjSLmRoTKK2VrXnxrdy6A== X-ExtLoop1: 1 Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.215]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2026 07:52:41 -0800 Date: Mon, 5 Jan 2026 17:52:39 +0200 From: Andy Shevchenko To: Tomas Borquez Cc: Andy Shevchenko , Jonathan Cameron , Greg Kroah-Hartman , Lars-Peter Clausen , Michael Hennerich , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v2 4/6] staging: iio: ad9832: remove dds.h dependency Message-ID: References: <20251230203459.28935-1-tomasborquez13@gmail.com> <20251230203459.28935-5-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Sun, Jan 04, 2026 at 02:25:23AM -0300, Tomas Borquez wrote: > On Wed, Dec 31, 2025 at 12:46:28AM +0200, Andy Shevchenko wrote: > > On Tue, Dec 30, 2025 at 10:35 PM Tomas Borquez wrote: ... > > > +static IIO_DEVICE_ATTR(out_altvoltage0_frequency0, 0200, NULL, ad9832_write, AD9832_FREQ0HM); > > > +static IIO_DEVICE_ATTR(out_altvoltage0_frequency1, 0200, NULL, ad9832_write, AD9832_FREQ1HM); > > > > Any particular point in not using _WO() / _RO() variants of the > > IIO_DEVICE_ATTR_*() macros? > I was looking into this and saw that the definition for both _WO() and _RO() only takes _name and _addr: > > #define IIO_DEVICE_ATTR_WO(_name, _addr) \ > struct iio_dev_attr iio_dev_attr_##_name = IIO_ATTR_WO(_name, _addr) > > So if we use it for frequency0 for example, it assumes the store function > since we don't pass it: > > static IIO_DEVICE_ATTR_WO(out_altvoltage0_frequency0, AD9832_FREQ0HM); > > // Expands to > struct iio_dev_attr iio_dev_attr_out_altvoltage0_frequency0 = { > .dev_attr = { > . attr = { > ... > .store = out_altvoltage0_frequency0_store, > } > } > } > > Meaning we would have to create a store for each one instead of using > just one write function Yes, and it will be fine, no? Explicit is better than implicit (at least in this case). -- With Best Regards, Andy Shevchenko