From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F77A38B7DA for ; Tue, 10 Mar 2026 11:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773142179; cv=none; b=gTVs3EHx4rFOD4yH1ATKr6HcXWcbv+/807Olzrzln+JS0ffK/F9HqNf907y/DO4O+Q/qvmFaKH2Tsq5kO2Adn5qQkqIF5YuiAjBBgn+gHuo6SWd2aH0gGRPpptYl/15WUiYMt80KZyH++NeV3vkqrWo1WP8eyh2zqYDa0oBgi5Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773142179; c=relaxed/simple; bh=xSl0s2zz+wo+86PP+k37aIc2ft2S7nYDHzhdwHaCql4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=C+eNC8wdBlVLG0R035uzojTNoDJvvGt827LFWHfpeoVUEOH5Z5xeZgZbqXayYxw3mobz4KA7FH7chcU42oPTCwUF53QM3xTZb4r9ZT3O9tKiaX2j8GpDvrxZ/tkgK+O4qbqJQy/k1ClW0AMJaXMzim7ihP1qN3MdSb88WDPu/Dw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ceN8YLsS; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ceN8YLsS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773142179; x=1804678179; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=xSl0s2zz+wo+86PP+k37aIc2ft2S7nYDHzhdwHaCql4=; b=ceN8YLsSKwQRbLohp2wXFzs3DWpm1iHFXD2PWF7buyTWSKbWyDlSQDxZ A8ZMdiEVEJuKlkgC/XjkUVUZsa/gaCrBpJxiacs4XRtTdZ7QMzEvL0NMi xZ8VuwHBoG12WNhJupcWmcfdbwI4+OlXfTZ5ih4U17Q2iEJTvnBi7IFKU rE3rLoMKdw1SwMLCK1F2KTbWoyC1QPfaGhmKRjPi3R7hHuBB++3AVoE7w 38xMgWkD6a9lrqPQHiockaU55iiKHj7/Q/CsbAjw52Y8tBJcW31/6DWRt eAxtB6tNV7WPogZNneheFJ+BQ1v2mRV2vhyXK3MEmcWQN/jTV9EGHJfJ6 g==; X-CSE-ConnectionGUID: 7NRUWt1KRN+1QiByZEenDA== X-CSE-MsgGUID: gd8WJLpYTV6TfiB1ql/i7g== X-IronPort-AV: E=McAfee;i="6800,10657,11724"; a="73885098" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="73885098" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 04:29:39 -0700 X-CSE-ConnectionGUID: 9TiaZRgwTEe5FUQa9byevg== X-CSE-MsgGUID: 6jslkUWMQsmiKmqKdWFrmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="250561422" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.244.54]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 04:29:36 -0700 Date: Tue, 10 Mar 2026 13:29:32 +0200 From: Andy Shevchenko To: Michael Harris Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Greg Kroah-Hartman , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , linux-iio@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/4] staging: iio: adt7316: remove shift/offset macros Message-ID: References: <20260305-adt7316-correct-macros-v2-0-3702e3841c42@gmail.com> <20260305-adt7316-correct-macros-v2-2-3702e3841c42@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Mar 09, 2026 at 06:32:36PM -0700, Michael Harris wrote: > On 3/6/26 6:53 AM, Andy Shevchenko wrote: ... > >> #include > >> #include > >> #include > >> +#include > > > > Try to squeeze it to make a longest (but sparse AFAICS) ordered list of > > inclusions. With given context > > > > #include > > #include > > #include > > #include > > > > gives 3 out of 4 in order. > > Placing it there would put it right below slab.h, sysfs.h, and list.h. > The includes as a whole are fairly messy and unorganized and I don't > think there's a clean area where I could insert it. Fully reordering it > would be out of scope for this patch series. If you prefer, I can put it > at the top of the includes since it would be the highest alphabetically. As I pointed out "with the given context", meaning that you might find better place. The idea is to have the longest ordered chain even if it's interrupted by some unordered items. ... > >> - data = msb << ADT7316_T_VALUE_FLOAT_OFFSET; > >> + data = FIELD_PREP(ADT7316_AD_MSB_MASK, msb); > >> data |= lsb & ADT7316_LSB_IN_TEMP_MASK; > > > > Ditto and so on... > > The main purpose of this patch was to delete the offset/shift macros, > so I only applied the bitfield macros to areas that were using those > offsets or shifts. I left that existing bitwise operation there because > it wasn't affected by the offsets or shifts. If you'd prefer, I can > update it in this case for the sake of symmetry. The idea is to be consistent. If we change to bitfield,h somewhere else, it probably better to cover the whole driver at the same time. -- With Best Regards, Andy Shevchenko