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Fri, 02 Oct 2026 00:39:51 -0700 (PDT) Received: from debian ([2804:14d:9ea1:8718:c77c:8:a40d:84f2]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5da568a76f6sm2631074e0c.0.2026.10.02.00.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2026 00:39:50 -0700 (PDT) Date: Fri, 2 Oct 2026 04:39:46 -0300 From: Leonardo Martins Martins To: Greg Kroah-Hartman Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/3] staging: rtl8723bs: refactor PHY_ConvertTxPowerLimitToPowerIndex() Message-ID: References: <20261002-rtl8723bs-tx-pwr-limit-v2-0-48b180fb6f7f@gmail.com> <2026100211-scenic-eligibly-58f5@gregkh> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2026100211-scenic-eligibly-58f5@gregkh> > When doing logic refactoring, testing on the real hardware is best. Makes sense, so should I be dropping patch 2 where the logic is refactored, but still do patch 3 where the inner loop is extracted into __phy_tx_power_limit_to_index() to reduce all the indentations? Best Regards, Leonardo Martins