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Thu, 26 Feb 2026 09:52:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772095969; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:content-language:in-reply-to:references; bh=cqoaeSOvXhitA2HXEQSMccZTdcMAnAelkKxEfxzuAyU=; b=ceyG5wRzBUSZDZJd8vq7QFyD7UyDmJWfbAJfQwYXtJD5prIhqEEhLjgfJAd91y1drMc6ok 5joGS6f7f7IZw+nshB+ezUhebo+tXOx9SWIMOZzgHJy4iT0fgqjqq6xW9JcuWTQ0m//H+S rs0bxqV8/j1NBG7vicb5BdxG7z3LOTnrhB4jL1kVWwXm0xbaoRkMoCY7S8X+CwWL08o9Im IIho6/U9V1KZ1GhuS8YjOT2lPxuIVXxfTseoQMd+fODg52SyC+8/MgPXm8w+7xWcA8e2pA 7oVSpwrAYVkmsDZgVFn/tlXtI71scFC9fhjX6bEwIDlFn/fBzfXZtgFhNGXkog== Message-ID: <11efec54-6d13-4ca1-a11b-f91da9e1306b@bootlin.com> Date: Thu, 26 Feb 2026 09:52:43 +0100 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/4] Introduce Allwinner H616 PWM controller To: John Stultz Cc: =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Paul Kocialkowski , Thomas Petazzoni , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org References: <20260123093322.1327389-1-richard.genoud@bootlin.com> From: Richard GENOUD Content-Language: en-US, fr Organization: Bootlin In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Le 23/02/2026 à 21:14, John Stultz a écrit : > On Fri, Jan 23, 2026 at 1:33 AM Richard Genoud > wrote: >> >> Allwinner H616 PWM controller is quite different from the A10 one. >> >> It can drive 6 PWM channels, and like for the A10, each channel has a >> bypass that permits to output a clock, bypassing the PWM logic, when >> enabled. >> >> But, the channels are paired 2 by 2, sharing a first set of >> MUX/prescaler/gate. >> Then, for each channel, there's another prescaler (that will be bypassed >> if the bypass is enabled for this channel). >> >> It looks like that: >> _____ ______ ________ >> OSC24M --->| | | | | | >> APB1 ----->| Mux |--->| Gate |--->| /div_m |-----> PWM_clock_src_xy >> |_____| |______| |________| >> ________ >> | | >> +->| /div_k |---> PWM_clock_x >> | |________| >> | ______ >> | | | >> +-->| Gate |----> PWM_bypass_clock_x >> | |______| >> PWM_clock_src_xy -----+ ________ >> | | | >> +->| /div_k |---> PWM_clock_y >> | |________| >> | ______ >> | | | >> +-->| Gate |----> PWM_bypass_clock_y >> |______| >> >> Where xy can be 0/1, 2/3, 4/5 >> >> PWM_clock_x/y serve for the PWM purpose. >> PWM_bypass_clock_x/y serve for the clock-provider purpose. >> The common clock framework has been used to manage those clocks. >> >> This PWM driver serves as a clock-provider for PWM_bypass_clocks. >> This is needed for example by the embedded AC300 PHY which clock comes >> from PMW5 pin (PB12). >> >> Usually, to get a clock from a PWM driver, we use the pwm-clock driver >> so that the PWM driver doesn't need to be a clk-provider itself. >> While this works in most cases, here it just doesn't. >> That's because the pwm-clock request a period from the PWM driver, >> without any clue that it actually wants a clock at a specific frequency, >> and not a PWM signal with duty cycle capability. >> So, the PWM driver doesn't know if it can use the bypass or not, it >> doesn't even have the real accurate frequency information (23809524 Hz >> instead of 24MHz) because PWM drivers only deal with periods. >> >> With pwm-clock, we loose a precious information along the way (that we >> actually want a clock and not a PWM signal). >> That's ok with simple PWM drivers that don't have multiple input clocks, >> but in this case, without this information, we can't know for sure which >> clock to use. >> And here, for instance, if we ask for a 24MHz clock, pwm-clock will >> requests 42ns (assigned-clocks doesn't help for that matter). The logic >> is to select the highest clock (100MHz) with no prescaler and a duty >> cycle value of 2/4 => we have 25MHz instead of 24MHz. >> And that's a perfectly fine choice for a PMW, because we still can >> change the duty cycle in the range [0-4]/4. >> But obviously for a clock, we don't care about the duty cycle, but more >> about the clock accuracy. >> >> And actually, this PWM is really a PWM AND a real clock when the bypass >> is set. > > During my free/personal time this weekend I was tinkering with Orange > Pi Zero 2w and was able to use this patch series (along with an > hdmi-phy patch and some dts changes) to get HDMI working on the > device. > I'm eager to see these land! > > Tested-by: John Stultz That's great, thanks for testing! > > thanks > -john > -- Richard Genoud, Bootlin Embedded Linux and Kernel engineering https://bootlin.com