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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6eb3efe0c9csm31660146d6.95.2025.03.23.05.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 05:15:49 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Tom Rini , Andre Przywara Cc: Simon Glass , Mikhail Kalashnikov , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 13/34] sunxi: spl: add support for Allwinner A523 watchdog Date: Sun, 23 Mar 2025 13:15:46 +0100 Message-ID: <13723892.uLZWGnKmhe@jernej-laptop> In-Reply-To: <20250323113544.7933-14-andre.przywara@arm.com> References: <20250323113544.7933-1-andre.przywara@arm.com> <20250323113544.7933-14-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne nedelja, 23. marec 2025 ob 12:35:23 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > From: Jernej Skrabec >=20 > The watchdog in the Allwinner A523 SoC differs a bit from the one in the > previous SoCs: it lives in a separate register frame, so no longer > inside some timer device, and it manages to shuffle around some > registers a bit. >=20 > Provide a new struct describing the register layout, and adjust the > address calculation in the SPL code accoringly. This is guarded by the > MACH_SUN55I_A523 Kconfig variable. This one is missing SoB, apparently by me :) > --- > arch/arm/include/asm/arch-sunxi/watchdog.h | 12 ++++++++++++ > arch/arm/mach-sunxi/board.c | 6 ++++++ > 2 files changed, 18 insertions(+) >=20 > diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/includ= e/asm/arch-sunxi/watchdog.h > index 38e2ef2aca3..96d5725141e 100644 > --- a/arch/arm/include/asm/arch-sunxi/watchdog.h > +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h > @@ -26,6 +26,18 @@ struct sunxi_wdog { > u32 res[2]; > }; > =20 > +#elif defined(CONFIG_MACH_SUN55I_A523) > + > +struct sunxi_wdog { > + u32 irq_en; /* 0x00 */ > + u32 irq_sta; /* 0x04 */ > + u32 srst; /* 0x08 */ > + u32 ctl; /* 0x0c */ > + u32 cfg; /* 0x10 */ > + u32 mode; /* 0x14 */ > + u32 ocfg; /* 0x18 */ > +}; Anyway, since you announced battle against C structures for register layout, it seems contraproductive to add it here. What do you think? Best regards, Jernej > + > #else > =20 > #define WDT_CFG_RESET (0x1) > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index 701899ee4b2..89aea61e8e8 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -495,6 +495,12 @@ void reset_cpu(void) > /* sun5i sometimes gets stuck without this */ > writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); > } > +#elif defined(CONFIG_MACH_SUN55I_A523) > + static const struct sunxi_wdog *wdog =3D > + (struct sunxi_wdog *)SUNXI_TIMER_BASE; > + > + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->srst); > + while (1) { } > #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) |= | defined(CONFIG_SUNXI_GEN_NCAT2) > #if defined(CONFIG_MACH_SUN50I_H6) > /* WDOG is broken for some H6 rev. use the R_WDOG instead */ >=20