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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id z14-20020a170906944e00b006f38c33b6e3sm5970246ejx.68.2022.04.27.22.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 22:45:34 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Joerg Roedel , Will Deacon , iommu@lists.linux-foundation.org, Samuel Holland Cc: Heiko Stuebner , Palmer Dabbelt , linux-riscv@lists.infradead.org, Samuel Holland , Chen-Yu Tsai , Krzysztof Kozlowski , Maxime Ripard , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 0/5] iommu/sun50i: Allwinner D1 support Date: Thu, 28 Apr 2022 07:45:33 +0200 Message-ID: <1849776.IobQ9Gjlxr@jernej-laptop> In-Reply-To: <20220428010401.11323-1-samuel@sholland.org> References: <20220428010401.11323-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Hi Samuel! Dne =C4=8Detrtek, 28. april 2022 ob 03:03:55 CEST je Samuel Holland napisal= (a): > D1 is a RISC-V SoC from Allwinner's sunxi family. This series adds IOMMU > binding and driver support. >=20 > One piece is still missing to use the IOMMU for DMA allocations: a call > to iommu_setup_dma_ops(). On ARM64 this is handled by the architecture's > code. RISC-V does not currently select ARCH_HAS_SETUP_DMA_OPS, but it > will once Zicbom support[1] is merged. >=20 > [1]: https://lore.kernel.org/lkml/20220307224620.1933061-2-heiko@sntech.d= e/ >=20 > So I cannot follow virtio-iommu.c and call iommu_setup_dma_ops() when > ARCH_HAS_SETUP_DMA_OPS=3Dn. However, if I apply the following patch on top > of Heiko's non-coherent DMA series, the display engine successfully uses > the IOMMU to allocate its framebuffer: Did you test this on any other device than display pipeline? It should be=20 supported by Cedrus too, right? I think there are still some corner cases t= o=20 fix on Cedrus before IOMMU fully works. Best regards, Jernej >=20 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -6,6 +6,7 @@ > */ >=20 > #include > +#include > #include > #include >=20 > @@ -53,4 +54,7 @@ > { > /* If a specific device is dma-coherent, set it here */ > dev->dma_coherent =3D coherent; > + > + if (iommu) > + iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); > } >=20 >=20 > Samuel Holland (5): > dt-bindings: iommu: sun50i: Add compatible for Allwinner D1 > iommu/sun50i: Support variants without an external reset > iommu/sun50i: Ensure bypass is disabled > iommu/sun50i: Add support for the D1 variant > iommu/sun50i: Ensure the IOMMU can be used for DMA >=20 > .../iommu/allwinner,sun50i-h6-iommu.yaml | 16 +++++++++++-- > drivers/iommu/Kconfig | 1 + > drivers/iommu/sun50i-iommu.c | 24 +++++++++++++++++-- > 3 files changed, 37 insertions(+), 4 deletions(-)