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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id q18-20020a170906145200b00a3d2d81daafsm6335565ejc.172.2024.02.22.11.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 11:15:26 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Vasily Khoruzhick , Yangtao Li , Chen-Yu Tsai , Samuel Holland , Andre Przywara , Daniel Lezcano Cc: "Rafael J . Wysocki" , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Botka , Maksim Kiselev , Bob McChesney , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616 Date: Thu, 22 Feb 2024 20:15:24 +0100 Message-ID: <1956003.PYKUYFuaPT@jernej-laptop> In-Reply-To: References: <20240219153639.179814-1-andre.przywara@arm.com> <2717467.mvXUDI8C0e@jernej-laptop> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Dne =C4=8Detrtek, 22. februar 2024 ob 19:44:12 CET je Daniel Lezcano napisa= l(a): > On 22/02/2024 19:26, Jernej =C5=A0krabec wrote: > > Dne ponedeljek, 19. februar 2024 ob 16:36:33 CET je Andre Przywara napi= sal(a): > >> The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 > >> in the SRAM control block. If bit 16 is set (the reset value), the > >> temperature readings of the THS are way off, leading to reports about > >> 200C, at normal ambient temperatures. Clearing this bits brings the > >> reported values down to the expected values. > >> The BSP code clears this bit in firmware (U-Boot), and has an explicit > >> comment about this, but offers no real explanation. > >> > >> Experiments in U-Boot show that register 0x0 has no effect on the SRAM= C > >> visibility: all tested bit settings still allow full read and write > >> access by the CPU to the whole of SRAM C. Only bit 24 of the register = at > >> offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling > >> the THS switch functionality as an SRAM region would not reflect reali= ty. > >> > >> Since we should not rely on firmware settings, allow other code (the T= HS > >> driver) to access this register, by exporting it through the already > >> existing regmap. This mimics what we already do for the LDO control and > >> the EMAC register. > >> > >> To avoid concurrent accesses to the same register at the same time, by > >> the SRAM switch code and the regmap code, use the same lock to protect > >> the access. The regmap subsystem allows to use an existing lock, so we > >> just need to hook in there. > >> > >> Signed-off-by: Andre Przywara > >=20 > > Reviewed-by: Jernej Skrabec > >=20 > > I guess this one goes through sunxi tree, right? >=20 > I'll pick this patch along with the patch 2-6, so through the thermal=20 > tree. The patch 7/7 will go indeed via the sunxi tree Ok. Best regards, Jernej