From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C56F32C88 for ; Sat, 20 Nov 2021 07:34:54 +0000 (UTC) Received: by mail-wm1-f47.google.com with SMTP id o29so10458476wms.2 for ; Fri, 19 Nov 2021 23:34:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ASlC5C6m5gJ71BapJOvaJHGwBoSPe7ieP2AA6vAXZno=; b=dlwIDWGVloqrbBqRI+ShKyZCLShiBh+hlboknMoVoM1P0kJMYU4Kzixn2WvN9WfWea lXpM8+Xkr40Ijo8gDK+le2MgFM08l4PfAbS81bFVPfRi+S/wonKeYRSyvv/HaMIFeVU3 Auz5MIs+0CJFl+arDQnuiiYV8LzicecgXHQ3ULhIZScEl2MogmbperIFAYuHFrBChwlI oglMyJzv5rwN9ikopUGJ9s8pc1+lIGcwgflMpjgiDj41B7UH3Sg5Q31+OWSd6LlFXeQY 46IYZZertIfffyvHAKX9b3LPMhAR+l0o79vMj3SNHjdgW0RBFztVrOCnxT6fAKia9eSs 2Fgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ASlC5C6m5gJ71BapJOvaJHGwBoSPe7ieP2AA6vAXZno=; b=UkQr2xrmJC7nGD+1M7VBPrXNoLxYXM1dF6dnJv7xjciZQ9pG6gYO5/86WeCAjK3Qmw SimD++iI7QSZnfG8CS0GfT2d2ysjejtT0HVCuDv1A9MzQl0R9DOGOSuqJjN1LZ6Kdu7c EnQrEfg9hNkve9zGnE1NoSIZHNcOb/fqfLhVBvPImFa+ltWXZityS1fDBaqlsLfAI+ic QEk6xVj6ZooH2IPAMIpjwR5MHUTMQOE0wwR5ozOY2Jwgt+h3imF/TkHfJvVQZwRX2JD2 sK3PPlR1l5ZZ0jf36jN74zPMfqIwIGNshICTDKvgF0tJypcrzgN3dIWBDviFpICqC36f 3KZA== X-Gm-Message-State: AOAM533r36nMd8V7nUu+PdVZAVsmdChkLJdKmsWhHjer1rCc7zohv+pH kYttVeWt+CMgr0YfM+e9OqY= X-Google-Smtp-Source: ABdhPJxyLzieymM7+bifW9sxG8pozDBwHv2HD3dn9fJQ6KCugye4Po8a6hhHGQjYlvZa/lLvbQcPlg== X-Received: by 2002:a7b:cc8f:: with SMTP id p15mr8117915wma.158.1637393693154; Fri, 19 Nov 2021 23:34:53 -0800 (PST) Received: from kista.localdomain (cpe-86-58-29-253.static.triera.net. [86.58.29.253]) by smtp.gmail.com with ESMTPSA id a141sm13776345wme.37.2021.11.19.23.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 23:34:52 -0800 (PST) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 0/2] dts: Add CEC clock to DW HDMI Date: Sat, 20 Nov 2021 08:34:46 +0100 Message-Id: <20211120073448.32480-1-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Experimentation proved that CEC controller in H3-like DW-HDMI core depends on 32 kHz clock output from RTC. If board has external 32768 Hz crystal, HDMI CEC always work. However, if external crystal is missing and 32 kHz clock is generated by internal oscillator, CEC communication may or may not work, depending on accuracy. Changing internal oscillator prescaler can make CEC work. This was totally missed when implementing HDMI support, because user manual has no CEC information besides the fact that it exists. Please take a look. Best regards, Jernej Jernej Skrabec (2): arm64: dts: allwinner: a64: Add CEC clock to HDMI ARM: dts: sunxi: Add CEC clock to DW-HDMI arch/arm/boot/dts/sun8i-r40.dtsi | 4 ++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++-- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- 2.34.0