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Date: Tue, 8 Mar 2022 10:42:58 +0000
From: Andre Przywara <andre.przywara@arm.com>
To: Jesse Taube <mr.bossman075@gmail.com>
Cc: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej
 Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>,
 Rob Herring <robh+dt@kernel.org>, Mesih Kilinc <mesihkilinc@gmail.com>,
 Icenowy Zheng <icenowy@aosc.io>, Giulio Benetti
 <giulio.benetti@benettiengineering.com>, George Hilliard
 <thirtythreeforty@gmail.com>, devicetree@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 05/14] ARM: dts: suniv: F1C100: fix CPU node
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On Mon, 7 Mar 2022 21:44:15 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:

Hi,

> On 3/7/22 09:34, Andre Przywara wrote:
> > The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing
> > the reg property, and the corresponding address and size cells
> > properties.
> > 
> > Add them to make the bindings check pass.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >   arch/arm/boot/dts/suniv-f1c100s.dtsi | 4 ++++
> >   1 file changed, 4 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > index 922efd5e9457..43d342eaf661 100644
> > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> > @@ -29,9 +29,13 @@ osc32k: clk-32k {
> >   	};
> >   
> >   	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> >   		cpu {  
> cpu@0

Right, thanks for spotting this. Wondering why make dtbs and make
dtbs_check didn't warn.

> also is memory node required?

As Icenowy said, it's added by U-Boot anyway, filled with the actual
amount of memory. This means you can have a F1C200s instead and it will
work automatically.

Cheers,
Andre

> 
> Thanks,
> jesse
> >   			compatible = "arm,arm926ej-s";
> >   			device_type = "cpu";
> > +			reg = <0x0>;
> >   		};
> >   	};
> >     
>