From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) (using TLSv1.2 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28D587C for ; Fri, 24 Jun 2022 00:03:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656029013; x=1687565013; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=V+hXaNzG1xRg90Us21edRjM0CTBX8UcXbRwupTdVLP4=; b=IGOXFbmfoG5J1w4kEQWBGOvBbgVNwOLgisjzGGuxACCrLjqfADidKsLN 3GDS38xnLHpiQZkH6I38ZwQpDMjtPG/rb6ErrQbInvPXOtvs7SW3NGz51 OES8GUxD5DY1WUMlZmqqjSOFN/LA2c66bZIBdf9C1DWZ7g41C8i4bZziP w=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 23 Jun 2022 17:03:32 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 17:03:31 -0700 Received: from quicinc.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 23 Jun 2022 17:03:31 -0700 Date: Thu, 23 Jun 2022 17:03:30 -0700 From: Guru Das Srinagesh To: Andy Shevchenko CC: Aidan MacDonald , Mark Brown , Andy Gross , Bjorn Andersson , Srinivas Kandagatla , Banajit Goswami , Greg Kroah-Hartman , "Rafael J. Wysocki" , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , MyungJoo Ham , Michael Walle , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Marc Zyngier , Lee Jones , Manivannan Sadhasivam , Cristian Ciocaltea , Chen-Yu Tsai , , , Matti Vaittinen , , , , Jernej Skrabec , Samuel Holland , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , , linux-arm-msm , linux-arm Mailing List , , ALSA Development Mailing List Subject: Re: [PATCH 18/49] mfd: qcom-pm8008: Add broken_mask_unmask irq chip flag Message-ID: <20220624000329.GB21400@quicinc.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> <20220620200644.1961936-19-aidanmacdonald.0x0@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) On Tue, Jun 21, 2022 at 11:35:09AM +0200, Andy Shevchenko wrote: > On Mon, Jun 20, 2022 at 10:08 PM Aidan MacDonald > wrote: > > > > The qcom-pm8008 appears to use "1 to enable" convention for > > enabling interrupts, with separate set and clear registers. > > It's relying on masks and unmasks being inverted from their > > It relies > > > intuitive meaning, so it needs the broken_mask_unmask flag. > > How has it worked until now? It is as Aidan rightly pointed out. When I was writing the pm8008 driver, I found that the mask and unmask terminology used in the framework was inverted when it came to the hardware, so I had to make do and swap them. It works because in regmap_irq_sync_unlock(), the same mask is used to update mask_reg and unmask_reg, except that it is inverted for updating the unmask register. So, by just swapping which register gets updated with the plain mask and which one gets updated with the inverted mask, I could use the framework to accomplish the setting and clearing of the correct registers.