From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 14D147C for ; Tue, 1 Nov 2022 14:17:23 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FC7C23A; Tue, 1 Nov 2022 07:17:29 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 20EBA3F703; Tue, 1 Nov 2022 07:17:21 -0700 (PDT) From: Andre Przywara To: Jernej Skrabec , Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Hans de Goede , Dmitry Torokhov , linux-input@vger.kernel.org Subject: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node Date: Tue, 1 Nov 2022 14:16:58 +0000 Message-Id: <20221101141658.3631342-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221101141658.3631342-1-andre.przywara@arm.com> References: <20221101141658.3631342-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) compatible to the version in other SoCs. The manual doesn't mention the ratio of the input voltage that is used, but comparing actual measurements with the values in the register suggests that it is 3/4 of Vref. Add the DT node describing the base address and interrupt. As in the older SoCs, there is no explicit reset or clock gate, also there is a dedicated, non-multiplexed pin, so need for more properties. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -262,6 +262,14 @@ ir: ir@1c22c00 { status = "disabled"; }; + lradc: lradc@1c23400 { + compatible = "allwinner,suniv-f1c100s-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c23400 0x100>; + interrupts = <22>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; -- 2.25.1