From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A12EF7C for ; Tue, 1 Nov 2022 14:17:16 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CACD113E; Tue, 1 Nov 2022 07:17:16 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8E5093F703; Tue, 1 Nov 2022 07:17:08 -0700 (PDT) From: Andre Przywara To: Jernej Skrabec , Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org Subject: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node Date: Tue, 1 Nov 2022 14:16:51 +0000 Message-Id: <20221101141658.3631342-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221101141658.3631342-1-andre.przywara@arm.com> References: <20221101141658.3631342-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b3..d5a6324e76465 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -192,6 +192,15 @@ wdt: watchdog@1c20ca0 { clocks = <&osc32k>; }; + pwm: pwm@1c21000 { + compatible = "allwinner,suniv-f1c100s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21000 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; -- 2.25.1