Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI

Maxime Ripard
2023-03-21T14:57:43Z

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Hi,

On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
> Set the required PLL rate by adjusting the dotclock rate when calling
> clk_set_rate() when using DSI.
>
> According to the Allwinners A64's BSP code, a TCON divider of 4 has to
> be used and the PLL rate needs to be set to the following frequency when
> using DSI:
> PLL rate = DCLK * bpp / lanes
>
> After this change the common mode set function would only contain
> setting the resolution. Therefore, dissolve the function and transfer
> the functionality to the individual mode set functions.
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>

This is similar to:
https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/

What's the story there?

Maxime

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