Re: [PATCH v3 46/65] clk: at91: smd: Switch to determine_rate

Claudiu.Beznea
2023-05-18T07:39:03Z

On 04.04.2023 13:11, Maxime Ripard wrote:
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>
> The Atmel SAM9x5 SMD clocks implements a mux with a set_parent
> hook, but doesn't provide a determine_rate implementation.
>
> This is a bit odd, since set_parent() is there to, as its name implies,
> change the parent of a clock. However, the most likely candidate to
> trigger that parent change is a call to clk_set_rate(), with
> determine_rate() figuring out which parent is the best suited for a
> given rate.
>
> The other trigger would be a call to clk_set_parent(), but it's far less
> used, and it doesn't look like there's any obvious user for that clock.
>
> So, the set_parent hook is effectively unused, possibly because of an
> oversight. However, it could also be an explicit decision by the
> original author to avoid any reparenting but through an explicit call to
> clk_set_parent().
>
> The driver does implement round_rate() though, which means that we can
> change the rate of the clock, but we will never get to change the
> parent.
>
> However, It's hard to tell whether it's been done on purpose or not.
>
> Since we'll start mandating a determine_rate() implementation, let's
> convert the round_rate() implementation to a determine_rate(), which
> will also make the current behavior explicit. And if it was an
> oversight, the clock behaviour can be adjusted later on.
>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>

> ---
> drivers/clk/at91/clk-smd.c | 29 +++++++++++++++++------------
> 1 file changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
> index 160378438f1b..09c649c8598e 100644
> --- a/drivers/clk/at91/clk-smd.c
> +++ b/drivers/clk/at91/clk-smd.c
> @@ -36,26 +36,31 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
> return parent_rate / (smddiv + 1);
> }
>
> -static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long *parent_rate)
> +static int at91sam9x5_clk_smd_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> {
> unsigned long div;
> unsigned long bestrate;
> unsigned long tmp;
>
> - if (rate >= *parent_rate)
> - return *parent_rate;
> + if (req->rate >= req->best_parent_rate) {
> + req->rate = req->best_parent_rate;
> + return 0;
> + }
>
> - div = *parent_rate / rate;
> - if (div > SMD_MAX_DIV)
> - return *parent_rate / (SMD_MAX_DIV + 1);
> + div = req->best_parent_rate / req->rate;
> + if (div > SMD_MAX_DIV) {
> + req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1);
> + return 0;
> + }
>
> - bestrate = *parent_rate / div;
> - tmp = *parent_rate / (div + 1);
> - if (bestrate - rate > rate - tmp)
> + bestrate = req->best_parent_rate / div;
> + tmp = req->best_parent_rate / (div + 1);
> + if (bestrate - req->rate > req->rate - tmp)
> bestrate = tmp;
>
> - return bestrate;
> + req->rate = bestrate;
> + return 0;
> }
>
> static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
> @@ -98,7 +103,7 @@ static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
>
> static const struct clk_ops at91sam9x5_smd_ops = {
> .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
> - .round_rate = at91sam9x5_clk_smd_round_rate,
> + .determine_rate = at91sam9x5_clk_smd_determine_rate,
> .get_parent = at91sam9x5_clk_smd_get_parent,
> .set_parent = at91sam9x5_clk_smd_set_parent,
> .set_rate = at91sam9x5_clk_smd_set_rate,
>
> --
> 2.39.2
>