From: Roman Beranek <me@crly.cz>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>
Cc: Roman Beranek <me@crly.cz>, Frank Oltmanns <frank@oltmanns.dev>,
Icenowy Zheng <icenowy@aosc.io>, Ondrej Jirman <megi@xff.cz>,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH v3 3/7] arm64: dts: allwinner: a64: assign PLL_MIPI to CLK_TCON0
Date: Thu, 27 Apr 2023 11:16:07 +0200 [thread overview]
Message-ID: <20230427091611.99044-4-me@crly.cz> (raw)
In-Reply-To: <20230427091611.99044-1-me@crly.cz>
Assign pll-mipi parent to tcon0's source clock via 'assigned-clocks'.
Signed-off-by: Roman Beranek <me@crly.cz>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 62f45f71ec65..e6a194db420d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -411,6 +411,8 @@ tcon0: lcd-controller@1c0c000 {
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
+ assigned-clocks = <&ccu CLK_TCON0>;
+ assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
ports {
#address-cells = <1>;
--
2.34.1
next prev parent reply other threads:[~2023-04-27 9:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 9:16 [PATCH v3 0/7] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Roman Beranek
2023-04-27 9:16 ` [PATCH v3 1/7] clk: sunxi-ng: a64: export PLL_MIPI Roman Beranek
2023-04-28 10:07 ` Krzysztof Kozlowski
2023-04-27 9:16 ` [PATCH v3 2/7] clk: sunxi-ng: a64: prevent CLK_TCON0 being reparented Roman Beranek
2023-04-27 9:16 ` Roman Beranek [this message]
2023-04-27 9:27 ` [PATCH v3 3/7] arm64: dts: allwinner: a64: assign PLL_MIPI to CLK_TCON0 Maxime Ripard
2023-04-28 6:37 ` Jernej Škrabec
2023-04-27 9:16 ` [PATCH v3 4/7] arm64: dts: allwinner: a64: reset pll-video0 rate Roman Beranek
2023-04-27 9:31 ` Maxime Ripard
2023-04-28 6:43 ` Jernej Škrabec
2023-04-29 18:28 ` Frank Oltmanns
2023-04-27 9:16 ` [PATCH v3 5/7] ARM: dts: sunxi: rename tcon's clock output Roman Beranek
2023-04-27 9:16 ` [PATCH v3 6/7] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Roman Beranek
2023-04-27 9:16 ` [PATCH v3 7/7] drm: sun4i: calculate proper DCLK rate for DSI Roman Beranek
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