[PATCH 0/4] sunxi: DRAM: H6: fixes and size reduction

[Andre Przywara <andre.przywara@arm.com>]

Hi,

this contains two fixes for the Allwinner H6 DRAM code: patch 1/4 adds a
DSB barrier instruction after the actual DRAM register setup, to make
sure that subsequent DRAM accesses actually match the just programmed
setup. The last patch makes sure the compiler does not optimise away
the MMIO writes for the address map setup.
The middle two patches help to bring the code size down (which would
increase with just patch 4/4): by splitting the parameter struct into a
constant and a dynamic part, we help the compiler with its constant
propagation optimisation, so it can fold some parameters directly into
the code. This helps with the notoriously tight H6 SPL.

Gunjan, please have a look at my version of your original OPi 3 LTS fix
patch 1/4: Does that still work reliably? If not, can you add your
"udelay(50);" right after this new DSB? And maybe experiment with the
duration a bit?

Cheers,
Andre

Andre Przywara (3):
  sunxi: DRAM: H6: const-ify DRAM function parameters
  sunxi: DRAM: H6: split struct dram_para
  sunxi: DRAM: H6: use proper MMIO accessors in mctl_set_addrmap()

Gunjan Gupta (1):
  sunxi: DRAM: H6: add barrier after finishing DRAM setup

 .../include/asm/arch-sunxi/dram_sun50i_h6.h   |  10 +-
 arch/arm/mach-sunxi/dram_sun50i_h6.c          | 243 ++++++++++--------
 .../mach-sunxi/dram_timings/h6_ddr3_1333.c    |   2 +-
 arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c  |   2 +-
 4 files changed, 138 insertions(+), 119 deletions(-)

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2.35.8