From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de, Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Jaehoon Chung <jh80.chung@samsung.com>
Cc: Tom Rini <trini@konsulko.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Cody Eksal <masterr3c0rd@epochal.quest>,
Simon Glass <sjg@chromium.org>,
linux-sunxi@lists.linux.dev, Parthiban <parthiban@linumiz.com>
Subject: [PATCH 5/8] pinctrl: sunxi: add Allwinner A100/A133 pinctrl description
Date: Fri, 17 Jan 2025 01:45:34 +0000 [thread overview]
Message-ID: <20250117014537.22513-6-andre.przywara@arm.com> (raw)
In-Reply-To: <20250117014537.22513-1-andre.przywara@arm.com>
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/pinctrl/sunxi/Kconfig | 10 ++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 +++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index cbd61795986..65e8192a99a 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,6 +124,16 @@ config PINCTRL_SUN50I_H616_R
default MACH_SUN50I_H616
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100/A133 PIO"
+ default MACH_SUN50I_A133
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100/A133 R-PIO"
+ default MACH_SUN50I_A133
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN20I_D1
bool "Support for the Allwinner D1/R528 PIO"
default MACH_SUN8I_R528
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 37ea93715d1..c38edf7d4f5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -774,6 +774,41 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc
.num_banks = 1,
};
+static const struct sunxi_pinctrl_function sun50i_a100_pinctrl_functions[] = {
+ { "emac0", 5 }, /* PH0-PH16 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC0-PC16 */
+ { "spi0", 4 }, /* PC2-PC4, PC7, PC12, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB9-PB10 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_pinctrl_desc = {
+ .functions = sun50i_a100_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a100_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a100_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c0", 2 },
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc = {
+ .functions = sun50i_a100_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a100_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
static const struct udevice_id sunxi_pinctrl_ids[] = {
#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
{
@@ -936,6 +971,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
.compatible = "allwinner,sun50i-h616-r-pinctrl",
.data = (ulong)&sun50i_h616_r_pinctrl_desc,
},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100
+ {
+ .compatible = "allwinner,sun50i-a100-pinctrl",
+ .data = (ulong)&sun50i_a100_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100_R
+ {
+ .compatible = "allwinner,sun50i-a100-r-pinctrl",
+ .data = (ulong)&sun50i_a100_r_pinctrl_desc,
+ },
#endif
{}
};
--
2.46.2
next prev parent reply other threads:[~2025-01-17 1:47 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-17 1:45 [PATCH 0/8] sunxi: (early) Allwinner A133 SoC support Andre Przywara
2025-01-17 1:45 ` [PATCH 1/8] sunxi: clock: improve grouping of default clock register values Andre Przywara
2025-01-18 7:16 ` Jernej Škrabec
2025-01-17 1:45 ` [PATCH 2/8] sunxi: pmic_bus: support alternative I2C address Andre Przywara
2025-01-18 7:21 ` Jernej Škrabec
2025-01-19 22:25 ` Andre Przywara
2025-01-20 16:42 ` Jernej Škrabec
2025-01-20 19:21 ` Simon Glass
2025-01-21 0:05 ` Andre Przywara
2025-01-23 14:37 ` Simon Glass
2025-03-18 0:34 ` Andre Przywara
2025-01-17 1:45 ` [PATCH 3/8] sunxi: H616: DRAM: rename Kconfig parameters to be more generic Andre Przywara
2025-01-18 7:22 ` Jernej Škrabec
2025-01-17 1:45 ` [PATCH 4/8] clk: sunxi: Add support for the A100/A133 CCU Andre Przywara
2025-01-18 7:24 ` Jernej Škrabec
2025-01-17 1:45 ` Andre Przywara [this message]
2025-01-18 7:25 ` [PATCH 5/8] pinctrl: sunxi: add Allwinner A100/A133 pinctrl description Jernej Škrabec
2025-01-17 1:45 ` [PATCH 6/8] power: pmic: sunxi: add SPL support for the AXP803 Andre Przywara
2025-01-18 7:29 ` Jernej Škrabec
2025-01-17 1:45 ` [PATCH 7/8] sunxi: A133: add DRAM init code [WIP!] Andre Przywara
2025-01-18 8:17 ` Jernej Škrabec
2025-01-18 15:20 ` Cody Eksal
2025-01-17 1:45 ` [PATCH 8/8] sunxi: add support for the Allwinner A100/A133 SoC Andre Przywara
2025-01-18 7:35 ` Jernej Škrabec
2025-01-19 23:52 ` Andre Przywara
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