From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6B7561426C for ; Fri, 14 Feb 2025 00:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493604; cv=none; b=Vn8sb1eWjq7mVFDlOKnPxMeHzQUvnuqrH9zu9OjSstbPU2xGJDXyHjT+fV3/P9KGKdiNtEyMLefKM5DijqAPF55+bnl+6Bsq8lSYuBa1QVehHudrVVdWzw+MWawnV2qncwmm99F+9ofjjdFuwHue0UqR0jNY9U76FNUXcFKytFQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739493604; c=relaxed/simple; bh=121spaMlpCdmk+wzfSLjmbf5MLhgPjLXeYoXRdBa9Cw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WDFzpWfUS9omcSR0mcfury6d7oifrSMG1b2lSm0TOh0OMdxlAKiAh5WQItIXH5qMLbIorbv9MGDWwHOE2lL98LQwl1CSeW376a2pp8svyGoIuchphjwRMEj/czxYnoYxpurlp2e8oRngLmMdeeiljRqFmkReNgv09IPIVX45d+0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EFF81A9A; Thu, 13 Feb 2025 16:40:23 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 69B303F5A1; Thu, 13 Feb 2025 16:40:01 -0800 (PST) From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] pinctrl: sunxi: increase number of GPIO bank regulators Date: Fri, 14 Feb 2025 00:37:28 +0000 Message-ID: <20250214003734.14944-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250214003734.14944-1-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit By design, the Allwinner pinctrl IP always supported up to 11 GPIO banks, though no SoC ever used more than 9 banks so far. The Allwinner A523 has pins in all 11 banks, which exceeds the number of per-bank regulators that we currently support, as this was set to 9. Increase the size of the array to hold up to 11 regulator structs, to support pins in bank J and K as well. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 8e2eca45b57f8..fbbf070a87542 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -155,7 +155,7 @@ struct sunxi_pinctrl { struct gpio_chip *chip; const struct sunxi_pinctrl_desc *desc; struct device *dev; - struct sunxi_pinctrl_regulator regulators[9]; + struct sunxi_pinctrl_regulator regulators[11]; struct irq_domain *domain; struct sunxi_pinctrl_function *functions; unsigned nfunctions; -- 2.46.3