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From: Andre Przywara <andre.przywara@arm.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH v2 06/15] clk: sunxi-ng: a523: Add support for bus clocks
Date: Fri, 14 Feb 2025 12:53:50 +0000	[thread overview]
Message-ID: <20250214125359.5204-7-andre.przywara@arm.com> (raw)
In-Reply-To: <20250214125359.5204-1-andre.przywara@arm.com>

Add the basic bus clocks for the Allwinner A523 and T527 SoCs.
This covers the AHB, APB0 and APB1 clocks. Linux is not supposed to
change those clocks, but they are needed as parents for many other mod
clocks.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 39 ++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
index 8374e841e9d82..59f45e7c0904b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -331,6 +331,39 @@ static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x",
 static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x",
 			   &pll_npu_4x_clk.common.hw, 4, 1, 0);
 
+
+/**************************************************************************
+ *                           bus clocks                                   *
+ **************************************************************************/
+
+static const struct clk_parent_data ahb_apb0_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .hw = &pll_periph0_600M_clk.hw },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb0_parents, 0x510,
+				 0, 5,		/* M */
+				 24, 2,		/* mux */
+				 0);
+static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb0_parents, 0x520,
+				 0, 5,		/* M */
+				 24, 2,	/* mux */
+				 0);
+
+static const struct clk_parent_data apb1_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .hw = &pll_periph0_600M_clk.hw },
+	{ .hw = &pll_periph0_480M_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524,
+				 0, 5,		/* M */
+				 24, 3,		/* mux */
+				 0);
+
 /*
  * Contains all clocks that are controlled by a hardware register. They
  * have a (sunxi) .common member, which needs to be initialised by the common
@@ -358,6 +391,9 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 	&pll_ve_clk.common,
 	&pll_audio0_4x_clk.common,
 	&pll_npu_4x_clk.common,
+	&ahb_clk.common,
+	&apb0_clk.common,
+	&apb1_clk.common,
 };
 
 static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -403,6 +439,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
 		[CLK_PLL_NPU_4X]	= &pll_npu_4x_clk.common.hw,
 		[CLK_PLL_NPU_2X]	= &pll_npu_2x_clk.hw,
 		[CLK_PLL_NPU]		= &pll_npu_1x_clk.hw,
+		[CLK_AHB]		= &ahb_clk.common.hw,
+		[CLK_APB0]		= &apb0_clk.common.hw,
+		[CLK_APB1]		= &apb1_clk.common.hw,
 	},
 };
 
-- 
2.46.3


  parent reply	other threads:[~2025-02-14 12:56 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-14 12:53 [PATCH v2 00/15] clk: sunxi-ng: add A523 clock support Andre Przywara
2025-02-14 12:53 ` [PATCH v2 01/15] clk: sunxi-ng: mp: Add SUNXI_CCU_P_DATA_WITH_MUX_GATE wrapper Andre Przywara
2025-02-16  8:39   ` Chen-Yu Tsai
2025-02-14 12:53 ` [PATCH v2 02/15] clk: sunxi-ng: mp: introduce dual-divider clock Andre Przywara
2025-02-16  8:39   ` Chen-Yu Tsai
2025-02-14 12:53 ` [PATCH v2 03/15] clk: sunxi-ng: mp: provide wrapper for setting feature flags Andre Przywara
2025-02-16  8:41   ` Chen-Yu Tsai
2025-02-14 12:53 ` [PATCH v2 04/15] dt-bindings: clk: sunxi-ng: add compatible for the A523 CCU Andre Przywara
2025-02-14 12:53 ` [PATCH v2 05/15] clk: sunxi-ng: Add support for the A523/T527 CCU PLLs Andre Przywara
2025-02-18 19:03   ` Jernej Škrabec
2025-02-28 13:29     ` Andre Przywara
2025-02-14 12:53 ` Andre Przywara [this message]
2025-02-18 19:06   ` [PATCH v2 06/15] clk: sunxi-ng: a523: Add support for bus clocks Jernej Škrabec
2025-02-14 12:53 ` [PATCH v2 07/15] clk: sunxi-ng: a523: add video mod clocks Andre Przywara
2025-02-18 19:26   ` Jernej Škrabec
2025-02-28 13:42     ` Andre Przywara
2025-02-14 12:53 ` [PATCH v2 08/15] clk: sunxi-ng: a523: add system " Andre Przywara
2025-02-18 19:34   ` Jernej Škrabec
2025-02-28 13:43     ` Andre Przywara
2025-02-14 12:53 ` [PATCH v2 09/15] clk: sunxi-ng: a523: add interface " Andre Przywara
2025-02-18 19:42   ` Jernej Škrabec
2025-02-28 13:46     ` Andre Przywara
2025-02-14 12:53 ` [PATCH v2 10/15] clk: sunxi-ng: a523: add USB " Andre Przywara
2025-02-18 19:46   ` Jernej Škrabec
2025-02-14 12:53 ` [PATCH v2 11/15] clk: sunxi-ng: a523: remaining " Andre Przywara
2025-02-18 19:55   ` Jernej Škrabec
2025-02-28 13:50     ` Andre Przywara
2025-02-14 12:53 ` [PATCH v2 12/15] clk: sunxi-ng: a523: add bus clock gates Andre Przywara
2025-02-18 20:12   ` Jernej Škrabec
2025-02-28 14:04     ` Andre Przywara
2025-02-28 14:41       ` Jernej Škrabec
2025-02-14 12:53 ` [PATCH v2 13/15] clk: sunxi-ng: a523: add reset lines Andre Przywara
2025-02-18 20:29   ` Jernej Škrabec
2025-02-28 14:21     ` Andre Przywara
2025-02-14 12:53 ` [PATCH v2 14/15] dt-bindings: clk: sunxi-ng: add compatible for the A523 PRCM-CCU Andre Przywara
2025-02-14 12:53 ` [PATCH v2 15/15] clk: sunxi-ng: add support for the A523/T527 PRCM CCU Andre Przywara
2025-02-18 20:42   ` Jernej Škrabec
2025-02-28 14:33     ` Andre Przywara

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