From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF2D338F9C for ; Fri, 21 Feb 2025 01:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740101971; cv=none; b=OhoE3G50ZLmwYg2jKPhk3BfZKN+ExvSHv1iW6ZcjUHSnOzQwrRDZZ6NFYro+8YalhX4CFUq2lrqVp1+Ul+WNOC/tFQkAer8W4jo1E+SphlO0TOlMwLTzSZ21oYFCDwPq40rAqvzdwvbcTPtMoyNlIhzvM3HU51iGwHrVaezGU2Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740101971; c=relaxed/simple; bh=XidwWYprxvvp9LVHmJrQKB7BF7kwB4sqxfHp3Zc1fQM=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=inlMzixqlbOxmcO38NFlumQx2iZ/sBIzw0gKD51cdRNS3/plEy4rgflhWhuFZ0jkTdOSOXxpLj7wV0LMeRXKhu3oJG6LdS8v12yTdF5lCaNXNs1vmta+CZ+w0KQUxK7hvjVga8js4j6MNdzsAFF1dFZL8wm9T62ayDGOiDUVWc4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E0241BA8; Thu, 20 Feb 2025 17:39:47 -0800 (PST) Received: from minigeek.lan (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4BEF83F59E; Thu, 20 Feb 2025 17:39:27 -0800 (PST) Date: Fri, 21 Feb 2025 01:37:21 +0000 From: Andre Przywara To: Anastasia Belova Cc: Emilio =?UTF-8?B?TMOzcGV6?= , David Laight , Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Hans de Goede , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org Subject: Re: [PATCH] clk: sunxi: clean up rate counting Message-ID: <20250221013721.32468f6c@minigeek.lan> In-Reply-To: <20250203112930.650813-1-abelova@astralinux.ru> References: <20250203112930.650813-1-abelova@astralinux.ru> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 3 Feb 2025 14:29:28 +0300 Anastasia Belova wrote: Hi, > If n = 255, the result of multiplication of n and 24000000 > may not fit int type. Swap division and shift with multiplication. > > Found by Linux Verification Center (linuxtesting.org) with SVACE. I guess this is effectively a v2 of this patch? https://lore.kernel.org/linux-sunxi/20250120084719.63116-1-abelova@astralinux.ru/T/#u In this case, and for the records, I'd like to repeat some comments of mine from this former patch, about this being mostly irrelevant: - PLL4 is PLL_PERIPH0, which is meant to be fixed to 960MHz. Linux would not change this frequency. - the Allwinner A80 is both old and quite rare/obscure: the most prominent board (Cubieboard4) was broken for a while and nobody noticed - this "allwinner,sun9i-a80-pll4-clk" clock is not used by any DT in the kernel, so it's effectively dead code So do we really need this change? Or asked another way: What does this patch fix, exactly? Some comments still, regardless: > Fixes: 6424e0aeebc4 ("clk: sunxi: rewrite sun9i_a80_get_pll4_factors()") > Signed-off-by: Anastasia Belova > --- > drivers/clk/sunxi/clk-sun9i-core.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c > index d93c7a53c6c0..639c83ed63b8 100644 > --- a/drivers/clk/sunxi/clk-sun9i-core.c > +++ b/drivers/clk/sunxi/clk-sun9i-core.c > @@ -25,12 +25,12 @@ > > static void sun9i_a80_get_pll4_factors(struct factors_request *req) > { > - int n; > - int m = 1; > - int p = 1; > + unsigned int n; > + unsigned int m = 1; > + unsigned int p = 1; > > /* Normalize value to a 6 MHz multiple (24 MHz / 4) */ > - n = DIV_ROUND_UP(req->rate, 6000000); > + n = DIV_ROUND_UP(req->rate, 6000000ul); What would the "unsigned long" change here? This is 32-bit code, so int and long are the same size. And regardless, how does changing the divisor type help anyway? > > /* If n is too large switch to steps of 12 MHz */ > if (n > 255) { > @@ -50,7 +50,11 @@ static void sun9i_a80_get_pll4_factors(struct factors_request *req) > else if (n < 12) > n = 12; > > - req->rate = ((24000000 * n) >> p) / (m + 1); > + /* Division and shift should be done before multiplication to > + * avoid overflow. The result will be correct because '>> p' and > + * '/ (m + 1)' are both just conditional 'divide by 2' > + */ > + req->rate = ((24000000ul >> p) / (m + 1)) * n; This looks OKish, since indeed the divisors are just 1 or 2, so we don't lose any precision here. But again: what is "ul" supposed to fix? Also the comment reads slightly wrong to me: Normally division and shift _should_ be done *after* multiplication to avoid loss of precision. The comment here should state that we _can_ do it the other way around here, since the divisors are small and divide the dividend "cleanly". Cheers, Andre > req->n = n; > req->m = m; > req->p = p;