From: Andre Przywara <andre.przywara@arm.com>
To: Paul Kocialkowski <paulk@sys-base.io>
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name
Date: Sat, 5 Jul 2025 15:38:25 +0100 [thread overview]
Message-ID: <20250705153825.2be2b333@minigeek.lan> (raw)
In-Reply-To: <20250704233535.4b026641@minigeek.lan>
On Fri, 4 Jul 2025 23:35:35 +0100
Andre Przywara <andre.przywara@arm.com> wrote:
Hi,
> On Thu, 26 Jun 2025 10:09:19 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> Hi Paul,
>
> > The Allwinner A100/A133 only has a single emac instance, which is
> > referred to as "emac" everywhere. Fix the pin names to drop the
> > trailing "0" that has no reason to be.
>
> Sorry, but this is wrong. There *is* a second EMAC on the A133 die: it's
> indeed not mentioned in the manual, but you can probe its MMIO
> registers (@0x5030000), and there is a second syscon register
> (@0x03000034). It's mentioned in several BSP code places ([1]).
> It seem like no suitable pins are connected on the A133
> package, but that should not affect the A100 .dtsi (we use a similar
> approach for the H616 and A523).
>
> So I think we should keep the emac0 name.
just thinking that it's even worse: this changes the DT visible pinctrl
function name, so it's a DT ABI change. With the "emac0" function name,
Ethernet would work with stable kernels already (as everything is
compatible, it's just about DT changes). But with this change, pinctrl
drivers in older kernels would not match.
So I would very much like to see this patch moved out. Is it just in
LinusW's tree so far? I don't see it in -next yet.
Cheers,
Andre.
> [1]
> https://github.com/qiaoweibiao/T507_Kernel/blob/main/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
>
>
> >
> > Fixes: 473436e7647d ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")
> > Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> > ---
> > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 32 ++++++++++-----------
> > 1 file changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > index b97de80ae2f3..95b764ee1c0d 100644
> > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
> > @@ -546,33 +546,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
> > SUNXI_FUNCTION(0x3, "cir0"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */
> > + SUNXI_FUNCTION(0x5, "emac"), /* CLKIN */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* TX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CS */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -580,14 +580,14 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* RX */
> > SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
> > SUNXI_FUNCTION(0x4, "ledc"),
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -595,7 +595,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
> > SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
> > SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXCTL */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -611,7 +611,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDC */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDC */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -619,7 +619,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
> > SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
> > SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */
> > + SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -642,33 +642,33 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */
> > SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */
> > + SUNXI_FUNCTION(0x5, "emac"), /* EPHY */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
> > SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */
> > + SUNXI_FUNCTION(0x5, "emac"), /* RXCK */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > SUNXI_FUNCTION(0x1, "gpio_out"),
> > SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */
> > SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD3 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
> > @@ -676,7 +676,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
> > SUNXI_FUNCTION(0x2, "cir0"), /* OUT */
> > SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */
> > SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
> > - SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */
> > + SUNXI_FUNCTION(0x5, "emac"), /* TXD2 */
> > SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
> > SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
> > SUNXI_FUNCTION(0x0, "gpio_in"),
>
>
next prev parent reply other threads:[~2025-07-05 14:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 8:09 [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 1/5] pinctrl: sunxi: Fix a100 emac pin function name Paul Kocialkowski
2025-06-28 4:39 ` Chen-Yu Tsai
2025-07-04 8:02 ` Linus Walleij
2025-07-04 22:35 ` Andre Przywara
2025-07-05 14:38 ` Andre Przywara [this message]
2025-07-06 0:00 ` Paul Kocialkowski
2025-07-06 15:04 ` Chen-Yu Tsai
2025-07-07 3:07 ` Chen-Yu Tsai
2025-07-07 9:40 ` Paul Kocialkowski
2025-07-07 9:39 ` Paul Kocialkowski
2025-07-07 9:52 ` Chen-Yu Tsai
2025-07-07 10:13 ` Paul Kocialkowski
2025-07-07 10:22 ` Chen-Yu Tsai
2025-07-07 10:40 ` Paul Kocialkowski
2025-07-07 12:38 ` Andre Przywara
2025-07-07 13:19 ` Paul Kocialkowski
2025-07-07 15:27 ` Chen-Yu Tsai
2025-07-11 18:13 ` Linus Walleij
2025-07-05 23:52 ` Paul Kocialkowski
2025-06-26 8:09 ` [PATCH 2/5] arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII Paul Kocialkowski
2025-07-04 22:45 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 3/5] dt-bindings: net: sun8i-emac: Add A100 EMAC compatible Paul Kocialkowski
2025-06-27 21:21 ` Rob Herring (Arm)
2025-07-04 22:40 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 4/5] arm64: dts: allwinner: a100: Add EMAC support Paul Kocialkowski
2025-07-04 23:32 ` Andre Przywara
2025-06-26 8:09 ` [PATCH 5/5] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support Paul Kocialkowski
2025-06-27 22:40 ` [PATCH 0/5] Allwinner A100/A133 Ethernet MAC (EMAC) Support patchwork-bot+netdevbpf
2025-07-04 15:37 ` (subset) " Chen-Yu Tsai
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